5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
177 Value type: <stringlist>
178 Usage and definition depend on ARM architecture version.
179 # On ARM v8 64-bit this property is required and must
183 # On ARM 32-bit systems this property is optional and
185 "allwinner,sun6i-a31"
187 "marvell,armada-375-smp"
188 "marvell,armada-380-smp"
189 "marvell,armada-xp-smp"
193 "rockchip,rk3066-smp"
196 Usage: required for systems that have an "enable-method"
197 property value of "spin-table".
198 Value type: <prop-encoded-array>
200 # On ARM v8 64-bit systems must be a two cell
201 property identifying a 64-bit zero-initialised
205 Usage: required for systems that have an "enable-method"
206 property value of "qcom,kpss-acc-v1" or
208 Value type: <phandle>
209 Definition: Specifies the SAW[1] node associated with this CPU.
212 Usage: required for systems that have an "enable-method"
213 property value of "qcom,kpss-acc-v1" or
215 Value type: <phandle>
216 Definition: Specifies the ACC[2] node associated with this CPU.
219 Example 1 (dual-cluster big.LITTLE system 32-bit):
223 #address-cells = <1>;
227 compatible = "arm,cortex-a15";
233 compatible = "arm,cortex-a15";
239 compatible = "arm,cortex-a7";
245 compatible = "arm,cortex-a7";
250 Example 2 (Cortex-A8 uniprocessor 32-bit system):
254 #address-cells = <1>;
258 compatible = "arm,cortex-a8";
263 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
267 #address-cells = <1>;
271 compatible = "arm,arm926ej-s";
276 Example 4 (ARM Cortex-A57 64-bit system):
280 #address-cells = <2>;
284 compatible = "arm,cortex-a57";
286 enable-method = "spin-table";
287 cpu-release-addr = <0 0x20000000>;
292 compatible = "arm,cortex-a57";
294 enable-method = "spin-table";
295 cpu-release-addr = <0 0x20000000>;
300 compatible = "arm,cortex-a57";
302 enable-method = "spin-table";
303 cpu-release-addr = <0 0x20000000>;
308 compatible = "arm,cortex-a57";
310 enable-method = "spin-table";
311 cpu-release-addr = <0 0x20000000>;
316 compatible = "arm,cortex-a57";
318 enable-method = "spin-table";
319 cpu-release-addr = <0 0x20000000>;
324 compatible = "arm,cortex-a57";
326 enable-method = "spin-table";
327 cpu-release-addr = <0 0x20000000>;
332 compatible = "arm,cortex-a57";
334 enable-method = "spin-table";
335 cpu-release-addr = <0 0x20000000>;
340 compatible = "arm,cortex-a57";
342 enable-method = "spin-table";
343 cpu-release-addr = <0 0x20000000>;
348 compatible = "arm,cortex-a57";
350 enable-method = "spin-table";
351 cpu-release-addr = <0 0x20000000>;
356 compatible = "arm,cortex-a57";
358 enable-method = "spin-table";
359 cpu-release-addr = <0 0x20000000>;
364 compatible = "arm,cortex-a57";
366 enable-method = "spin-table";
367 cpu-release-addr = <0 0x20000000>;
372 compatible = "arm,cortex-a57";
374 enable-method = "spin-table";
375 cpu-release-addr = <0 0x20000000>;
380 compatible = "arm,cortex-a57";
382 enable-method = "spin-table";
383 cpu-release-addr = <0 0x20000000>;
388 compatible = "arm,cortex-a57";
390 enable-method = "spin-table";
391 cpu-release-addr = <0 0x20000000>;
396 compatible = "arm,cortex-a57";
398 enable-method = "spin-table";
399 cpu-release-addr = <0 0x20000000>;
404 compatible = "arm,cortex-a57";
406 enable-method = "spin-table";
407 cpu-release-addr = <0 0x20000000>;
412 [1] arm/msm/qcom,saw2.txt
413 [2] arm/msm/qcom,kpss-acc.txt