5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
177 Value type: <stringlist>
178 Usage and definition depend on ARM architecture version.
179 # On ARM v8 64-bit this property is required and must
183 # On ARM 32-bit systems this property is optional and
190 Usage: required for systems that have an "enable-method"
191 property value of "spin-table".
192 Value type: <prop-encoded-array>
194 # On ARM v8 64-bit systems must be a two cell
195 property identifying a 64-bit zero-initialised
199 Usage: required for systems that have an "enable-method"
200 property value of "qcom,kpss-acc-v1" or
202 Value type: <phandle>
203 Definition: Specifies the SAW[1] node associated with this CPU.
206 Usage: required for systems that have an "enable-method"
207 property value of "qcom,kpss-acc-v1" or
209 Value type: <phandle>
210 Definition: Specifies the ACC[2] node associated with this CPU.
213 Example 1 (dual-cluster big.LITTLE system 32-bit):
217 #address-cells = <1>;
221 compatible = "arm,cortex-a15";
227 compatible = "arm,cortex-a15";
233 compatible = "arm,cortex-a7";
239 compatible = "arm,cortex-a7";
244 Example 2 (Cortex-A8 uniprocessor 32-bit system):
248 #address-cells = <1>;
252 compatible = "arm,cortex-a8";
257 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
261 #address-cells = <1>;
265 compatible = "arm,arm926ej-s";
270 Example 4 (ARM Cortex-A57 64-bit system):
274 #address-cells = <2>;
278 compatible = "arm,cortex-a57";
280 enable-method = "spin-table";
281 cpu-release-addr = <0 0x20000000>;
286 compatible = "arm,cortex-a57";
288 enable-method = "spin-table";
289 cpu-release-addr = <0 0x20000000>;
294 compatible = "arm,cortex-a57";
296 enable-method = "spin-table";
297 cpu-release-addr = <0 0x20000000>;
302 compatible = "arm,cortex-a57";
304 enable-method = "spin-table";
305 cpu-release-addr = <0 0x20000000>;
310 compatible = "arm,cortex-a57";
312 enable-method = "spin-table";
313 cpu-release-addr = <0 0x20000000>;
318 compatible = "arm,cortex-a57";
320 enable-method = "spin-table";
321 cpu-release-addr = <0 0x20000000>;
326 compatible = "arm,cortex-a57";
328 enable-method = "spin-table";
329 cpu-release-addr = <0 0x20000000>;
334 compatible = "arm,cortex-a57";
336 enable-method = "spin-table";
337 cpu-release-addr = <0 0x20000000>;
342 compatible = "arm,cortex-a57";
344 enable-method = "spin-table";
345 cpu-release-addr = <0 0x20000000>;
350 compatible = "arm,cortex-a57";
352 enable-method = "spin-table";
353 cpu-release-addr = <0 0x20000000>;
358 compatible = "arm,cortex-a57";
360 enable-method = "spin-table";
361 cpu-release-addr = <0 0x20000000>;
366 compatible = "arm,cortex-a57";
368 enable-method = "spin-table";
369 cpu-release-addr = <0 0x20000000>;
374 compatible = "arm,cortex-a57";
376 enable-method = "spin-table";
377 cpu-release-addr = <0 0x20000000>;
382 compatible = "arm,cortex-a57";
384 enable-method = "spin-table";
385 cpu-release-addr = <0 0x20000000>;
390 compatible = "arm,cortex-a57";
392 enable-method = "spin-table";
393 cpu-release-addr = <0 0x20000000>;
398 compatible = "arm,cortex-a57";
400 enable-method = "spin-table";
401 cpu-release-addr = <0 0x20000000>;
406 [1] arm/msm/qcom,saw2.txt
407 [2] arm/msm/qcom,kpss-acc.txt