5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
180 "nvidia,tegra132-denver"
181 "nvidia,tegra186-denver"
186 Value type: <stringlist>
187 Usage and definition depend on ARM architecture version.
188 # On ARM v8 64-bit this property is required and must
192 # On ARM 32-bit systems this property is optional and
194 "allwinner,sun6i-a31"
195 "allwinner,sun8i-a23"
197 "brcm,bcm11351-cpu-method"
201 "marvell,armada-375-smp"
202 "marvell,armada-380-smp"
203 "marvell,armada-390-smp"
204 "marvell,armada-xp-smp"
205 "mediatek,mt6589-smp"
206 "mediatek,mt81xx-tz-smp"
211 "rockchip,rk3036-smp"
212 "rockchip,rk3066-smp"
216 Usage: required for systems that have an "enable-method"
217 property value of "spin-table".
218 Value type: <prop-encoded-array>
220 # On ARM v8 64-bit systems must be a two cell
221 property identifying a 64-bit zero-initialised
225 Usage: required for systems that have an "enable-method"
226 property value of "qcom,kpss-acc-v1" or
228 Value type: <phandle>
229 Definition: Specifies the SAW[1] node associated with this CPU.
232 Usage: required for systems that have an "enable-method"
233 property value of "qcom,kpss-acc-v1" or
235 Value type: <phandle>
236 Definition: Specifies the ACC[2] node associated with this CPU.
240 Value type: <prop-encoded-array>
242 # List of phandles to idle state nodes supported
249 # u32 value representing CPU capacity [3] in
250 DMIPS/MHz, relative to highest capacity-dmips-mhz
254 Usage: optional for systems that have an "enable-method"
255 property value of "rockchip,rk3066-smp"
256 While optional, it is the preferred way to get access to
257 the cpu-core power-domains.
258 Value type: <phandle>
259 Definition: Specifies the syscon node controlling the cpu core
262 - dynamic-power-coefficient
264 Value type: <prop-encoded-array>
265 Definition: A u32 value that represents the running time dynamic
266 power coefficient in units of mW/MHz/uV^2. The
267 coefficient can either be calculated from power
268 measurements or derived by analysis.
270 The dynamic power consumption of the CPU is
271 proportional to the square of the Voltage (V) and
272 the clock frequency (f). The coefficient is used to
273 calculate the dynamic power as below -
275 Pdyn = dynamic-power-coefficient * V^2 * f
277 where voltage is in uV, frequency is in MHz.
279 Example 1 (dual-cluster big.LITTLE system 32-bit):
283 #address-cells = <1>;
287 compatible = "arm,cortex-a15";
293 compatible = "arm,cortex-a15";
299 compatible = "arm,cortex-a7";
305 compatible = "arm,cortex-a7";
310 Example 2 (Cortex-A8 uniprocessor 32-bit system):
314 #address-cells = <1>;
318 compatible = "arm,cortex-a8";
323 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
327 #address-cells = <1>;
331 compatible = "arm,arm926ej-s";
336 Example 4 (ARM Cortex-A57 64-bit system):
340 #address-cells = <2>;
344 compatible = "arm,cortex-a57";
346 enable-method = "spin-table";
347 cpu-release-addr = <0 0x20000000>;
352 compatible = "arm,cortex-a57";
354 enable-method = "spin-table";
355 cpu-release-addr = <0 0x20000000>;
360 compatible = "arm,cortex-a57";
362 enable-method = "spin-table";
363 cpu-release-addr = <0 0x20000000>;
368 compatible = "arm,cortex-a57";
370 enable-method = "spin-table";
371 cpu-release-addr = <0 0x20000000>;
376 compatible = "arm,cortex-a57";
378 enable-method = "spin-table";
379 cpu-release-addr = <0 0x20000000>;
384 compatible = "arm,cortex-a57";
386 enable-method = "spin-table";
387 cpu-release-addr = <0 0x20000000>;
392 compatible = "arm,cortex-a57";
394 enable-method = "spin-table";
395 cpu-release-addr = <0 0x20000000>;
400 compatible = "arm,cortex-a57";
402 enable-method = "spin-table";
403 cpu-release-addr = <0 0x20000000>;
408 compatible = "arm,cortex-a57";
410 enable-method = "spin-table";
411 cpu-release-addr = <0 0x20000000>;
416 compatible = "arm,cortex-a57";
418 enable-method = "spin-table";
419 cpu-release-addr = <0 0x20000000>;
424 compatible = "arm,cortex-a57";
426 enable-method = "spin-table";
427 cpu-release-addr = <0 0x20000000>;
432 compatible = "arm,cortex-a57";
434 enable-method = "spin-table";
435 cpu-release-addr = <0 0x20000000>;
440 compatible = "arm,cortex-a57";
442 enable-method = "spin-table";
443 cpu-release-addr = <0 0x20000000>;
448 compatible = "arm,cortex-a57";
450 enable-method = "spin-table";
451 cpu-release-addr = <0 0x20000000>;
456 compatible = "arm,cortex-a57";
458 enable-method = "spin-table";
459 cpu-release-addr = <0 0x20000000>;
464 compatible = "arm,cortex-a57";
466 enable-method = "spin-table";
467 cpu-release-addr = <0 0x20000000>;
472 [1] arm/msm/qcom,saw2.txt
473 [2] arm/msm/qcom,kpss-acc.txt
474 [3] ARM Linux kernel documentation - idle states bindings
475 Documentation/devicetree/bindings/arm/idle-states.txt
476 [3] ARM Linux kernel documentation - cpu capacity bindings
477 Documentation/devicetree/bindings/arm/cpu-capacity.txt