1 Device Tree Clock bindings for arch-at91
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "atmel,at91rm9200-pmc" or
10 "atmel,at91sam9g45-pmc" or
11 "atmel,at91sam9n12-pmc" or
12 "atmel,at91sam9x5-pmc" or
14 at91 PMC (Power Management Controller)
15 All at91 specific clocks (clocks defined below) must be child
18 "atmel,at91rm9200-clk-main-osc"
19 "atmel,at91sam9x5-clk-main-rc-osc"
22 "atmel,at91sam9x5-clk-main"
23 "atmel,at91rm9200-clk-main":
26 "atmel,at91rm9200-clk-master" or
27 "atmel,at91sam9x5-clk-master":
30 "atmel,at91sam9x5-clk-peripheral" or
31 "atmel,at91rm9200-clk-peripheral":
32 at91 peripheral clocks
34 "atmel,at91rm9200-clk-pll" or
35 "atmel,at91sam9g45-clk-pll" or
36 "atmel,at91sam9g20-clk-pllb" or
37 "atmel,sama5d3-clk-pll":
40 "atmel,at91sam9x5-clk-plldiv":
43 "atmel,at91rm9200-clk-programmable" or
44 "atmel,at91sam9g45-clk-programmable" or
45 "atmel,at91sam9x5-clk-programmable":
46 at91 programmable clocks
48 "atmel,at91sam9x5-clk-smd":
49 at91 SMD (Soft Modem) clock
51 "atmel,at91rm9200-clk-system":
54 "atmel,at91rm9200-clk-usb" or
55 "atmel,at91sam9x5-clk-usb" or
56 "atmel,at91sam9n12-clk-usb":
59 "atmel,at91sam9x5-clk-utmi":
62 Required properties for PMC node:
63 - reg : defines the IO memory reserved for the PMC.
64 - #size-cells : shall be 0 (reg is used to encode clk id).
65 - #address-cells : shall be 1 (reg is used to encode clk id).
66 - interrupts : shall be set to PMC interrupt line.
67 - interrupt-controller : tell that the PMC is an interrupt controller.
68 - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
69 and reflect the bit position in the PMC_ER/DR/SR registers.
70 You can use the dt macros defined in dt-bindings/clk/at91.h.
71 0 (AT91_PMC_MOSCS) -> main oscillator ready
72 1 (AT91_PMC_LOCKA) -> PLL A ready
73 2 (AT91_PMC_LOCKB) -> PLL B ready
74 3 (AT91_PMC_MCKRDY) -> master clock ready
75 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
76 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
77 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
78 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
79 18 (AT91_PMC_CFDEV) -> clock failure detected
83 compatible = "atmel,sama5d3-pmc";
86 #interrupt-cells = <2>;
90 /* put at91 clocks here */
93 Required properties for main clock internal RC oscillator:
94 - interrupt-parent : must reference the PMC node.
95 - interrupts : shall be set to "<0>".
96 - clock-frequency : define the internal RC oscillator frequency.
99 - clock-accuracy : define the internal RC oscillator accuracy.
102 main_rc_osc: main_rc_osc {
103 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
104 interrupt-parent = <&pmc>;
106 clock-frequency = <12000000>;
107 clock-accuracy = <50000000>;
110 Required properties for main clock oscillator:
111 - interrupt-parent : must reference the PMC node.
112 - interrupts : shall be set to "<0>".
113 - #clock-cells : from common clock binding; shall be set to 0.
114 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
117 - atmel,osc-bypass : boolean property. Specified if a clock signal is provided
120 clock signal is directly provided on XIN pin.
124 compatible = "atmel,at91rm9200-clk-main-osc";
125 interrupt-parent = <&pmc>;
128 clocks = <&main_xtal>;
131 Required properties for main clock:
132 - interrupt-parent : must reference the PMC node.
133 - interrupts : shall be set to "<0>".
134 - #clock-cells : from common clock binding; shall be set to 0.
135 - clocks : shall encode the main clk sources (see atmel datasheet).
139 compatible = "atmel,at91sam9x5-clk-main";
140 interrupt-parent = <&pmc>;
143 clocks = <&main_rc_osc &main_osc>;
146 Required properties for master clock:
147 - interrupt-parent : must reference the PMC node.
148 - interrupts : shall be set to "<3>".
149 - #clock-cells : from common clock binding; shall be set to 0.
150 - clocks : shall be the master clock sources (see atmel datasheet) phandles.
151 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
152 - atmel,clk-output-range : minimum and maximum clock frequency (two u32
154 e.g. output = <0 133000000>; <=> 0 to 133MHz.
155 - atmel,clk-divisors : master clock divisors table (four u32 fields).
156 0 <=> reserved value.
157 e.g. divisors = <1 2 4 6>;
158 - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
159 PRES field as CLOCK_DIV3 (e.g sam9x5).
163 compatible = "atmel,at91rm9200-clk-master";
164 interrupt-parent = <&pmc>;
167 atmel,clk-output-range = <0 133000000>;
168 atmel,clk-divisors = <1 2 4 0>;
171 Required properties for peripheral clocks:
172 - #size-cells : shall be 0 (reg is used to encode clk id).
173 - #address-cells : shall be 1 (reg is used to encode clk id).
174 - clocks : shall be the master clock phandle.
175 e.g. clocks = <&mck>;
176 - name: device tree node describing a specific system clock.
177 * #clock-cells : from common clock binding; shall be set to 0.
178 * reg: peripheral id. See Atmel's datasheets to get a full
179 list of peripheral ids.
180 * atmel,clk-output-range : minimum and maximum clock frequency
181 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
186 compatible = "atmel,at91sam9x5-clk-peripheral";
188 #address-cells = <1>;
194 atmel,clk-output-range = <0 133000000>;
200 atmel,clk-output-range = <0 66000000>;
205 Required properties for pll clocks:
206 - interrupt-parent : must reference the PMC node.
207 - interrupts : shall be set to "<1>".
208 - #clock-cells : from common clock binding; shall be set to 0.
209 - clocks : shall be the main clock phandle.
213 - atmel,clk-input-range : minimum and maximum source clock frequency (two u32
215 e.g. input = <1 32000000>; <=> 1 to 32MHz.
216 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
217 range description. Sould be set to 2, 3
219 * 1st and 2nd cells represent the frequency range (min-max).
220 * 3rd cell is optional and represents the OUT field value for the given
222 * 4th cell is optional and represents the ICPLL field (PLLICPR
224 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
225 depending on #atmel,pll-output-range-cells
230 compatible = "atmel,at91sam9g45-clk-pll";
231 interrupt-parent = <&pmc>;
236 atmel,clk-input-range = <2000000 32000000>;
237 #atmel,pll-clk-output-range-cells = <4>;
238 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
239 69500000 750000000 1 0
240 64500000 700000000 2 0
241 59500000 650000000 3 0
242 54500000 600000000 0 1
243 49500000 550000000 1 1
244 44500000 500000000 2 1
245 40000000 450000000 3 1>;
248 Required properties for plldiv clocks (plldiv = pll / 2):
249 - #clock-cells : from common clock binding; shall be set to 0.
250 - clocks : shall be the plla clock phandle.
252 The pll divisor is equal to 2 and cannot be changed.
256 compatible = "atmel,at91sam9x5-clk-plldiv";
261 Required properties for programmable clocks:
262 - interrupt-parent : must reference the PMC node.
263 - #size-cells : shall be 0 (reg is used to encode clk id).
264 - #address-cells : shall be 1 (reg is used to encode clk id).
265 - clocks : shall be the programmable clock source phandles.
266 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
267 - name: device tree node describing a specific prog clock.
268 * #clock-cells : from common clock binding; shall be set to 0.
269 * reg : programmable clock id (register offset from PCKx
271 * interrupts : shall be set to "<(8 + id)>".
275 compatible = "atmel,at91sam9g45-clk-programmable";
277 #address-cells = <1>;
278 interrupt-parent = <&pmc>;
279 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
295 Required properties for smd clock:
296 - #clock-cells : from common clock binding; shall be set to 0.
297 - clocks : shall be the smd clock source phandles.
298 e.g. clocks = <&plladiv>, <&utmi>;
302 compatible = "atmel,at91sam9x5-clk-smd";
304 clocks = <&plladiv>, <&utmi>;
307 Required properties for system clocks:
308 - #size-cells : shall be 0 (reg is used to encode clk id).
309 - #address-cells : shall be 1 (reg is used to encode clk id).
310 - name: device tree node describing a specific system clock.
311 * #clock-cells : from common clock binding; shall be set to 0.
312 * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
313 See Atmel's datasheet to get a full list of system clock ids.
317 compatible = "atmel,at91rm9200-clk-system";
318 #address-cells = <1>;
341 Required properties for usb clock:
342 - #clock-cells : from common clock binding; shall be set to 0.
343 - clocks : shall be the smd clock source phandles.
344 e.g. clocks = <&pllb>;
345 - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
346 usb clock divisor table.
347 e.g. divisors = <1 2 4 0>;
351 compatible = "atmel,at91sam9x5-clk-usb";
353 clocks = <&plladiv>, <&utmi>;
357 compatible = "atmel,at91rm9200-clk-usb";
360 atmel,clk-divisors = <1 2 4 0>;
364 Required properties for utmi clock:
365 - interrupt-parent : must reference the PMC node.
366 - interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
367 - #clock-cells : from common clock binding; shall be set to 0.
368 - clocks : shall be the main clock source phandle.
372 compatible = "atmel,at91sam9x5-clk-utmi";
373 interrupt-parent = <&pmc>;
374 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;