Documentation/devicetree/bindings/clock/sunxi.txt

   1 Device Tree Clock bindings for arch-sunxi
   2
   3 This binding uses the common clock binding[1].
   4
   5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
   6
   7 Required properties:
   8 - compatible : shall be one of the following:
   9         "allwinner,sun4i-osc-clk" - for a gatable oscillator
  10         "allwinner,sun4i-pll1-clk" - for the main PLL clock
  11         "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
  12         "allwinner,sun4i-axi-clk" - for the AXI clock
  13         "allwinner,sun4i-axi-gates-clk" - for the AXI gates
  14         "allwinner,sun4i-ahb-clk" - for the AHB clock
  15         "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
  16         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  17         "allwinner,sun4i-apb0-clk" - for the APB0 clock
  18         "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
  19         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
  20         "allwinner,sun4i-apb1-clk" - for the APB1 clock
  21         "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
  22         "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
  23         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
  24
  25 Required properties for all clocks:
  26 - reg : shall be the control register address for the clock.
  27 - clocks : shall be the input parent clock(s) phandle for the clock
  28 - #clock-cells : from common clock binding; shall be set to 0 except for
  29         "allwinner,*-gates-clk" where it shall be set to 1
  30
  31 Additionally, "allwinner,*-gates-clk" clocks require:
  32 - clock-output-names : the corresponding gate names that the clock controls
  33
  34 Clock consumers should specify the desired clocks they use with a
  35 "clocks" phandle cell. Consumers that are using a gated clock should
  36 provide an additional ID in their clock property. The values of this
  37 ID are documented in sunxi/<soc>-gates.txt.
  38
  39 For example:
  40
  41 osc24M: osc24M@01c20050 {
  42         #clock-cells = <0>;
  43         compatible = "allwinner,sun4i-osc-clk";
  44         reg = <0x01c20050 0x4>;
  45         clocks = <&osc24M_fixed>;
  46 };
  47
  48 pll1: pll1@01c20000 {
  49         #clock-cells = <0>;
  50         compatible = "allwinner,sun4i-pll1-clk";
  51         reg = <0x01c20000 0x4>;
  52         clocks = <&osc24M>;
  53 };
  54
  55 cpu: cpu@01c20054 {
  56         #clock-cells = <0>;
  57         compatible = "allwinner,sun4i-cpu-clk";
  58         reg = <0x01c20054 0x4>;
  59         clocks = <&osc32k>, <&osc24M>, <&pll1>;
  60 };