Documentation/devicetree/bindings/devfreq/exynos-bus.txt

   1 * Generic Exynos Bus frequency device
   2
   3 The Samsung Exynos SoC has many buses for data transfer between DRAM
   4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
   5 for buses. Generally, each bus of Exynos SoC includes a source clock
   6 and a power line, which are able to change the clock frequency
   7 of the bus in runtime. To monitor the usage of each bus in runtime,
   8 the driver uses the PPMU (Platform Performance Monitoring Unit), which
   9 is able to measure the current load of sub-blocks.
  10
  11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
  12 The each AXI bus has the owned source clock but, has not the only owned
  13 power line. The power line might be shared among one more sub-blocks.
  14 So, we can divide into two type of device as the role of each sub-block.
  15 There are two type of bus devices as following:
  16 - parent bus device
  17 - passive bus device
  18
  19 Basically, parent and passive bus device share the same power line.
  20 The parent bus device can only change the voltage of shared power line
  21 and the rest bus devices (passive bus device) depend on the decision of
  22 the parent bus device. If there are three blocks which share the VDD_xxx
  23 power line, Only one block should be parent device and then the rest blocks
  24 should depend on the parent device as passive device.
  25
  26         VDD_xxx |--- A block (parent)
  27                 |--- B block (passive)
  28                 |--- C block (passive)
  29
  30 There are a little different composition among Exynos SoC because each Exynos
  31 SoC has different sub-blocks. Therefore, such difference should be specified
  32 in devicetree file instead of each device driver. In result, this driver
  33 is able to support the bus frequency for all Exynos SoCs.
  34
  35 Required properties for all bus devices:
  36 - compatible: Should be "samsung,exynos-bus".
  37 - clock-names : the name of clock used by the bus, "bus".
  38 - clocks : phandles for clock specified in "clock-names" property.
  39 - operating-points-v2: the OPP table including frequency/voltage information
  40   to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
  41
  42 Required properties only for parent bus device:
  43 - vdd-supply: the regulator to provide the buses with the voltage.
  44 - devfreq-events: the devfreq-event device to monitor the current utilization
  45   of buses.
  46
  47 Required properties only for passive bus device:
  48 - devfreq: the parent bus device.
  49
  50 Optional properties only for parent bus device:
  51 - exynos,saturation-ratio: the percentage value which is used to calibrate
  52                         the performance count against total cycle count.
  53 - exynos,voltage-tolerance: the percentage value for bus voltage tolerance
  54                         which is used to calculate the max voltage.
  55
  56 Detailed correlation between sub-blocks and power line according to Exynos SoC:
  57 - In case of Exynos3250, there are two power line as following:
  58         VDD_MIF |--- DMC
  59
  60         VDD_INT |--- LEFTBUS (parent device)
  61                 |--- PERIL
  62                 |--- MFC
  63                 |--- G3D
  64                 |--- RIGHTBUS
  65                 |--- PERIR
  66                 |--- FSYS
  67                 |--- LCD0
  68                 |--- PERIR
  69                 |--- ISP
  70                 |--- CAM
  71
  72 - In case of Exynos4210, there is one power line as following:
  73         VDD_INT |--- DMC (parent device)
  74                 |--- LEFTBUS
  75                 |--- PERIL
  76                 |--- MFC(L)
  77                 |--- G3D
  78                 |--- TV
  79                 |--- LCD0
  80                 |--- RIGHTBUS
  81                 |--- PERIR
  82                 |--- MFC(R)
  83                 |--- CAM
  84                 |--- FSYS
  85                 |--- GPS
  86                 |--- LCD0
  87                 |--- LCD1
  88
  89 - In case of Exynos4x12, there are two power line as following:
  90         VDD_MIF |--- DMC
  91
  92         VDD_INT |--- LEFTBUS (parent device)
  93                 |--- PERIL
  94                 |--- MFC(L)
  95                 |--- G3D
  96                 |--- TV
  97                 |--- IMAGE
  98                 |--- RIGHTBUS
  99                 |--- PERIR
 100                 |--- MFC(R)
 101                 |--- CAM
 102                 |--- FSYS
 103                 |--- GPS
 104                 |--- LCD0
 105                 |--- ISP
 106
 107 Example1:
 108         Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 109         power line (regulator). The MIF (Memory Interface) AXI bus is used to
 110         transfer data between DRAM and CPU and uses the VDD_MIF regulator.
 111
 112         - MIF (Memory Interface) block
 113         : VDD_MIF |--- DMC (Dynamic Memory Controller)
 114
 115         - INT (Internal) block
 116         : VDD_INT |--- LEFTBUS (parent device)
 117                   |--- PERIL
 118                   |--- MFC
 119                   |--- G3D
 120                   |--- RIGHTBUS
 121                   |--- FSYS
 122                   |--- LCD0
 123                   |--- PERIR
 124                   |--- ISP
 125                   |--- CAM
 126
 127         - MIF bus's frequency/voltage table
 128         -----------------------
 129         |Lv| Freq   | Voltage |
 130         -----------------------
 131         |L1| 50000  |800000   |
 132         |L2| 100000 |800000   |
 133         |L3| 134000 |800000   |
 134         |L4| 200000 |825000   |
 135         |L5| 400000 |875000   |
 136         -----------------------
 137
 138         - INT bus's frequency/voltage table
 139         ----------------------------------------------------------
 140         |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
 141         | name|       |LCD0    |       |       |       ||        |
 142         |     |       |FSYS    |       |       |       ||        |
 143         |     |       |MFC     |       |       |       ||        |
 144         ----------------------------------------------------------
 145         |Mode |*parent|passive |passive|passive|passive||        |
 146         ----------------------------------------------------------
 147         |Lv   |Frequency                               ||Voltage |
 148         ----------------------------------------------------------
 149         |L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
 150         |L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
 151         |L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
 152         |L4   |134000 |134000  |200000 |200000 |       ||1000000 |
 153         |L5   |200000 |200000  |400000 |300000 |       ||1000000 |
 154         ----------------------------------------------------------
 155
 156 Example2 :
 157         The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
 158         is listed below:
 159
 160         bus_dmc: bus_dmc {
 161                 compatible = "samsung,exynos-bus";
 162                 clocks = <&cmu_dmc CLK_DIV_DMC>;
 163                 clock-names = "bus";
 164                 operating-points-v2 = <&bus_dmc_opp_table>;
 165                 status = "disabled";
 166         };
 167
 168         bus_dmc_opp_table: opp_table1 {
 169                 compatible = "operating-points-v2";
 170                 opp-shared;
 171
 172                 opp@50000000 {
 173                         opp-hz = /bits/ 64 <50000000>;
 174                         opp-microvolt = <800000>;
 175                 };
 176                 opp@100000000 {
 177                         opp-hz = /bits/ 64 <100000000>;
 178                         opp-microvolt = <800000>;
 179                 };
 180                 opp@134000000 {
 181                         opp-hz = /bits/ 64 <134000000>;
 182                         opp-microvolt = <800000>;
 183                 };
 184                 opp@200000000 {
 185                         opp-hz = /bits/ 64 <200000000>;
 186                         opp-microvolt = <825000>;
 187                 };
 188                 opp@400000000 {
 189                         opp-hz = /bits/ 64 <400000000>;
 190                         opp-microvolt = <875000>;
 191                 };
 192         };
 193
 194         bus_leftbus: bus_leftbus {
 195                 compatible = "samsung,exynos-bus";
 196                 clocks = <&cmu CLK_DIV_GDL>;
 197                 clock-names = "bus";
 198                 operating-points-v2 = <&bus_leftbus_opp_table>;
 199                 status = "disabled";
 200         };
 201
 202         bus_rightbus: bus_rightbus {
 203                 compatible = "samsung,exynos-bus";
 204                 clocks = <&cmu CLK_DIV_GDR>;
 205                 clock-names = "bus";
 206                 operating-points-v2 = <&bus_leftbus_opp_table>;
 207                 status = "disabled";
 208         };
 209
 210         bus_lcd0: bus_lcd0 {
 211                 compatible = "samsung,exynos-bus";
 212                 clocks = <&cmu CLK_DIV_ACLK_160>;
 213                 clock-names = "bus";
 214                 operating-points-v2 = <&bus_leftbus_opp_table>;
 215                 status = "disabled";
 216         };
 217
 218         bus_fsys: bus_fsys {
 219                 compatible = "samsung,exynos-bus";
 220                 clocks = <&cmu CLK_DIV_ACLK_200>;
 221                 clock-names = "bus";
 222                 operating-points-v2 = <&bus_leftbus_opp_table>;
 223                 status = "disabled";
 224         };
 225
 226         bus_mcuisp: bus_mcuisp {
 227                 compatible = "samsung,exynos-bus";
 228                 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 229                 clock-names = "bus";
 230                 operating-points-v2 = <&bus_mcuisp_opp_table>;
 231                 status = "disabled";
 232         };
 233
 234         bus_isp: bus_isp {
 235                 compatible = "samsung,exynos-bus";
 236                 clocks = <&cmu CLK_DIV_ACLK_266>;
 237                 clock-names = "bus";
 238                 operating-points-v2 = <&bus_isp_opp_table>;
 239                 status = "disabled";
 240         };
 241
 242         bus_peril: bus_peril {
 243                 compatible = "samsung,exynos-bus";
 244                 clocks = <&cmu CLK_DIV_ACLK_100>;
 245                 clock-names = "bus";
 246                 operating-points-v2 = <&bus_peril_opp_table>;
 247                 status = "disabled";
 248         };
 249
 250         bus_mfc: bus_mfc {
 251                 compatible = "samsung,exynos-bus";
 252                 clocks = <&cmu CLK_SCLK_MFC>;
 253                 clock-names = "bus";
 254                 operating-points-v2 = <&bus_leftbus_opp_table>;
 255                 status = "disabled";
 256         };
 257
 258         bus_leftbus_opp_table: opp_table1 {
 259                 compatible = "operating-points-v2";
 260                 opp-shared;
 261
 262                 opp@50000000 {
 263                         opp-hz = /bits/ 64 <50000000>;
 264                         opp-microvolt = <900000>;
 265                 };
 266                 opp@80000000 {
 267                         opp-hz = /bits/ 64 <80000000>;
 268                         opp-microvolt = <900000>;
 269                 };
 270                 opp@100000000 {
 271                         opp-hz = /bits/ 64 <100000000>;
 272                         opp-microvolt = <1000000>;
 273                 };
 274                 opp@134000000 {
 275                         opp-hz = /bits/ 64 <134000000>;
 276                         opp-microvolt = <1000000>;
 277                 };
 278                 opp@200000000 {
 279                         opp-hz = /bits/ 64 <200000000>;
 280                         opp-microvolt = <1000000>;
 281                 };
 282         };
 283
 284         bus_mcuisp_opp_table: opp_table2 {
 285                 compatible = "operating-points-v2";
 286                 opp-shared;
 287
 288                 opp@50000000 {
 289                         opp-hz = /bits/ 64 <50000000>;
 290                 };
 291                 opp@80000000 {
 292                         opp-hz = /bits/ 64 <80000000>;
 293                 };
 294                 opp@100000000 {
 295                         opp-hz = /bits/ 64 <100000000>;
 296                 };
 297                 opp@200000000 {
 298                         opp-hz = /bits/ 64 <200000000>;
 299                 };
 300                 opp@400000000 {
 301                         opp-hz = /bits/ 64 <400000000>;
 302                 };
 303         };
 304
 305         bus_isp_opp_table: opp_table3 {
 306                 compatible = "operating-points-v2";
 307                 opp-shared;
 308
 309                 opp@50000000 {
 310                         opp-hz = /bits/ 64 <50000000>;
 311                 };
 312                 opp@80000000 {
 313                         opp-hz = /bits/ 64 <80000000>;
 314                 };
 315                 opp@100000000 {
 316                         opp-hz = /bits/ 64 <100000000>;
 317                 };
 318                 opp@200000000 {
 319                         opp-hz = /bits/ 64 <200000000>;
 320                 };
 321                 opp@300000000 {
 322                         opp-hz = /bits/ 64 <300000000>;
 323                 };
 324         };
 325
 326         bus_peril_opp_table: opp_table4 {
 327                 compatible = "operating-points-v2";
 328                 opp-shared;
 329
 330                 opp@50000000 {
 331                         opp-hz = /bits/ 64 <50000000>;
 332                 };
 333                 opp@80000000 {
 334                         opp-hz = /bits/ 64 <80000000>;
 335                 };
 336                 opp@100000000 {
 337                         opp-hz = /bits/ 64 <100000000>;
 338                 };
 339         };
 340
 341
 342         Usage case to handle the frequency and voltage of bus on runtime
 343         in exynos3250-rinato.dts is listed below:
 344
 345         &bus_dmc {
 346                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
 347                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
 348                 status = "okay";
 349         };
 350
 351         &bus_leftbus {
 352                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
 353                 vdd-supply = <&buck3_reg>;
 354                 status = "okay";
 355         };
 356
 357         &bus_rightbus {
 358                 devfreq = <&bus_leftbus>;
 359                 status = "okay";
 360         };
 361
 362         &bus_lcd0 {
 363                 devfreq = <&bus_leftbus>;
 364                 status = "okay";
 365         };
 366
 367         &bus_fsys {
 368                 devfreq = <&bus_leftbus>;
 369                 status = "okay";
 370         };
 371
 372         &bus_mcuisp {
 373                 devfreq = <&bus_leftbus>;
 374                 status = "okay";
 375         };
 376
 377         &bus_isp {
 378                 devfreq = <&bus_leftbus>;
 379                 status = "okay";
 380         };
 381
 382         &bus_peril {
 383                 devfreq = <&bus_leftbus>;
 384                 status = "okay";
 385         };
 386
 387         &bus_mfc {
 388                 devfreq = <&bus_leftbus>;
 389                 status = "okay";
 390         };