1 * Synopsys Designware DMA Controller
4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt-parent: Should be the phandle for the interrupt controller
7 that services interrupts for this device
8 - interrupt: Should contain the DMAC interrupt number
9 - nr_channels: Number of channels supported by hardware
10 - is_private: The device channels should be marked as private and not for by the
11 general purpose DMA channel allocator. False if not passed.
12 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
14 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
15 increase from chan n->0
16 - block_size: Maximum block size supported by the controller
17 - nr_masters: Number of AHB masters supported by the controller
18 - data_width: Maximum data width supported by hardware per AHB master
19 (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
21 - bus_id: name of this device channel, not just a device name since
22 devices may have more than one channel e.g. "foo_tx". For using the
23 dw_generic_filter(), slave drivers must pass exactly this string as
24 param to filter function.
25 - cfg_hi: Platform-specific initializer for the CFG_HI register
26 - cfg_lo: Platform-specific initializer for the CFG_LO register
27 - src_master: src master for transfers on allocated channel.
28 - dst_master: dest master for transfers on allocated channel.
33 compatible = "snps,dma-spear1340";
34 reg = <0xfc000000 0x1000>;
35 interrupt-parent = <&vic1>;
39 chan_allocation_order = <1>;
43 data_width = <3 3 0 0>;
48 cfg_hi = <0x4000>; /* 0x8 << 11 */
55 cfg_hi = <0x2000>; /* 0x4 << 11 */