1 Qualcomm adreno/snapdragon display controller
6 - reg: Physical base address and length of the controller's registers.
7 - interrupts: The interrupt signal from the display controller.
8 - connectors: array of phandles for output device(s)
9 - clocks: device clocks
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: the following clocks are required:
20 - gpus: phandle for gpu device
27 mdp: qcom,mdp@5100000 {
28 compatible = "qcom,mdp";
29 reg = <0x05100000 0xf0000>;
30 interrupts = <GIC_SPI 75 0>;