4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
8 in the host1x address space. Should be 1.
9 - #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1.
11 - ranges: The mapping of the host1x address space to the CPU address space.
13 The host1x top-level node defines a number of children, each representing one
14 of the following host1x client modules:
19 - compatible: "nvidia,tegra<chip>-mpe"
20 - reg: Physical base address and length of the controller's registers.
21 - interrupts: The interrupt outputs from the controller.
26 - compatible: "nvidia,tegra<chip>-vi"
27 - reg: Physical base address and length of the controller's registers.
28 - interrupts: The interrupt outputs from the controller.
30 - epp: encoder pre-processor
33 - compatible: "nvidia,tegra<chip>-epp"
34 - reg: Physical base address and length of the controller's registers.
35 - interrupts: The interrupt outputs from the controller.
37 - isp: image signal processor
40 - compatible: "nvidia,tegra<chip>-isp"
41 - reg: Physical base address and length of the controller's registers.
42 - interrupts: The interrupt outputs from the controller.
44 - gr2d: 2D graphics engine
47 - compatible: "nvidia,tegra<chip>-gr2d"
48 - reg: Physical base address and length of the controller's registers.
49 - interrupts: The interrupt outputs from the controller.
51 - gr3d: 3D graphics engine
54 - compatible: "nvidia,tegra<chip>-gr3d"
55 - reg: Physical base address and length of the controller's registers.
57 - dc: display controller
60 - compatible: "nvidia,tegra<chip>-dc"
61 - reg: Physical base address and length of the controller's registers.
62 - interrupts: The interrupt outputs from the controller.
64 Each display controller node has a child node, named "rgb", that represents
65 the RGB output associated with the controller. It can take the following
67 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
68 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
69 - nvidia,edid: supplies a binary EDID blob
70 - nvidia,panel: phandle of a display panel
72 - hdmi: High Definition Multimedia Interface
75 - compatible: "nvidia,tegra<chip>-hdmi"
76 - reg: Physical base address and length of the controller's registers.
77 - interrupts: The interrupt outputs from the controller.
78 - vdd-supply: regulator for supply voltage
79 - pll-supply: regulator for PLL
82 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
83 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
84 - nvidia,edid: supplies a binary EDID blob
85 - nvidia,panel: phandle of a display panel
87 - tvo: TV encoder output
90 - compatible: "nvidia,tegra<chip>-tvo"
91 - reg: Physical base address and length of the controller's registers.
92 - interrupts: The interrupt outputs from the controller.
94 - dsi: display serial interface
97 - compatible: "nvidia,tegra<chip>-dsi"
98 - reg: Physical base address and length of the controller's registers.
106 compatible = "nvidia,tegra20-host1x", "simple-bus";
107 reg = <0x50000000 0x00024000>;
108 interrupts = <0 65 0x04 /* mpcore syncpt */
109 0 67 0x04>; /* mpcore general */
111 #address-cells = <1>;
114 ranges = <0x54000000 0x54000000 0x04000000>;
117 compatible = "nvidia,tegra20-mpe";
118 reg = <0x54040000 0x00040000>;
119 interrupts = <0 68 0x04>;
123 compatible = "nvidia,tegra20-vi";
124 reg = <0x54080000 0x00040000>;
125 interrupts = <0 69 0x04>;
129 compatible = "nvidia,tegra20-epp";
130 reg = <0x540c0000 0x00040000>;
131 interrupts = <0 70 0x04>;
135 compatible = "nvidia,tegra20-isp";
136 reg = <0x54100000 0x00040000>;
137 interrupts = <0 71 0x04>;
141 compatible = "nvidia,tegra20-gr2d";
142 reg = <0x54140000 0x00040000>;
143 interrupts = <0 72 0x04>;
147 compatible = "nvidia,tegra20-gr3d";
148 reg = <0x54180000 0x00040000>;
152 compatible = "nvidia,tegra20-dc";
153 reg = <0x54200000 0x00040000>;
154 interrupts = <0 73 0x04>;
162 compatible = "nvidia,tegra20-dc";
163 reg = <0x54240000 0x00040000>;
164 interrupts = <0 74 0x04>;
172 compatible = "nvidia,tegra20-hdmi";
173 reg = <0x54280000 0x00040000>;
174 interrupts = <0 75 0x04>;
179 compatible = "nvidia,tegra20-tvo";
180 reg = <0x542c0000 0x00040000>;
181 interrupts = <0 76 0x04>;
186 compatible = "nvidia,tegra20-dsi";
187 reg = <0x54300000 0x00040000>;