1 * Device tree bindings for ARM PL172 MultiPort Memory Controller
5 - compatible: "arm,pl172", "arm,primecell"
7 - reg: Must contains offset/length value for controller.
9 - #address-cells: Must be 2. The partition number has to be encoded in the
10 first address cell and it may accept values 0..N-1
11 (N - total number of partitions). The second cell is the
12 offset into the partition.
14 - #size-cells: Must be set to 1.
16 - ranges: Must contain one or more chip select memory regions.
18 - clocks: Must contain references to controller clocks.
20 - clock-names: Must contain "mpmcclk" and "apb_pclk".
22 - clock-ranges: Empty property indicating that child nodes can inherit
23 named clocks. Required only if clock tree data present
25 See clock-bindings.txt
27 Child chip-select (cs) nodes contain the memory devices nodes connected to
28 such as NOR (e.g. cfi-flash) and NAND.
30 Required child cs node properties:
32 - #address-cells: Must be 2.
34 - #size-cells: Must be 1.
36 - ranges: Empty property indicating that child nodes can inherit
39 - clock-ranges: Empty property indicating that child nodes can inherit
40 named clocks. Required only if clock tree data present
43 - mpmc,cs: Chip select number. Indicates to the pl0172 driver
44 which chipselect is used for accessing the memory.
46 - mpmc,memory-width: Width of the chip select memory. Must be equal to
49 Optional child cs node config properties:
51 - mpmc,async-page-mode: Enable asynchronous page mode.
53 - mpmc,cs-active-high: Set chip select polarity to active high.
55 - mpmc,byte-lane-low: Set byte lane state to low.
57 - mpmc,extended-wait: Enable extended wait.
59 - mpmc,buffer-enable: Enable write buffer.
61 - mpmc,write-protect: Enable write protect.
63 Optional child cs node timing properties:
65 - mpmc,write-enable-delay: Delay from chip select assertion to write
66 enable (WE signal) in nano seconds.
68 - mpmc,output-enable-delay: Delay from chip select assertion to output
69 enable (OE signal) in nano seconds.
71 - mpmc,write-access-delay: Delay from chip select assertion to write
72 access in nano seconds.
74 - mpmc,read-access-delay: Delay from chip select assertion to read
75 access in nano seconds.
77 - mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
78 accesses in nano seconds.
80 - mpmc,turn-round-delay: Delay between access to memory banks in nano
83 If any of the above timing parameters are absent, current parameter value will
84 be taken from the corresponding HW reg.
86 Example for pl172 with nor flash on chip select 0 shown below.
88 emc: memory-controller@40005000 {
89 compatible = "arm,pl172", "arm,primecell";
90 reg = <0x40005000 0x1000>;
91 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
92 clock-names = "mpmcclk", "apb_pclk";
95 ranges = <0 0 0x1c000000 0x1000000
96 1 0 0x1d000000 0x1000000
97 2 0 0x1e000000 0x1000000
98 3 0 0x1f000000 0x1000000>;
101 #address-cells = <2>;
106 mpmc,memory-width = <16>;
108 mpmc,write-enable-delay = <0>;
109 mpmc,output-enable-delay = <0>;
110 mpmc,read-enable-delay = <70>;
111 mpmc,page-mode-read-delay = <70>;
114 compatible = "sst,sst39vf320", "cfi-flash";
115 reg = <0 0 0x400000>;
117 #address-cells = <1>;