1 Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be "samsung,s5pv210-mipi-video-phy";
6 - reg : offset and length of the MIPI DPHY register set;
7 - #phy-cells : from the generic phy bindings, must be 1;
9 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
10 the PHY specifier identifies the PHY and its meaning is as follows:
16 Samsung EXYNOS SoC series Display Port PHY
17 -------------------------------------------------
20 - compatible : should be "samsung,exynos5250-dp-video-phy";
21 - reg : offset and length of the Display Port PHY register set;
22 - #phy-cells : from the generic PHY bindings, must be 0;
24 Samsung S5P/EXYNOS SoC series USB PHY
25 -------------------------------------------------
28 - compatible : should be one of the listed compatibles:
29 - "samsung,exynos3250-usb2-phy"
30 - "samsung,exynos4210-usb2-phy"
31 - "samsung,exynos4x12-usb2-phy"
32 - "samsung,exynos5250-usb2-phy"
33 - "samsung,s5pv210-usb2-phy"
34 - reg : a list of registers used by phy driver
35 - first and obligatory is the location of phy modules registers
36 - samsung,sysreg-phandle - handle to syscon used to control the system registers
37 - samsung,pmureg-phandle - handle to syscon used to control PMU registers
38 - #phy-cells : from the generic phy bindings, must be 1;
39 - clocks and clock-names:
40 - the "phy" clock is required by the phy module, used as a gate
41 - the "ref" clock is used to get the rate of the clock provided to the
44 The first phandle argument in the PHY specifier identifies the PHY, its
45 meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
46 and Exynos 4212) it is as follows:
47 0 - USB device ("device"),
48 1 - USB host ("host"),
51 Exynos3250 has only USB device phy available as phy 0.
53 Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
58 For Exynos 4412 (compatible with Exynos 4212):
60 usbphy: phy@125b0000 {
61 compatible = "samsung,exynos4x12-usb2-phy";
62 reg = <0x125b0000 0x100>;
63 clocks = <&clock 305>, <&clock 2>;
64 clock-names = "phy", "ref";
67 samsung,sysreg-phandle = <&sys_reg>;
68 samsung,pmureg-phandle = <&pmu_reg>;
71 Then the PHY can be used in other nodes such as:
73 phy-consumer@12340000 {
78 Refer to DT bindings documentation of particular PHY consumer devices for more
79 information about required PHYs and the way of specification.
81 Samsung SATA PHY Controller
82 ---------------------------
84 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
85 Each SATA PHY controller should have its own node.
88 - compatible : compatible list, contains "samsung,exynos5250-sata-phy"
89 - reg : offset and length of the SATA PHY register set;
90 - #phy-cells : must be zero
91 - clocks : must be exactly one entry
92 - clock-names : must be "sata_phyctrl"
93 - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
94 - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
97 sata_phy: sata-phy@12170000 {
98 compatible = "samsung,exynos5250-sata-phy";
99 reg = <0x12170000 0x1ff>;
100 clocks = <&clock 287>;
101 clock-names = "sata_phyctrl";
103 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
104 samsung,syscon-phandle = <&pmu_syscon>;
107 Device-Tree bindings for sataphy i2c client driver
108 --------------------------------------------------
111 compatible: Should be "samsung,exynos-sataphy-i2c"
112 - reg: I2C address of the sataphy i2c device.
116 sata_phy_i2c:sata-phy@38 {
117 compatible = "samsung,exynos-sataphy-i2c";
121 Samsung Exynos5 SoC series USB DRD PHY controller
122 --------------------------------------------------
125 - compatible : Should be set to one of the following supported values:
126 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
127 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
128 - reg : Register offset and length of USB DRD PHY register set;
129 - clocks: Clock IDs array as required by the controller
130 - clock-names: names of clocks correseponding to IDs in the clock property;
132 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
133 used for register access.
134 - ref: PHY's reference clock (usually crystal clock), used for
135 PHY operations, associated by phy name. It is used to
136 determine bit values for clock settings register.
137 For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
138 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
139 control pmu registers for power isolation.
140 - #phy-cells : from the generic PHY bindings, must be 1;
142 For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
143 compatible PHYs, the second cell in the PHY specifier identifies the
144 PHY id, which is interpreted as follows:
149 usbdrd_phy: usbphy@12100000 {
150 compatible = "samsung,exynos5250-usbdrd-phy";
151 reg = <0x12100000 0x100>;
152 clocks = <&clock 286>, <&clock 1>;
153 clock-names = "phy", "ref";
154 samsung,pmu-syscon = <&pmu_system_controller>;
158 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
159 'usbdrd_phy' nodes should have numbered alias in the aliases node,
160 in the form of usbdrdphyN, N = 0, 1... (depending on number of
164 usbdrdphy0 = &usb3_phy0;
165 usbdrdphy1 = &usb3_phy1;