1 Binding for MTK SPI controller
4 - compatible: should be one of the following.
5 - mediatek,mt8173-spi: for mt8173 platforms
6 - mediatek,mt8135-spi: for mt8135 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
9 - #address-cells: should be 1.
11 - #size-cells: should be 0.
13 - reg: Address and length of the register set for the device
15 - interrupts: Should contain spi interrupt
17 - clocks: phandles to input clocks.
18 The first should be one of the following. It's PLL.
19 - <&clk26m>: specify parent clock 26MHZ.
20 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
22 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
23 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
24 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
25 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
26 The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
28 - clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
29 muxes clock, and "spi-clk" for the clock gate.
32 - mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
33 controller used, this value should be 0~3, only required for MT8173.
34 0: specify GPIO69,70,71,72 for spi pins.
35 1: specify GPIO102,103,104,105 for spi pins.
36 2: specify GPIO128,129,130,131 for spi pins.
37 3: specify GPIO5,6,7,8 for spi pins.
41 - SoC Specific Portion:
43 compatible = "mediatek,mt8173-spi";
46 reg = <0 0x1100a000 0 0x1000>;
47 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
48 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
49 <&topckgen CLK_TOP_SPI_SEL>,
50 <&pericfg CLK_PERI_SPI0>;
51 clock-names = "parent-clk", "sel-clk", "spi-clk";
53 mediatek,pad-select = <0>;