1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
7 nodes describing each of the two LVDS encoder channels of the bridge.
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
13 Both LDB versions are similar, but i.MX6 has an additional
14 multiplexer in the front to select any of the four IPU display
15 interfaces as input for each LVDS channel.
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
20 the display interface selector clocks, as described in
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 The following clocks are expected on i.MX53:
23 "di0_pll" - LDB LVDS channel 0 mux
24 "di1_pll" - LDB LVDS channel 1 mux
25 "di0" - LDB LVDS channel 0 gate
26 "di1" - LDB LVDS channel 1 gate
27 "di0_sel" - IPU1 DI0 mux
28 "di1_sel" - IPU1 DI1 mux
29 On i.MX6q the following additional clocks are needed:
30 "di2_sel" - IPU2 DI0 mux
31 "di3_sel" - IPU2 DI1 mux
32 The needed clock numbers for each are documented in
33 Documentation/devicetree/bindings/clock/imx5-clock.txt, and in
34 Documentation/devicetree/bindings/clock/imx6q-clock.txt.
37 - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
38 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
40 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
41 be configured - one input will be distributed on both outputs in dual
47 Each LVDS Channel has to contain a display-timings node that describes the
48 video timings for the connected LVDS display. For detailed information, also
49 have a look at Documentation/devicetree/bindings/video/display-timing.txt.
52 - reg : should be <0> or <1>
53 - crtcs : a list of phandles with index pointing to the IPU display interfaces
54 that can be used as video source for this channel.
55 - fsl,data-mapping : should be "spwg" or "jeida"
56 This describes how the color bits are laid out in the
57 serialized LVDS signal.
58 - fsl,data-width : should be <18> or <24>
62 gpr: iomuxc-gpr@53fa8000 {
69 compatible = "fsl,imx53-ldb";
71 clocks = <&clks 122>, <&clks 120>,
72 <&clks 115>, <&clks 116>,
73 <&clks 123>, <&clks 85>;
74 clock-names = "di0_pll", "di1_pll",
81 fsl,data-mapping = "spwg";
82 fsl,data-width = <24>;
92 fsl,data-mapping = "spwg";
93 fsl,data-width = <24>;