1 Booting the Linux/ppc kernel without Open Firmware
2 --------------------------------------------------
4 (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
6 (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
7 Freescale Semiconductor, FSL SOC and 32-bit additions
8 (c) 2006 MontaVista Software, Inc.
9 Flash chip node definition
15 1) Entry point for arch/powerpc
18 II - The DT block format
20 2) Device tree generalities
21 3) Device tree "structure" block
22 4) Device tree "strings" block
24 III - Required content of the device tree
25 1) Note about cells and address representation
26 2) Note about "compatible" properties
27 3) Note about "name" properties
28 4) Note about node and property names and character set
29 5) Required nodes and properties
33 d) the /memory node(s)
35 f) the /soc<SOCname> node
37 IV - "dtc", the device tree compiler
39 V - Recommendations for a bootloader
41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification
45 b) Gianfar-compatible ethernet nodes
47 d) Interrupt controllers
49 f) Freescale SOC USB controllers
50 g) Freescale SOC SEC Security Engines
51 h) Board Control and Status (BCSR)
52 i) Freescale QUICC Engine module (QE)
53 j) CFI or JEDEC memory-mapped NOR flash
54 k) Global Utilities Block
55 l) Freescale Communications Processor Module
56 m) Chipselect/Local Bus
57 n) 4xx/Axon EMAC ethernet nodes
59 p) Freescale Synchronous Serial Interface
60 q) USB EHCI controllers
63 VII - Marvell Discovery mv64[345]6x System Controller chips
64 1) The /system-controller node
65 2) Child nodes of /system-controller
66 a) Marvell Discovery MDIO bus
67 b) Marvell Discovery ethernet controller
68 c) Marvell Discovery PHY nodes
69 d) Marvell Discovery SDMA nodes
70 e) Marvell Discovery BRG nodes
71 f) Marvell Discovery CUNIT nodes
72 g) Marvell Discovery MPSCROUTING nodes
73 h) Marvell Discovery MPSCINTR nodes
74 i) Marvell Discovery MPSC nodes
75 j) Marvell Discovery Watch Dog Timer nodes
76 k) Marvell Discovery I2C nodes
77 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
78 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
79 n) Marvell Discovery GPP (General Purpose Pins) nodes
80 o) Marvell Discovery PCI host bridge node
81 p) Marvell Discovery CPU Error nodes
82 q) Marvell Discovery SRAM Controller nodes
83 r) Marvell Discovery PCI Error Handler nodes
84 s) Marvell Discovery Memory Controller nodes
86 VIII - Specifying interrupt information for devices
87 1) interrupts property
88 2) interrupt-parent property
89 3) OpenPIC Interrupt Controllers
90 4) ISA Interrupt Controllers
92 IX - Specifying GPIO information for devices
94 2) gpio-controller nodes
96 X - Specifying device power management information (sleep property)
98 Appendix A - Sample SOC node for MPC8540
104 May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
106 May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
107 clarifies the fact that a lot of things are
108 optional, the kernel only requires a very
109 small device tree, though it is encouraged
110 to provide an as complete one as possible.
112 May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
114 - Define version 3 and new format version 16
115 for the DT block (version 16 needs kernel
116 patches, will be fwd separately).
117 String block now has a size, and full path
118 is replaced by unit name for more
120 linux,phandle is made optional, only nodes
121 that are referenced by other nodes need it.
122 "name" property is now automatically
123 deduced from the unit name
125 June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
126 OF_DT_END_NODE in structure definition.
127 - Change version 16 format to always align
128 property data to 4 bytes. Since tokens are
129 already aligned, that means no specific
130 required alignment between property size
131 and property data. The old style variable
132 alignment would make it impossible to do
133 "simple" insertion of properties using
134 memmove (thanks Milton for
135 noticing). Updated kernel patch as well
136 - Correct a few more alignment constraints
137 - Add a chapter about the device-tree
138 compiler and the textural representation of
139 the tree that can be "compiled" by dtc.
141 November 21, 2005: Rev 0.5
142 - Additions/generalizations for 32-bit
143 - Changed to reflect the new arch/powerpc
149 - Add some definitions of interrupt tree (simple/complex)
150 - Add some definitions for PCI host bridges
151 - Add some common address format examples
152 - Add definitions for standard properties and "compatible"
153 names for cells that are not already defined by the existing
155 - Compare FSL SOC use of PCI to standard and make sure no new
156 node definition required.
157 - Add more information about node definitions for SOC devices
158 that currently have no standard, like the FSL CPM.
164 During the recent development of the Linux/ppc64 kernel, and more
165 specifically, the addition of new platform types outside of the old
166 IBM pSeries/iSeries pair, it was decided to enforce some strict rules
167 regarding the kernel entry and bootloader <-> kernel interfaces, in
168 order to avoid the degeneration that had become the ppc32 kernel entry
169 point and the way a new platform should be added to the kernel. The
170 legacy iSeries platform breaks those rules as it predates this scheme,
171 but no new board support will be accepted in the main tree that
172 doesn't follows them properly. In addition, since the advent of the
173 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
174 platforms and 32-bit platforms which move into arch/powerpc will be
175 required to use these rules as well.
177 The main requirement that will be defined in more detail below is
178 the presence of a device-tree whose format is defined after Open
179 Firmware specification. However, in order to make life easier
180 to embedded board vendors, the kernel doesn't require the device-tree
181 to represent every device in the system and only requires some nodes
182 and properties to be present. This will be described in detail in
183 section III, but, for example, the kernel does not require you to
184 create a node for every PCI device in the system. It is a requirement
185 to have a node for PCI host bridges in order to provide interrupt
186 routing informations and memory/IO ranges, among others. It is also
187 recommended to define nodes for on chip devices and other busses that
188 don't specifically fit in an existing OF specification. This creates a
189 great flexibility in the way the kernel can then probe those and match
190 drivers to device, without having to hard code all sorts of tables. It
191 also makes it more flexible for board vendors to do minor hardware
192 upgrades without significantly impacting the kernel code or cluttering
193 it with special cases.
196 1) Entry point for arch/powerpc
197 -------------------------------
199 There is one and one single entry point to the kernel, at the start
200 of the kernel image. That entry point supports two calling
203 a) Boot from Open Firmware. If your firmware is compatible
204 with Open Firmware (IEEE 1275) or provides an OF compatible
205 client interface API (support for "interpret" callback of
206 forth words isn't required), you can enter the kernel with:
208 r5 : OF callback pointer as defined by IEEE 1275
209 bindings to powerpc. Only the 32-bit client interface
210 is currently supported
212 r3, r4 : address & length of an initrd if any or 0
214 The MMU is either on or off; the kernel will run the
215 trampoline located in arch/powerpc/kernel/prom_init.c to
216 extract the device-tree and other information from open
217 firmware and build a flattened device-tree as described
218 in b). prom_init() will then re-enter the kernel using
219 the second method. This trampoline code runs in the
220 context of the firmware, which is supposed to handle all
221 exceptions during that time.
223 b) Direct entry with a flattened device-tree block. This entry
224 point is called by a) after the OF trampoline and can also be
225 called directly by a bootloader that does not support the Open
226 Firmware client interface. It is also used by "kexec" to
227 implement "hot" booting of a new kernel from a previous
228 running one. This method is what I will describe in more
229 details in this document, as method a) is simply standard Open
230 Firmware, and thus should be implemented according to the
231 various standard documents defining it and its binding to the
232 PowerPC platform. The entry point definition then becomes:
234 r3 : physical pointer to the device-tree block
235 (defined in chapter II) in RAM
237 r4 : physical pointer to the kernel itself. This is
238 used by the assembly code to properly disable the MMU
239 in case you are entering the kernel with MMU enabled
240 and a non-1:1 mapping.
242 r5 : NULL (as to differentiate with method a)
244 Note about SMP entry: Either your firmware puts your other
245 CPUs in some sleep loop or spin loop in ROM where you can get
246 them out via a soft reset or some other means, in which case
247 you don't need to care, or you'll have to enter the kernel
248 with all CPUs. The way to do that with method b) will be
249 described in a later revision of this document.
257 Board supports (platforms) are not exclusive config options. An
258 arbitrary set of board supports can be built in a single kernel
259 image. The kernel will "know" what set of functions to use for a
260 given platform based on the content of the device-tree. Thus, you
263 a) add your platform support as a _boolean_ option in
264 arch/powerpc/Kconfig, following the example of PPC_PSERIES,
265 PPC_PMAC and PPC_MAPLE. The later is probably a good
266 example of a board support to start from.
268 b) create your main platform file as
269 "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
270 to the Makefile under the condition of your CONFIG_
271 option. This file will define a structure of type "ppc_md"
272 containing the various callbacks that the generic code will
273 use to get to your platform specific code
275 c) Add a reference to your "ppc_md" structure in the
276 "machines" table in arch/powerpc/kernel/setup_64.c if you are
279 d) request and get assigned a platform number (see PLATFORM_*
280 constants in include/asm-powerpc/processor.h
282 32-bit embedded kernels:
284 Currently, board support is essentially an exclusive config option.
285 The kernel is configured for a single platform. Part of the reason
286 for this is to keep kernels on embedded systems small and efficient;
287 part of this is due to the fact the code is already that way. In the
288 future, a kernel may support multiple platforms, but only if the
289 platforms feature the same core architecture. A single kernel build
290 cannot support both configurations with Book E and configurations
291 with classic Powerpc architectures.
293 32-bit embedded platforms that are moved into arch/powerpc using a
294 flattened device tree should adopt the merged tree practice of
295 setting ppc_md up dynamically, even though the kernel is currently
296 built with support for only a single platform at a time. This allows
297 unification of the setup code, and will make it easier to go to a
298 multiple-platform-support model in the future.
300 NOTE: I believe the above will be true once Ben's done with the merge
301 of the boot sequences.... someone speak up if this is wrong!
303 To add a 32-bit embedded platform support, follow the instructions
304 for 64-bit platforms above, with the exception that the Kconfig
305 option should be set up such that the kernel builds exclusively for
306 the platform selected. The processor type for the platform should
307 enable another config option to select the specific board
310 NOTE: If Ben doesn't merge the setup files, may need to change this to
314 I will describe later the boot process and various callbacks that
315 your platform should implement.
318 II - The DT block format
319 ========================
322 This chapter defines the actual format of the flattened device-tree
323 passed to the kernel. The actual content of it and kernel requirements
324 are described later. You can find example of code manipulating that
325 format in various places, including arch/powerpc/kernel/prom_init.c
326 which will generate a flattened device-tree from the Open Firmware
327 representation, or the fs2dt utility which is part of the kexec tools
328 which will generate one from a filesystem representation. It is
329 expected that a bootloader like uboot provides a bit more support,
330 that will be discussed later as well.
332 Note: The block has to be in main memory. It has to be accessible in
333 both real mode and virtual mode with no mapping other than main
334 memory. If you are writing a simple flash bootloader, it should copy
335 the block to RAM before passing it to the kernel.
341 The kernel is entered with r3 pointing to an area of memory that is
342 roughly described in include/asm-powerpc/prom.h by the structure
345 struct boot_param_header {
346 u32 magic; /* magic word OF_DT_HEADER */
347 u32 totalsize; /* total size of DT block */
348 u32 off_dt_struct; /* offset to structure */
349 u32 off_dt_strings; /* offset to strings */
350 u32 off_mem_rsvmap; /* offset to memory reserve map
352 u32 version; /* format version */
353 u32 last_comp_version; /* last compatible version */
355 /* version 2 fields below */
356 u32 boot_cpuid_phys; /* Which physical CPU id we're
358 /* version 3 fields below */
359 u32 size_dt_strings; /* size of the strings block */
361 /* version 17 fields below */
362 u32 size_dt_struct; /* size of the DT structure block */
365 Along with the constants:
367 /* Definitions used by the flattened device tree */
368 #define OF_DT_HEADER 0xd00dfeed /* 4: version,
370 #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
372 #define OF_DT_END_NODE 0x2 /* End node */
373 #define OF_DT_PROP 0x3 /* Property: name off,
375 #define OF_DT_END 0x9
377 All values in this header are in big endian format, the various
378 fields in this header are defined more precisely below. All
379 "offset" values are in bytes from the start of the header; that is
380 from the value of r3.
384 This is a magic value that "marks" the beginning of the
385 device-tree block header. It contains the value 0xd00dfeed and is
386 defined by the constant OF_DT_HEADER
390 This is the total size of the DT block including the header. The
391 "DT" block should enclose all data structures defined in this
392 chapter (who are pointed to by offsets in this header). That is,
393 the device-tree structure, strings, and the memory reserve map.
397 This is an offset from the beginning of the header to the start
398 of the "structure" part the device tree. (see 2) device tree)
402 This is an offset from the beginning of the header to the start
403 of the "strings" part of the device-tree
407 This is an offset from the beginning of the header to the start
408 of the reserved memory map. This map is a list of pairs of 64-
409 bit integers. Each pair is a physical address and a size. The
410 list is terminated by an entry of size 0. This map provides the
411 kernel with a list of physical memory areas that are "reserved"
412 and thus not to be used for memory allocations, especially during
413 early initialization. The kernel needs to allocate memory during
414 boot for things like un-flattening the device-tree, allocating an
415 MMU hash table, etc... Those allocations must be done in such a
416 way to avoid overriding critical things like, on Open Firmware
417 capable machines, the RTAS instance, or on some pSeries, the TCE
418 tables used for the iommu. Typically, the reserve map should
419 contain _at least_ this DT block itself (header,total_size). If
420 you are passing an initrd to the kernel, you should reserve it as
421 well. You do not need to reserve the kernel image itself. The map
422 should be 64-bit aligned.
426 This is the version of this structure. Version 1 stops
427 here. Version 2 adds an additional field boot_cpuid_phys.
428 Version 3 adds the size of the strings block, allowing the kernel
429 to reallocate it easily at boot and free up the unused flattened
430 structure after expansion. Version 16 introduces a new more
431 "compact" format for the tree itself that is however not backward
432 compatible. Version 17 adds an additional field, size_dt_struct,
433 allowing it to be reallocated or moved more easily (this is
434 particularly useful for bootloaders which need to make
435 adjustments to a device tree based on probed information). You
436 should always generate a structure of the highest version defined
437 at the time of your implementation. Currently that is version 17,
438 unless you explicitly aim at being backward compatible.
442 Last compatible version. This indicates down to what version of
443 the DT block you are backward compatible. For example, version 2
444 is backward compatible with version 1 (that is, a kernel build
445 for version 1 will be able to boot with a version 2 format). You
446 should put a 1 in this field if you generate a device tree of
447 version 1 to 3, or 16 if you generate a tree of version 16 or 17
448 using the new unit name format.
452 This field only exist on version 2 headers. It indicate which
453 physical CPU ID is calling the kernel entry point. This is used,
454 among others, by kexec. If you are on an SMP system, this value
455 should match the content of the "reg" property of the CPU node in
456 the device-tree corresponding to the CPU calling the kernel entry
457 point (see further chapters for more informations on the required
458 device-tree contents)
462 This field only exists on version 3 and later headers. It
463 gives the size of the "strings" section of the device tree (which
464 starts at the offset given by off_dt_strings).
468 This field only exists on version 17 and later headers. It gives
469 the size of the "structure" section of the device tree (which
470 starts at the offset given by off_dt_struct).
472 So the typical layout of a DT block (though the various parts don't
473 need to be in that order) looks like this (addresses go from top to
477 ------------------------------
478 r3 -> | struct boot_param_header |
479 ------------------------------
480 | (alignment gap) (*) |
481 ------------------------------
482 | memory reserve map |
483 ------------------------------
485 ------------------------------
487 | device-tree structure |
489 ------------------------------
491 ------------------------------
493 | device-tree strings |
495 -----> ------------------------------
500 (*) The alignment gaps are not necessarily present; their presence
501 and size are dependent on the various alignment requirements of
502 the individual data blocks.
505 2) Device tree generalities
506 ---------------------------
508 This device-tree itself is separated in two different blocks, a
509 structure block and a strings block. Both need to be aligned to a 4
512 First, let's quickly describe the device-tree concept before detailing
513 the storage format. This chapter does _not_ describe the detail of the
514 required types of nodes & properties for the kernel, this is done
515 later in chapter III.
517 The device-tree layout is strongly inherited from the definition of
518 the Open Firmware IEEE 1275 device-tree. It's basically a tree of
519 nodes, each node having two or more named properties. A property can
522 It is a tree, so each node has one and only one parent except for the
523 root node who has no parent.
525 A node has 2 names. The actual node name is generally contained in a
526 property of type "name" in the node property list whose value is a
527 zero terminated string and is mandatory for version 1 to 3 of the
528 format definition (as it is in Open Firmware). Version 16 makes it
529 optional as it can generate it from the unit name defined below.
531 There is also a "unit name" that is used to differentiate nodes with
532 the same name at the same level, it is usually made of the node
533 names, the "@" sign, and a "unit address", which definition is
534 specific to the bus type the node sits on.
536 The unit name doesn't exist as a property per-se but is included in
537 the device-tree structure. It is typically used to represent "path" in
538 the device-tree. More details about the actual format of these will be
541 The kernel powerpc generic code does not make any formal use of the
542 unit address (though some board support code may do) so the only real
543 requirement here for the unit address is to ensure uniqueness of
544 the node unit name at a given level of the tree. Nodes with no notion
545 of address and no possible sibling of the same name (like /memory or
546 /cpus) may omit the unit address in the context of this specification,
547 or use the "@0" default unit address. The unit name is used to define
548 a node "full path", which is the concatenation of all parent node
549 unit names separated with "/".
551 The root node doesn't have a defined name, and isn't required to have
552 a name property either if you are using version 3 or earlier of the
553 format. It also has no unit address (no @ symbol followed by a unit
554 address). The root node unit name is thus an empty string. The full
555 path to the root node is "/".
557 Every node which actually represents an actual device (that is, a node
558 which isn't only a virtual "container" for more nodes, like "/cpus"
559 is) is also required to have a "device_type" property indicating the
562 Finally, every node that can be referenced from a property in another
563 node is required to have a "linux,phandle" property. Real open
564 firmware implementations provide a unique "phandle" value for every
565 node that the "prom_init()" trampoline code turns into
566 "linux,phandle" properties. However, this is made optional if the
567 flattened device tree is used directly. An example of a node
568 referencing another node via "phandle" is when laying out the
569 interrupt tree which will be described in a further version of this
572 This "linux, phandle" property is a 32-bit value that uniquely
573 identifies a node. You are free to use whatever values or system of
574 values, internal pointers, or whatever to generate these, the only
575 requirement is that every node for which you provide that property has
576 a unique value for it.
578 Here is an example of a simple device-tree. In this example, an "o"
579 designates a node followed by the node unit name. Properties are
580 presented with their name followed by their content. "content"
581 represents an ASCII string (zero terminated) value, while <content>
582 represents a 32-bit hexadecimal value. The various nodes in this
583 example will be discussed in a later chapter. At this point, it is
584 only meant to give you a idea of what a device-tree looks like. I have
585 purposefully kept the "name" and "linux,phandle" properties which
586 aren't necessary in order to give you a better idea of what the tree
587 looks like in practice.
590 |- name = "device-tree"
591 |- model = "MyBoardName"
592 |- compatible = "MyBoardFamilyName"
593 |- #address-cells = <2>
595 |- linux,phandle = <0>
599 | | - linux,phandle = <1>
600 | | - #address-cells = <1>
601 | | - #size-cells = <0>
604 | |- name = "PowerPC,970"
605 | |- device_type = "cpu"
607 | |- clock-frequency = <5f5e1000>
609 | |- linux,phandle = <2>
613 | |- device_type = "memory"
614 | |- reg = <00000000 00000000 00000000 20000000>
615 | |- linux,phandle = <3>
619 |- bootargs = "root=/dev/sda2"
620 |- linux,phandle = <4>
622 This tree is almost a minimal tree. It pretty much contains the
623 minimal set of required nodes and properties to boot a linux kernel;
624 that is, some basic model informations at the root, the CPUs, and the
625 physical memory layout. It also includes misc information passed
626 through /chosen, like in this example, the platform type (mandatory)
627 and the kernel command line arguments (optional).
629 The /cpus/PowerPC,970@0/64-bit property is an example of a
630 property without a value. All other properties have a value. The
631 significance of the #address-cells and #size-cells properties will be
632 explained in chapter IV which defines precisely the required nodes and
633 properties and their content.
636 3) Device tree "structure" block
638 The structure of the device tree is a linearized tree structure. The
639 "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
640 ends that node definition. Child nodes are simply defined before
641 "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
642 bit value. The tree has to be "finished" with a OF_DT_END token
644 Here's the basic structure of a single node:
646 * token OF_DT_BEGIN_NODE (that is 0x00000001)
647 * for version 1 to 3, this is the node full path as a zero
648 terminated string, starting with "/". For version 16 and later,
649 this is the node unit name only (or an empty string for the
651 * [align gap to next 4 bytes boundary]
653 * token OF_DT_PROP (that is 0x00000003)
654 * 32-bit value of property value size in bytes (or 0 if no
656 * 32-bit value of offset in string block of property name
657 * property value data if any
658 * [align gap to next 4 bytes boundary]
659 * [child nodes if any]
660 * token OF_DT_END_NODE (that is 0x00000002)
662 So the node content can be summarized as a start token, a full path,
663 a list of properties, a list of child nodes, and an end token. Every
664 child node is a full node structure itself as defined above.
666 NOTE: The above definition requires that all property definitions for
667 a particular node MUST precede any subnode definitions for that node.
668 Although the structure would not be ambiguous if properties and
669 subnodes were intermingled, the kernel parser requires that the
670 properties come first (up until at least 2.6.22). Any tools
671 manipulating a flattened tree must take care to preserve this
674 4) Device tree "strings" block
676 In order to save space, property names, which are generally redundant,
677 are stored separately in the "strings" block. This block is simply the
678 whole bunch of zero terminated strings for all property names
679 concatenated together. The device-tree property definitions in the
680 structure block will contain offset values from the beginning of the
684 III - Required content of the device tree
685 =========================================
687 WARNING: All "linux,*" properties defined in this document apply only
688 to a flattened device-tree. If your platform uses a real
689 implementation of Open Firmware or an implementation compatible with
690 the Open Firmware client interface, those properties will be created
691 by the trampoline code in the kernel's prom_init() file. For example,
692 that's where you'll have to add code to detect your board model and
693 set the platform number. However, when using the flattened device-tree
694 entry point, there is no prom_init() pass, and thus you have to
695 provide those properties yourself.
698 1) Note about cells and address representation
699 ----------------------------------------------
701 The general rule is documented in the various Open Firmware
702 documentations. If you choose to describe a bus with the device-tree
703 and there exist an OF bus binding, then you should follow the
704 specification. However, the kernel does not require every single
705 device or bus to be described by the device tree.
707 In general, the format of an address for a device is defined by the
708 parent bus type, based on the #address-cells and #size-cells
709 properties. Note that the parent's parent definitions of #address-cells
710 and #size-cells are not inhereted so every node with children must specify
711 them. The kernel requires the root node to have those properties defining
712 addresses format for devices directly mapped on the processor bus.
714 Those 2 properties define 'cells' for representing an address and a
715 size. A "cell" is a 32-bit number. For example, if both contain 2
716 like the example tree given above, then an address and a size are both
717 composed of 2 cells, and each is a 64-bit number (cells are
718 concatenated and expected to be in big endian format). Another example
719 is the way Apple firmware defines them, with 2 cells for an address
720 and one cell for a size. Most 32-bit implementations should define
721 #address-cells and #size-cells to 1, which represents a 32-bit value.
722 Some 32-bit processors allow for physical addresses greater than 32
723 bits; these processors should define #address-cells as 2.
725 "reg" properties are always a tuple of the type "address size" where
726 the number of cells of address and size is specified by the bus
727 #address-cells and #size-cells. When a bus supports various address
728 spaces and other flags relative to a given address allocation (like
729 prefetchable, etc...) those flags are usually added to the top level
730 bits of the physical address. For example, a PCI physical address is
731 made of 3 cells, the bottom two containing the actual address itself
732 while the top cell contains address space indication, flags, and pci
733 bus & device numbers.
735 For busses that support dynamic allocation, it's the accepted practice
736 to then not provide the address in "reg" (keep it 0) though while
737 providing a flag indicating the address is dynamically allocated, and
738 then, to provide a separate "assigned-addresses" property that
739 contains the fully allocated addresses. See the PCI OF bindings for
742 In general, a simple bus with no address space bits and no dynamic
743 allocation is preferred if it reflects your hardware, as the existing
744 kernel address parsing functions will work out of the box. If you
745 define a bus type with a more complex address format, including things
746 like address space bits, you'll have to add a bus translator to the
747 prom_parse.c file of the recent kernels for your bus type.
749 The "reg" property only defines addresses and sizes (if #size-cells is
750 non-0) within a given bus. In order to translate addresses upward
751 (that is into parent bus addresses, and possibly into CPU physical
752 addresses), all busses must contain a "ranges" property. If the
753 "ranges" property is missing at a given level, it's assumed that
754 translation isn't possible, i.e., the registers are not visible on the
755 parent bus. The format of the "ranges" property for a bus is a list
758 bus address, parent bus address, size
760 "bus address" is in the format of the bus this bus node is defining,
761 that is, for a PCI bridge, it would be a PCI address. Thus, (bus
762 address, size) defines a range of addresses for child devices. "parent
763 bus address" is in the format of the parent bus of this bus. For
764 example, for a PCI host controller, that would be a CPU address. For a
765 PCI<->ISA bridge, that would be a PCI address. It defines the base
766 address in the parent bus where the beginning of that range is mapped.
768 For a new 64-bit powerpc board, I recommend either the 2/2 format or
769 Apple's 2/1 format which is slightly more compact since sizes usually
770 fit in a single 32-bit word. New 32-bit powerpc boards should use a
771 1/1 format, unless the processor supports physical addresses greater
772 than 32-bits, in which case a 2/1 format is recommended.
774 Alternatively, the "ranges" property may be empty, indicating that the
775 registers are visible on the parent bus using an identity mapping
776 translation. In other words, the parent bus address space is the same
777 as the child bus address space.
779 2) Note about "compatible" properties
780 -------------------------------------
782 These properties are optional, but recommended in devices and the root
783 node. The format of a "compatible" property is a list of concatenated
784 zero terminated strings. They allow a device to express its
785 compatibility with a family of similar devices, in some cases,
786 allowing a single driver to match against several devices regardless
787 of their actual names.
789 3) Note about "name" properties
790 -------------------------------
792 While earlier users of Open Firmware like OldWorld macintoshes tended
793 to use the actual device name for the "name" property, it's nowadays
794 considered a good practice to use a name that is closer to the device
795 class (often equal to device_type). For example, nowadays, ethernet
796 controllers are named "ethernet", an additional "model" property
797 defining precisely the chip type/model, and "compatible" property
798 defining the family in case a single driver can driver more than one
799 of these chips. However, the kernel doesn't generally put any
800 restriction on the "name" property; it is simply considered good
801 practice to follow the standard and its evolutions as closely as
804 Note also that the new format version 16 makes the "name" property
805 optional. If it's absent for a node, then the node's unit name is then
806 used to reconstruct the name. That is, the part of the unit name
807 before the "@" sign is used (or the entire unit name if no "@" sign
810 4) Note about node and property names and character set
811 -------------------------------------------------------
813 While open firmware provides more flexible usage of 8859-1, this
814 specification enforces more strict rules. Nodes and properties should
815 be comprised only of ASCII characters 'a' to 'z', '0' to
816 '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
817 allow uppercase characters 'A' to 'Z' (property names should be
818 lowercase. The fact that vendors like Apple don't respect this rule is
819 irrelevant here). Additionally, node and property names should always
820 begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
823 The maximum number of characters for both nodes and property names
824 is 31. In the case of node names, this is only the leftmost part of
825 a unit name (the pure "name" property), it doesn't include the unit
826 address which can extend beyond that limit.
829 5) Required nodes and properties
830 --------------------------------
831 These are all that are currently required. However, it is strongly
832 recommended that you expose PCI host bridges as documented in the
833 PCI binding to open firmware, and your interrupt tree as documented
834 in OF interrupt tree specification.
838 The root node requires some properties to be present:
840 - model : this is your board name/model
841 - #address-cells : address representation for "root" devices
842 - #size-cells: the size representation for "root" devices
843 - device_type : This property shouldn't be necessary. However, if
844 you decide to create a device_type for your root node, make sure it
845 is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
846 one for 64-bit, or a CHRP-type machine for 32-bit as this will
847 matched by the kernel this way.
849 Additionally, some recommended properties are:
851 - compatible : the board "family" generally finds its way here,
852 for example, if you have 2 board models with a similar layout,
853 that typically get driven by the same platform code in the
854 kernel, you would use a different "model" property but put a
855 value in "compatible". The kernel doesn't directly use that
856 value but it is generally useful.
858 The root node is also generally where you add additional properties
859 specific to your board like the serial number if any, that sort of
860 thing. It is recommended that if you add any "custom" property whose
861 name may clash with standard defined ones, you prefix them with your
862 vendor name and a comma.
866 This node is the parent of all individual CPU nodes. It doesn't
867 have any specific requirements, though it's generally good practice
870 #address-cells = <00000001>
871 #size-cells = <00000000>
873 This defines that the "address" for a CPU is a single cell, and has
874 no meaningful size. This is not necessary but the kernel will assume
875 that format when reading the "reg" properties of a CPU node, see
880 So under /cpus, you are supposed to create a node for every CPU on
881 the machine. There is no specific restriction on the name of the
882 CPU, though It's common practice to call it PowerPC,<name>. For
883 example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
887 - device_type : has to be "cpu"
888 - reg : This is the physical CPU number, it's a single 32-bit cell
889 and is also used as-is as the unit number for constructing the
890 unit name in the full path. For example, with 2 CPUs, you would
892 /cpus/PowerPC,970FX@0
893 /cpus/PowerPC,970FX@1
894 (unit addresses do not require leading zeroes)
895 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
896 - i-cache-block-size : one cell, L1 instruction cache block size in
898 - d-cache-size : one cell, size of L1 data cache in bytes
899 - i-cache-size : one cell, size of L1 instruction cache in bytes
901 (*) The cache "block" size is the size on which the cache management
902 instructions operate. Historically, this document used the cache
903 "line" size here which is incorrect. The kernel will prefer the cache
904 block size and will fallback to cache line size for backward
907 Recommended properties:
909 - timebase-frequency : a cell indicating the frequency of the
910 timebase in Hz. This is not directly used by the generic code,
911 but you are welcome to copy/paste the pSeries code for setting
912 the kernel timebase/decrementer calibration based on this
914 - clock-frequency : a cell indicating the CPU core clock frequency
915 in Hz. A new property will be defined for 64-bit values, but if
916 your frequency is < 4Ghz, one cell is enough. Here as well as
917 for the above, the common code doesn't use that property, but
918 you are welcome to re-use the pSeries or Maple one. A future
919 kernel version might provide a common function for this.
920 - d-cache-line-size : one cell, L1 data cache line size in bytes
921 if different from the block size
922 - i-cache-line-size : one cell, L1 instruction cache line size in
923 bytes if different from the block size
925 You are welcome to add any property you find relevant to your board,
926 like some information about the mechanism used to soft-reset the
927 CPUs. For example, Apple puts the GPIO number for CPU soft reset
928 lines in there as a "soft-reset" property since they start secondary
929 CPUs by soft-resetting them.
932 d) the /memory node(s)
934 To define the physical memory layout of your board, you should
935 create one or more memory node(s). You can either create a single
936 node with all memory ranges in its reg property, or you can create
937 several nodes, as you wish. The unit address (@ part) used for the
938 full path is the address of the first range of memory defined by a
939 given node. If you use a single memory node, this will typically be
944 - device_type : has to be "memory"
945 - reg : This property contains all the physical memory ranges of
946 your board. It's a list of addresses/sizes concatenated
947 together, with the number of cells of each defined by the
948 #address-cells and #size-cells of the root node. For example,
949 with both of these properties being 2 like in the example given
950 earlier, a 970 based machine with 6Gb of RAM could typically
951 have a "reg" property here that looks like:
953 00000000 00000000 00000000 80000000
954 00000001 00000000 00000001 00000000
956 That is a range starting at 0 of 0x80000000 bytes and a range
957 starting at 0x100000000 and of 0x100000000 bytes. You can see
958 that there is no memory covering the IO hole between 2Gb and
959 4Gb. Some vendors prefer splitting those ranges into smaller
960 segments, but the kernel doesn't care.
964 This node is a bit "special". Normally, that's where open firmware
965 puts some variable environment information, like the arguments, or
966 the default input/output devices.
968 This specification makes a few of these mandatory, but also defines
969 some linux-specific properties that would be normally constructed by
970 the prom_init() trampoline when booting with an OF client interface,
971 but that you have to provide yourself when using the flattened format.
973 Recommended properties:
975 - bootargs : This zero-terminated string is passed as the kernel
977 - linux,stdout-path : This is the full path to your standard
978 console device if any. Typically, if you have serial devices on
979 your board, you may want to put the full path to the one set as
980 the default console in the firmware here, for the kernel to pick
981 it up as its own default console. If you look at the function
982 set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
983 that the kernel tries to find out the default console and has
984 knowledge of various types like 8250 serial ports. You may want
985 to extend this function to add your own.
987 Note that u-boot creates and fills in the chosen node for platforms
990 (Note: a practice that is now obsolete was to include a property
991 under /chosen called interrupt-controller which had a phandle value
992 that pointed to the main interrupt controller)
994 f) the /soc<SOCname> node
996 This node is used to represent a system-on-a-chip (SOC) and must be
997 present if the processor is a SOC. The top-level soc node contains
998 information that is global to all devices on the SOC. The node name
999 should contain a unit address for the SOC, which is the base address
1000 of the memory-mapped register set for the SOC. The name of an soc
1001 node should start with "soc", and the remainder of the name should
1002 represent the part number for the soc. For example, the MPC8540's
1003 soc node would be called "soc8540".
1005 Required properties:
1007 - device_type : Should be "soc"
1008 - ranges : Should be defined as specified in 1) to describe the
1009 translation of SOC addresses for memory mapped SOC registers.
1010 - bus-frequency: Contains the bus frequency for the SOC node.
1011 Typically, the value of this field is filled in by the boot
1015 Recommended properties:
1017 - reg : This property defines the address and size of the
1018 memory-mapped registers that are used for the SOC node itself.
1019 It does not include the child device registers - these will be
1020 defined inside each child node. The address specified in the
1021 "reg" property should match the unit address of the SOC node.
1022 - #address-cells : Address representation for "soc" devices. The
1023 format of this field may vary depending on whether or not the
1024 device registers are memory mapped. For memory mapped
1025 registers, this field represents the number of cells needed to
1026 represent the address of the registers. For SOCs that do not
1027 use MMIO, a special address format should be defined that
1028 contains enough cells to represent the required information.
1029 See 1) above for more details on defining #address-cells.
1030 - #size-cells : Size representation for "soc" devices
1031 - #interrupt-cells : Defines the width of cells used to represent
1032 interrupts. Typically this value is <2>, which includes a
1033 32-bit number that represents the interrupt number, and a
1034 32-bit number that represents the interrupt sense and level.
1035 This field is only needed if the SOC contains an interrupt
1038 The SOC node may contain child nodes for each SOC device that the
1039 platform uses. Nodes should not be created for devices which exist
1040 on the SOC but are not used by a particular platform. See chapter VI
1041 for more information on how to specify devices that are part of a SOC.
1043 Example SOC node for the MPC8540:
1046 #address-cells = <1>;
1048 #interrupt-cells = <2>;
1049 device_type = "soc";
1050 ranges = <00000000 e0000000 00100000>
1051 reg = <e0000000 00003000>;
1052 bus-frequency = <0>;
1057 IV - "dtc", the device tree compiler
1058 ====================================
1061 dtc source code can be found at
1062 <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
1064 WARNING: This version is still in early development stage; the
1065 resulting device-tree "blobs" have not yet been validated with the
1066 kernel. The current generated bloc lacks a useful reserve map (it will
1067 be fixed to generate an empty one, it's up to the bootloader to fill
1068 it up) among others. The error handling needs work, bugs are lurking,
1071 dtc basically takes a device-tree in a given format and outputs a
1072 device-tree in another format. The currently supported formats are:
1077 - "dtb": "blob" format, that is a flattened device-tree block
1079 header all in a binary blob.
1080 - "dts": "source" format. This is a text file containing a
1081 "source" for a device-tree. The format is defined later in this
1083 - "fs" format. This is a representation equivalent to the
1084 output of /proc/device-tree, that is nodes are directories and
1085 properties are files
1090 - "dtb": "blob" format
1091 - "dts": "source" format
1092 - "asm": assembly language file. This is a file that can be
1093 sourced by gas to generate a device-tree "blob". That file can
1094 then simply be added to your Makefile. Additionally, the
1095 assembly file exports some symbols that can be used.
1098 The syntax of the dtc tool is
1100 dtc [-I <input-format>] [-O <output-format>]
1101 [-o output-filename] [-V output_version] input_filename
1104 The "output_version" defines what version of the "blob" format will be
1105 generated. Supported versions are 1,2,3 and 16. The default is
1106 currently version 3 but that may change in the future to version 16.
1108 Additionally, dtc performs various sanity checks on the tree, like the
1109 uniqueness of linux, phandle properties, validity of strings, etc...
1111 The format of the .dts "source" file is "C" like, supports C and C++
1117 The above is the "device-tree" definition. It's the only statement
1118 supported currently at the toplevel.
1121 property1 = "string_value"; /* define a property containing a 0
1125 property2 = <1234abcd>; /* define a property containing a
1126 * numerical 32-bit value (hexadecimal)
1129 property3 = <12345678 12345678 deadbeef>;
1130 /* define a property containing 3
1131 * numerical 32-bit values (cells) in
1134 property4 = [0a 0b 0c 0d de ea ad be ef];
1135 /* define a property whose content is
1136 * an arbitrary array of bytes
1139 childnode@addresss { /* define a child node named "childnode"
1140 * whose unit name is "childnode at
1144 childprop = "hello\n"; /* define a property "childprop" of
1145 * childnode (in this case, a string)
1150 Nodes can contain other nodes etc... thus defining the hierarchical
1151 structure of the tree.
1153 Strings support common escape sequences from C: "\n", "\t", "\r",
1154 "\(octal value)", "\x(hex value)".
1156 It is also suggested that you pipe your source file through cpp (gcc
1157 preprocessor) so you can use #include's, #define for constants, etc...
1159 Finally, various options are planned but not yet implemented, like
1160 automatic generation of phandles, labels (exported to the asm file so
1161 you can point to a property content and change it easily from whatever
1162 you link the device-tree with), label or path instead of numeric value
1163 in some cells to "point" to a node (replaced by a phandle at compile
1164 time), export of reserve map address to the asm file, ability to
1165 specify reserve map content at compile time, etc...
1167 We may provide a .h include file with common definitions of that
1168 proves useful for some properties (like building PCI properties or
1169 interrupt maps) though it may be better to add a notion of struct
1170 definitions to the compiler...
1173 V - Recommendations for a bootloader
1174 ====================================
1177 Here are some various ideas/recommendations that have been proposed
1178 while all this has been defined and implemented.
1180 - The bootloader may want to be able to use the device-tree itself
1181 and may want to manipulate it (to add/edit some properties,
1182 like physical memory size or kernel arguments). At this point, 2
1183 choices can be made. Either the bootloader works directly on the
1184 flattened format, or the bootloader has its own internal tree
1185 representation with pointers (similar to the kernel one) and
1186 re-flattens the tree when booting the kernel. The former is a bit
1187 more difficult to edit/modify, the later requires probably a bit
1188 more code to handle the tree structure. Note that the structure
1189 format has been designed so it's relatively easy to "insert"
1190 properties or nodes or delete them by just memmoving things
1191 around. It contains no internal offsets or pointers for this
1194 - An example of code for iterating nodes & retrieving properties
1195 directly from the flattened tree format can be found in the kernel
1196 file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
1197 its usage in early_init_devtree(), and the corresponding various
1198 early_init_dt_scan_*() callbacks. That code can be re-used in a
1199 GPL bootloader, and as the author of that code, I would be happy
1200 to discuss possible free licensing to any vendor who wishes to
1201 integrate all or part of this code into a non-GPL bootloader.
1205 VI - System-on-a-chip devices and nodes
1206 =======================================
1208 Many companies are now starting to develop system-on-a-chip
1209 processors, where the processor core (CPU) and many peripheral devices
1210 exist on a single piece of silicon. For these SOCs, an SOC node
1211 should be used that defines child nodes for the devices that make
1212 up the SOC. While platforms are not required to use this model in
1213 order to boot the kernel, it is highly encouraged that all SOC
1214 implementations define as complete a flat-device-tree as possible to
1215 describe the devices on the SOC. This will allow for the
1216 genericization of much of the kernel code.
1219 1) Defining child nodes of an SOC
1220 ---------------------------------
1222 Each device that is part of an SOC may have its own node entry inside
1223 the SOC node. For each device that is included in the SOC, the unit
1224 address property represents the address offset for this device's
1225 memory-mapped registers in the parent's address space. The parent's
1226 address space is defined by the "ranges" property in the top-level soc
1227 node. The "reg" property for each node that exists directly under the
1228 SOC node should contain the address mapping from the child address space
1229 to the parent SOC address space and the size of the device's
1230 memory-mapped register file.
1232 For many devices that may exist inside an SOC, there are predefined
1233 specifications for the format of the device tree node. All SOC child
1234 nodes should follow these specifications, except where noted in this
1237 See appendix A for an example partial SOC node definition for the
1241 2) Representing devices without a current OF specification
1242 ----------------------------------------------------------
1244 Currently, there are many devices on SOCs that do not have a standard
1245 representation pre-defined as part of the open firmware
1246 specifications, mainly because the boards that contain these SOCs are
1247 not currently booted using open firmware. This section contains
1248 descriptions for the SOC devices for which new nodes have been
1249 defined; this list will expand as more and more SOC-containing
1250 platforms are moved over to use the flattened-device-tree model.
1254 Required properties:
1256 - device_type : Should be "ethernet-phy"
1257 - interrupts : <a b> where a is the interrupt number and b is a
1258 field that represents an encoding of the sense and level
1259 information for the interrupt. This should be encoded based on
1260 the information in section 2) depending on the type of interrupt
1261 controller you have.
1262 - interrupt-parent : the phandle for the interrupt controller that
1263 services interrupts for this device.
1264 - reg : The ID number for the phy, usually a small integer
1265 - linux,phandle : phandle for this node; likely referenced by an
1266 ethernet controller node.
1272 linux,phandle = <2452000>
1273 interrupt-parent = <40000>;
1274 interrupts = <35 1>;
1276 device_type = "ethernet-phy";
1280 b) Interrupt controllers
1282 Some SOC devices contain interrupt controllers that are different
1283 from the standard Open PIC specification. The SOC device nodes for
1284 these types of controllers should be specified just like a standard
1285 OpenPIC controller. Sense and level information should be encoded
1286 as specified in section 2) of this chapter for each device that
1287 specifies an interrupt.
1292 linux,phandle = <40000>;
1293 interrupt-controller;
1294 #address-cells = <0>;
1295 reg = <40000 40000>;
1296 compatible = "chrp,open-pic";
1297 device_type = "open-pic";
1300 c) CFI or JEDEC memory-mapped NOR flash
1302 Flash chips (Memory Technology Devices) are often used for solid state
1303 file systems on embedded devices.
1305 - compatible : should contain the specific model of flash chip(s)
1306 used, if known, followed by either "cfi-flash" or "jedec-flash"
1307 - reg : Address range of the flash chip
1308 - bank-width : Width (in bytes) of the flash bank. Equal to the
1309 device width times the number of interleaved chips.
1310 - device-width : (optional) Width of a single flash chip. If
1311 omitted, assumed to be equal to 'bank-width'.
1312 - #address-cells, #size-cells : Must be present if the flash has
1313 sub-nodes representing partitions (see below). In this case
1314 both #address-cells and #size-cells must be equal to 1.
1316 For JEDEC compatible devices, the following additional properties
1319 - vendor-id : Contains the flash chip's vendor id (1 byte).
1320 - device-id : Contains the flash chip's device id (1 byte).
1322 In addition to the information on the flash bank itself, the
1323 device tree may optionally contain additional information
1324 describing partitions of the flash address space. This can be
1325 used on platforms which have strong conventions about which
1326 portions of the flash are used for what purposes, but which don't
1327 use an on-flash partition table such as RedBoot.
1329 Each partition is represented as a sub-node of the flash device.
1330 Each node's name represents the name of the corresponding
1331 partition of the flash device.
1334 - reg : The partition's offset and size within the flash bank.
1335 - label : (optional) The label / name for this flash partition.
1336 If omitted, the label is taken from the node name (excluding
1338 - read-only : (optional) This parameter, if present, is a hint to
1339 Linux that this flash partition should only be mounted
1340 read-only. This is usually used for flash partitions
1341 containing early-boot firmware images or data which should not
1347 compatible = "amd,am29lv128ml", "cfi-flash";
1348 reg = <ff000000 01000000>;
1351 #address-cells = <1>;
1359 reg = <f80000 80000>;
1364 d) 4xx/Axon EMAC ethernet nodes
1366 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1367 the Axon bridge. To operate this needs to interact with a ths
1368 special McMAL DMA controller, and sometimes an RGMII or ZMII
1369 interface. In addition to the nodes and properties described
1370 below, the node for the OPB bus on which the EMAC sits must have a
1371 correct clock-frequency property.
1373 i) The EMAC node itself
1375 Required properties:
1376 - device_type : "network"
1378 - compatible : compatible list, contains 2 entries, first is
1379 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1380 405gp, Axon) and second is either "ibm,emac" or
1381 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1383 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1384 - interrupt-parent : optional, if needed for interrupt mapping
1385 - reg : <registers mapping>
1386 - local-mac-address : 6 bytes, MAC address
1387 - mal-device : phandle of the associated McMAL node
1388 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1390 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1392 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1393 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1395 - max-frame-size : 1 cell, maximum frame size supported in bytes
1396 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1399 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1402 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1404 For Axon, 0x00000010
1405 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1407 For Axon, 0x00000100 (I think ...)
1408 - phy-mode : string, mode of operations of the PHY interface.
1409 Supported values are: "mii", "rmii", "smii", "rgmii",
1410 "tbi", "gmii", rtbi", "sgmii".
1411 For Axon on CAB, it is "rgmii"
1412 - mdio-device : 1 cell, required iff using shared MDIO registers
1413 (440EP). phandle of the EMAC to use to drive the
1414 MDIO lines for the PHY used by this EMAC.
1415 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1416 the ZMII device node
1417 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1418 channel or 0xffffffff if ZMII is only used for MDIO.
1419 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1420 of the RGMII device node.
1421 For Axon: phandle of plb5/plb4/opb/rgmii
1422 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1423 RGMII channel is used by this EMAC.
1424 Fox Axon: present, whatever value is appropriate for each
1425 EMAC, that is the content of the current (bogus) "phy-port"
1428 Optional properties:
1429 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1430 a search is performed.
1431 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1432 for, used if phy-address is absent. bit 0x00000001 is
1434 For Axon it can be absent, thouugh my current driver
1435 doesn't handle phy-address yet so for now, keep
1437 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1438 operations (if absent the value is the same as
1439 rx-fifo-size). For Axon, either absent or 2048.
1440 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1441 operations (if absent the value is the same as
1442 tx-fifo-size). For Axon, either absent or 2048.
1443 - tah-device : 1 cell, optional. If connected to a TAH engine for
1444 offload, phandle of the TAH device node.
1445 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1450 EMAC0: ethernet@40000800 {
1451 device_type = "network";
1452 compatible = "ibm,emac-440gp", "ibm,emac";
1453 interrupt-parent = <&UIC1>;
1454 interrupts = <1c 4 1d 4>;
1455 reg = <40000800 70>;
1456 local-mac-address = [00 04 AC E3 1B 1E];
1457 mal-device = <&MAL0>;
1458 mal-tx-channel = <0 1>;
1459 mal-rx-channel = <0>;
1461 max-frame-size = <5dc>;
1462 rx-fifo-size = <1000>;
1463 tx-fifo-size = <800>;
1465 phy-map = <00000001>;
1466 zmii-device = <&ZMII0>;
1472 Required properties:
1473 - device_type : "dma-controller"
1474 - compatible : compatible list, containing 2 entries, first is
1475 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1476 emac) and the second is either "ibm,mcmal" or
1478 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1479 - interrupts : <interrupt mapping for the MAL interrupts sources:
1480 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1481 For Axon: This is _different_ from the current
1482 firmware. We use the "delayed" interrupts for txeob
1483 and rxeob. Thus we end up with mapping those 5 MPIC
1484 interrupts, all level positive sensitive: 10, 11, 32,
1486 - dcr-reg : < DCR registers range >
1487 - dcr-parent : if needed for dcr-reg
1488 - num-tx-chans : 1 cell, number of Tx channels
1489 - num-rx-chans : 1 cell, number of Rx channels
1493 Required properties:
1494 - compatible : compatible list, containing 2 entries, first is
1495 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1496 EMAC) and the second is "ibm,zmii".
1497 For Axon, there is no ZMII node.
1498 - reg : <registers mapping>
1502 Required properties:
1503 - compatible : compatible list, containing 2 entries, first is
1504 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1505 EMAC) and the second is "ibm,rgmii".
1506 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1507 - reg : <registers mapping>
1508 - revision : as provided by the RGMII new version register if
1510 For Axon: 0x0000012a
1514 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
1515 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
1516 of standard device types (network, serial, etc.) and miscellanious
1517 devices (gpio, LCD, spi, etc). Also, since these devices are
1518 implemented within the fpga fabric every instance of the device can be
1519 synthesised with different options that change the behaviour.
1521 Each IP-core has a set of parameters which the FPGA designer can use to
1522 control how the core is synthesized. Historically, the EDK tool would
1523 extract the device parameters relevant to device drivers and copy them
1524 into an 'xparameters.h' in the form of #define symbols. This tells the
1525 device drivers how the IP cores are configured, but it requres the kernel
1526 to be recompiled every time the FPGA bitstream is resynthesized.
1528 The new approach is to export the parameters into the device tree and
1529 generate a new device tree each time the FPGA bitstream changes. The
1530 parameters which used to be exported as #defines will now become
1531 properties of the device node. In general, device nodes for IP-cores
1532 will take the following form:
1534 (name): (generic-name)@(base-address) {
1535 compatible = "xlnx,(ip-core-name)-(HW_VER)"
1536 [, (list of compatible devices), ...];
1537 reg = <(baseaddr) (size)>;
1538 interrupt-parent = <&interrupt-controller-phandle>;
1539 interrupts = < ... >;
1540 xlnx,(parameter1) = "(string-value)";
1541 xlnx,(parameter2) = <(int-value)>;
1544 (generic-name): an open firmware-style name that describes the
1545 generic class of device. Preferably, this is one word, such
1546 as 'serial' or 'ethernet'.
1547 (ip-core-name): the name of the ip block (given after the BEGIN
1548 directive in system.mhs). Should be in lowercase
1549 and all underscores '_' converted to dashes '-'.
1550 (name): is derived from the "PARAMETER INSTANCE" value.
1551 (parameter#): C_* parameters from system.mhs. The C_ prefix is
1552 dropped from the parameter name, the name is converted
1553 to lowercase and all underscore '_' characters are
1554 converted to dashes '-'.
1555 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
1556 (HW_VER): from the HW_VER parameter.
1557 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
1559 Typically, the compatible list will include the exact IP core version
1560 followed by an older IP core version which implements the same
1561 interface or any other device with the same interface.
1563 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
1565 For example, the following block from system.mhs:
1568 PARAMETER INSTANCE = opb_uartlite_0
1569 PARAMETER HW_VER = 1.00.b
1570 PARAMETER C_BAUDRATE = 115200
1571 PARAMETER C_DATA_BITS = 8
1572 PARAMETER C_ODD_PARITY = 0
1573 PARAMETER C_USE_PARITY = 0
1574 PARAMETER C_CLK_FREQ = 50000000
1575 PARAMETER C_BASEADDR = 0xEC100000
1576 PARAMETER C_HIGHADDR = 0xEC10FFFF
1577 BUS_INTERFACE SOPB = opb_7
1578 PORT OPB_Clk = CLK_50MHz
1579 PORT Interrupt = opb_uartlite_0_Interrupt
1580 PORT RX = opb_uartlite_0_RX
1581 PORT TX = opb_uartlite_0_TX
1582 PORT OPB_Rst = sys_bus_reset_0
1585 becomes the following device tree node:
1587 opb_uartlite_0: serial@ec100000 {
1588 device_type = "serial";
1589 compatible = "xlnx,opb-uartlite-1.00.b";
1590 reg = <ec100000 10000>;
1591 interrupt-parent = <&opb_intc_0>;
1592 interrupts = <1 0>; // got this from the opb_intc parameters
1593 current-speed = <d#115200>; // standard serial device prop
1594 clock-frequency = <d#50000000>; // standard serial device prop
1595 xlnx,data-bits = <8>;
1596 xlnx,odd-parity = <0>;
1597 xlnx,use-parity = <0>;
1600 Some IP cores actually implement 2 or more logical devices. In
1601 this case, the device should still describe the whole IP core with
1602 a single node and add a child node for each logical device. The
1603 ranges property can be used to translate from parent IP-core to the
1604 registers of each device. In addition, the parent node should be
1605 compatible with the bus type 'xlnx,compound', and should contain
1606 #address-cells and #size-cells, as with any other bus. (Note: this
1607 makes the assumption that both logical devices have the same bus
1608 binding. If this is not true, then separate nodes should be used
1609 for each logical device). The 'cell-index' property can be used to
1610 enumerate logical devices within an IP core. For example, the
1611 following is the system.mhs entry for the dual ps2 controller found
1612 on the ml403 reference design.
1614 BEGIN opb_ps2_dual_ref
1615 PARAMETER INSTANCE = opb_ps2_dual_ref_0
1616 PARAMETER HW_VER = 1.00.a
1617 PARAMETER C_BASEADDR = 0xA9000000
1618 PARAMETER C_HIGHADDR = 0xA9001FFF
1619 BUS_INTERFACE SOPB = opb_v20_0
1620 PORT Sys_Intr1 = ps2_1_intr
1621 PORT Sys_Intr2 = ps2_2_intr
1622 PORT Clkin1 = ps2_clk_rx_1
1623 PORT Clkin2 = ps2_clk_rx_2
1624 PORT Clkpd1 = ps2_clk_tx_1
1625 PORT Clkpd2 = ps2_clk_tx_2
1626 PORT Rx1 = ps2_d_rx_1
1627 PORT Rx2 = ps2_d_rx_2
1628 PORT Txpd1 = ps2_d_tx_1
1629 PORT Txpd2 = ps2_d_tx_2
1632 It would result in the following device tree nodes:
1634 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
1635 #address-cells = <1>;
1637 compatible = "xlnx,compound";
1638 ranges = <0 a9000000 2000>;
1639 // If this device had extra parameters, then they would
1642 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1644 interrupt-parent = <&opb_intc_0>;
1649 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1651 interrupt-parent = <&opb_intc_0>;
1657 Also, the system.mhs file defines bus attachments from the processor
1658 to the devices. The device tree structure should reflect the bus
1659 attachments. Again an example; this system.mhs fragment:
1661 BEGIN ppc405_virtex4
1662 PARAMETER INSTANCE = ppc405_0
1663 PARAMETER HW_VER = 1.01.a
1664 BUS_INTERFACE DPLB = plb_v34_0
1665 BUS_INTERFACE IPLB = plb_v34_0
1669 PARAMETER INSTANCE = opb_intc_0
1670 PARAMETER HW_VER = 1.00.c
1671 PARAMETER C_BASEADDR = 0xD1000FC0
1672 PARAMETER C_HIGHADDR = 0xD1000FDF
1673 BUS_INTERFACE SOPB = opb_v20_0
1677 PARAMETER INSTANCE = opb_uart16550_0
1678 PARAMETER HW_VER = 1.00.d
1679 PARAMETER C_BASEADDR = 0xa0000000
1680 PARAMETER C_HIGHADDR = 0xa0001FFF
1681 BUS_INTERFACE SOPB = opb_v20_0
1685 PARAMETER INSTANCE = plb_v34_0
1686 PARAMETER HW_VER = 1.02.a
1689 BEGIN plb_bram_if_cntlr
1690 PARAMETER INSTANCE = plb_bram_if_cntlr_0
1691 PARAMETER HW_VER = 1.00.b
1692 PARAMETER C_BASEADDR = 0xFFFF0000
1693 PARAMETER C_HIGHADDR = 0xFFFFFFFF
1694 BUS_INTERFACE SPLB = plb_v34_0
1697 BEGIN plb2opb_bridge
1698 PARAMETER INSTANCE = plb2opb_bridge_0
1699 PARAMETER HW_VER = 1.01.a
1700 PARAMETER C_RNG0_BASEADDR = 0x20000000
1701 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
1702 PARAMETER C_RNG1_BASEADDR = 0x60000000
1703 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
1704 PARAMETER C_RNG2_BASEADDR = 0x80000000
1705 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
1706 PARAMETER C_RNG3_BASEADDR = 0xC0000000
1707 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
1708 BUS_INTERFACE SPLB = plb_v34_0
1709 BUS_INTERFACE MOPB = opb_v20_0
1712 Gives this device tree (some properties removed for clarity):
1715 #address-cells = <1>;
1717 compatible = "xlnx,plb-v34-1.02.a";
1718 device_type = "ibm,plb";
1719 ranges; // 1:1 translation
1721 plb_bram_if_cntrl_0: bram@ffff0000 {
1722 reg = <ffff0000 10000>;
1726 #address-cells = <1>;
1728 ranges = <20000000 20000000 20000000
1729 60000000 60000000 20000000
1730 80000000 80000000 40000000
1731 c0000000 c0000000 20000000>;
1733 opb_uart16550_0: serial@a0000000 {
1734 reg = <a00000000 2000>;
1737 opb_intc_0: interrupt-controller@d1000fc0 {
1738 reg = <d1000fc0 20>;
1743 That covers the general approach to binding xilinx IP cores into the
1744 device tree. The following are bindings for specific devices:
1746 i) Xilinx ML300 Framebuffer
1748 Simple framebuffer device from the ML300 reference design (also on the
1749 ML403 reference design as well as others).
1751 Optional properties:
1752 - resolution = <xres yres> : pixel resolution of framebuffer. Some
1753 implementations use a different resolution.
1754 Default is <d#640 d#480>
1755 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
1756 Default is <d#1024 d#480>.
1757 - rotate-display (empty) : rotate display 180 degrees.
1759 ii) Xilinx SystemACE
1761 The Xilinx SystemACE device is used to program FPGAs from an FPGA
1762 bitstream stored on a CF card. It can also be used as a generic CF
1765 Optional properties:
1766 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
1768 iii) Xilinx EMAC and Xilinx TEMAC
1770 Xilinx Ethernet devices. In addition to general xilinx properties
1771 listed above, nodes for these devices should include a phy-handle
1772 property, and may include other common network device properties
1773 like local-mac-address.
1777 Xilinx uartlite devices are simple fixed speed serial ports.
1780 - current-speed : Baud rate of uartlite
1784 Xilinx hwicap devices provide access to the configuration logic
1785 of the FPGA through the Internal Configuration Access Port
1786 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
1787 readback of the configuration information, and some control over
1788 'warm boots' of the FPGA fabric.
1790 Required properties:
1791 - xlnx,family : The family of the FPGA, necessary since the
1792 capabilities of the underlying ICAP hardware
1793 differ between different families. May be
1794 'virtex2p', 'virtex4', or 'virtex5'.
1796 vi) Xilinx Uart 16550
1798 Xilinx UART 16550 devices are very similar to the NS16550 but with
1799 different register spacing and an offset from the base address.
1802 - clock-frequency : Frequency of the clock input
1803 - reg-offset : A value of 3 is required
1804 - reg-shift : A value of 2 is required
1806 f) USB EHCI controllers
1808 Required properties:
1809 - compatible : should be "usb-ehci".
1810 - reg : should contain at least address and length of the standard EHCI
1811 register set for the device. Optional platform-dependent registers
1812 (debug-port or other) can be also specified here, but only after
1813 definition of standard EHCI registers.
1814 - interrupts : one EHCI interrupt should be described here.
1815 If device registers are implemented in big endian mode, the device
1816 node should have "big-endian-regs" property.
1817 If controller implementation operates with big endian descriptors,
1818 "big-endian-desc" property should be specified.
1819 If both big endian registers and descriptors are used by the controller
1820 implementation, "big-endian" property can be specified instead of having
1821 both "big-endian-regs" and "big-endian-desc".
1823 Example (Sequoia 440EPx):
1825 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
1826 interrupt-parent = <&UIC0>;
1827 interrupts = <1a 4>;
1828 reg = <0 e0000300 90 0 e0000390 70>;
1832 r) Freescale Display Interface Unit
1834 The Freescale DIU is a LCD controller, with proper hardware, it can also
1837 Required properties:
1838 - compatible : should be "fsl-diu".
1839 - reg : should contain at least address and length of the DIU register
1841 - Interrupts : one DIU interrupt should be describe here.
1843 Example (MPC8610HPCD)
1845 compatible = "fsl,diu";
1846 reg = <0x2c000 100>;
1847 interrupts = <72 2>;
1848 interrupt-parent = <&mpic>;
1851 s) Freescale on board FPGA
1853 This is the memory-mapped registers for on board FPGA.
1855 Required properities:
1856 - compatible : should be "fsl,fpga-pixis".
1857 - reg : should contain the address and the lenght of the FPPGA register
1860 Example (MPC8610HPCD)
1861 board-control@e8000000 {
1862 compatible = "fsl,fpga-pixis";
1863 reg = <0xe8000000 32>;
1868 Currently defined compatibles:
1871 MDC and MDIO lines connected to GPIO controllers are listed in the
1872 gpios property as described in section VIII.1 in the following order:
1879 compatible = "virtual,mdio-gpio";
1880 #address-cells = <1>;
1882 gpios = <&qe_pio_a 11
1886 VII - Marvell Discovery mv64[345]6x System Controller chips
1887 ===========================================================
1889 The Marvell mv64[345]60 series of system controller chips contain
1890 many of the peripherals needed to implement a complete computer
1891 system. In this section, we define device tree nodes to describe
1892 the system controller chip itself and each of the peripherals
1893 which it contains. Compatible string values for each node are
1894 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
1896 1) The /system-controller node
1898 This node is used to represent the system-controller and must be
1899 present when the system uses a system contller chip. The top-level
1900 system-controller node contains information that is global to all
1901 devices within the system controller chip. The node name begins
1902 with "system-controller" followed by the unit address, which is
1903 the base address of the memory-mapped register set for the system
1906 Required properties:
1908 - ranges : Describes the translation of system controller addresses
1909 for memory mapped registers.
1910 - clock-frequency: Contains the main clock frequency for the system
1912 - reg : This property defines the address and size of the
1913 memory-mapped registers contained within the system controller
1914 chip. The address specified in the "reg" property should match
1915 the unit address of the system-controller node.
1916 - #address-cells : Address representation for system controller
1917 devices. This field represents the number of cells needed to
1918 represent the address of the memory-mapped registers of devices
1919 within the system controller chip.
1920 - #size-cells : Size representation for for the memory-mapped
1921 registers within the system controller chip.
1922 - #interrupt-cells : Defines the width of cells used to represent
1925 Optional properties:
1927 - model : The specific model of the system controller chip. Such
1928 as, "mv64360", "mv64460", or "mv64560".
1929 - compatible : A string identifying the compatibility identifiers
1930 of the system controller chip.
1932 The system-controller node contains child nodes for each system
1933 controller device that the platform uses. Nodes should not be created
1934 for devices which exist on the system controller chip but are not used
1936 Example Marvell Discovery mv64360 system-controller node:
1938 system-controller@f1000000 { /* Marvell Discovery mv64360 */
1939 #address-cells = <1>;
1941 model = "mv64360"; /* Default */
1942 compatible = "marvell,mv64360";
1943 clock-frequency = <133333333>;
1944 reg = <0xf1000000 0x10000>;
1945 virtual-reg = <0xf1000000>;
1946 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
1947 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
1948 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
1949 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
1950 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
1952 [ child node definitions... ]
1955 2) Child nodes of /system-controller
1957 a) Marvell Discovery MDIO bus
1959 The MDIO is a bus to which the PHY devices are connected. For each
1960 device that exists on this bus, a child node should be created. See
1961 the definition of the PHY node below for an example of how to define
1964 Required properties:
1965 - #address-cells : Should be <1>
1966 - #size-cells : Should be <0>
1967 - device_type : Should be "mdio"
1968 - compatible : Should be "marvell,mv64360-mdio"
1973 #address-cells = <1>;
1975 device_type = "mdio";
1976 compatible = "marvell,mv64360-mdio";
1984 b) Marvell Discovery ethernet controller
1986 The Discover ethernet controller is described with two levels
1987 of nodes. The first level describes an ethernet silicon block
1988 and the second level describes up to 3 ethernet nodes within
1989 that block. The reason for the multiple levels is that the
1990 registers for the node are interleaved within a single set
1991 of registers. The "ethernet-block" level describes the
1992 shared register set, and the "ethernet" nodes describe ethernet
1993 port-specific properties.
1997 Required properties:
1998 - #address-cells : <1>
2000 - compatible : "marvell,mv64360-eth-block"
2001 - reg : Offset and length of the register set for this block
2003 Example Discovery Ethernet block node:
2004 ethernet-block@2000 {
2005 #address-cells = <1>;
2007 compatible = "marvell,mv64360-eth-block";
2008 reg = <0x2000 0x2000>;
2016 Required properties:
2017 - device_type : Should be "network".
2018 - compatible : Should be "marvell,mv64360-eth".
2019 - reg : Should be <0>, <1>, or <2>, according to which registers
2020 within the silicon block the device uses.
2021 - interrupts : <a> where a is the interrupt number for the port.
2022 - interrupt-parent : the phandle for the interrupt controller
2023 that services interrupts for this device.
2024 - phy : the phandle for the PHY connected to this ethernet
2026 - local-mac-address : 6 bytes, MAC address
2028 Example Discovery Ethernet port node:
2030 device_type = "network";
2031 compatible = "marvell,mv64360-eth";
2034 interrupt-parent = <&PIC>;
2036 local-mac-address = [ 00 00 00 00 00 00 ];
2041 c) Marvell Discovery PHY nodes
2043 Required properties:
2044 - device_type : Should be "ethernet-phy"
2045 - interrupts : <a> where a is the interrupt number for this phy.
2046 - interrupt-parent : the phandle for the interrupt controller that
2047 services interrupts for this device.
2048 - reg : The ID number for the phy, usually a small integer
2050 Example Discovery PHY node:
2052 device_type = "ethernet-phy";
2053 compatible = "broadcom,bcm5421";
2054 interrupts = <76>; /* GPP 12 */
2055 interrupt-parent = <&PIC>;
2060 d) Marvell Discovery SDMA nodes
2062 Represent DMA hardware associated with the MPSC (multiprotocol
2063 serial controllers).
2065 Required properties:
2066 - compatible : "marvell,mv64360-sdma"
2067 - reg : Offset and length of the register set for this device
2068 - interrupts : <a> where a is the interrupt number for the DMA
2070 - interrupt-parent : the phandle for the interrupt controller
2071 that services interrupts for this device.
2073 Example Discovery SDMA node:
2075 compatible = "marvell,mv64360-sdma";
2076 reg = <0x4000 0xc18>;
2077 virtual-reg = <0xf1004000>;
2079 interrupt-parent = <&PIC>;
2083 e) Marvell Discovery BRG nodes
2085 Represent baud rate generator hardware associated with the MPSC
2086 (multiprotocol serial controllers).
2088 Required properties:
2089 - compatible : "marvell,mv64360-brg"
2090 - reg : Offset and length of the register set for this device
2091 - clock-src : A value from 0 to 15 which selects the clock
2092 source for the baud rate generator. This value corresponds
2093 to the CLKS value in the BRGx configuration register. See
2094 the mv64x60 User's Manual.
2095 - clock-frequence : The frequency (in Hz) of the baud rate
2096 generator's input clock.
2097 - current-speed : The current speed setting (presumably by
2098 firmware) of the baud rate generator.
2100 Example Discovery BRG node:
2102 compatible = "marvell,mv64360-brg";
2105 clock-frequency = <133333333>;
2106 current-speed = <9600>;
2110 f) Marvell Discovery CUNIT nodes
2112 Represent the Serial Communications Unit device hardware.
2114 Required properties:
2115 - reg : Offset and length of the register set for this device
2117 Example Discovery CUNIT node:
2119 reg = <0xf200 0x200>;
2123 g) Marvell Discovery MPSCROUTING nodes
2125 Represent the Discovery's MPSC routing hardware
2127 Required properties:
2128 - reg : Offset and length of the register set for this device
2130 Example Discovery CUNIT node:
2136 h) Marvell Discovery MPSCINTR nodes
2138 Represent the Discovery's MPSC DMA interrupt hardware registers
2139 (SDMA cause and mask registers).
2141 Required properties:
2142 - reg : Offset and length of the register set for this device
2144 Example Discovery MPSCINTR node:
2146 reg = <0xb800 0x100>;
2150 i) Marvell Discovery MPSC nodes
2152 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
2155 Required properties:
2156 - device_type : "serial"
2157 - compatible : "marvell,mv64360-mpsc"
2158 - reg : Offset and length of the register set for this device
2159 - sdma : the phandle for the SDMA node used by this port
2160 - brg : the phandle for the BRG node used by this port
2161 - cunit : the phandle for the CUNIT node used by this port
2162 - mpscrouting : the phandle for the MPSCROUTING node used by this port
2163 - mpscintr : the phandle for the MPSCINTR node used by this port
2164 - cell-index : the hardware index of this cell in the MPSC core
2165 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
2167 - interrupts : <a> where a is the interrupt number for the MPSC.
2168 - interrupt-parent : the phandle for the interrupt controller
2169 that services interrupts for this device.
2171 Example Discovery MPSCINTR node:
2173 device_type = "serial";
2174 compatible = "marvell,mv64360-mpsc";
2175 reg = <0x8000 0x38>;
2176 virtual-reg = <0xf1008000>;
2180 mpscrouting = <&MPSCROUTING>;
2181 mpscintr = <&MPSCINTR>;
2185 interrupt-parent = <&PIC>;
2189 j) Marvell Discovery Watch Dog Timer nodes
2191 Represent the Discovery's watchdog timer hardware
2193 Required properties:
2194 - compatible : "marvell,mv64360-wdt"
2195 - reg : Offset and length of the register set for this device
2197 Example Discovery Watch Dog Timer node:
2199 compatible = "marvell,mv64360-wdt";
2204 k) Marvell Discovery I2C nodes
2206 Represent the Discovery's I2C hardware
2208 Required properties:
2209 - device_type : "i2c"
2210 - compatible : "marvell,mv64360-i2c"
2211 - reg : Offset and length of the register set for this device
2212 - interrupts : <a> where a is the interrupt number for the I2C.
2213 - interrupt-parent : the phandle for the interrupt controller
2214 that services interrupts for this device.
2216 Example Discovery I2C node:
2217 compatible = "marvell,mv64360-i2c";
2218 reg = <0xc000 0x20>;
2219 virtual-reg = <0xf100c000>;
2221 interrupt-parent = <&PIC>;
2225 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
2227 Represent the Discovery's PIC hardware
2229 Required properties:
2230 - #interrupt-cells : <1>
2231 - #address-cells : <0>
2232 - compatible : "marvell,mv64360-pic"
2233 - reg : Offset and length of the register set for this device
2234 - interrupt-controller
2236 Example Discovery PIC node:
2238 #interrupt-cells = <1>;
2239 #address-cells = <0>;
2240 compatible = "marvell,mv64360-pic";
2242 interrupt-controller;
2246 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
2248 Represent the Discovery's MPP hardware
2250 Required properties:
2251 - compatible : "marvell,mv64360-mpp"
2252 - reg : Offset and length of the register set for this device
2254 Example Discovery MPP node:
2256 compatible = "marvell,mv64360-mpp";
2257 reg = <0xf000 0x10>;
2261 n) Marvell Discovery GPP (General Purpose Pins) nodes
2263 Represent the Discovery's GPP hardware
2265 Required properties:
2266 - compatible : "marvell,mv64360-gpp"
2267 - reg : Offset and length of the register set for this device
2269 Example Discovery GPP node:
2271 compatible = "marvell,mv64360-gpp";
2272 reg = <0xf100 0x20>;
2276 o) Marvell Discovery PCI host bridge node
2278 Represents the Discovery's PCI host bridge device. The properties
2279 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
2280 1275-1994. A typical value for the compatible property is
2281 "marvell,mv64360-pci".
2283 Example Discovery PCI host bridge node
2285 #address-cells = <3>;
2287 #interrupt-cells = <1>;
2288 device_type = "pci";
2289 compatible = "marvell,mv64360-pci";
2291 ranges = <0x01000000 0x0 0x0
2292 0x88000000 0x0 0x01000000
2293 0x02000000 0x0 0x80000000
2294 0x80000000 0x0 0x08000000>;
2295 bus-range = <0 255>;
2296 clock-frequency = <66000000>;
2297 interrupt-parent = <&PIC>;
2298 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2301 0x5000 0 0 1 &PIC 80
2302 0x5000 0 0 2 &PIC 81
2303 0x5000 0 0 3 &PIC 91
2304 0x5000 0 0 4 &PIC 93
2307 0x5800 0 0 1 &PIC 91
2308 0x5800 0 0 2 &PIC 93
2309 0x5800 0 0 3 &PIC 80
2310 0x5800 0 0 4 &PIC 81
2313 0x6000 0 0 1 &PIC 91
2314 0x6000 0 0 2 &PIC 93
2315 0x6000 0 0 3 &PIC 80
2316 0x6000 0 0 4 &PIC 81
2319 0x6800 0 0 1 &PIC 93
2320 0x6800 0 0 2 &PIC 80
2321 0x6800 0 0 3 &PIC 81
2322 0x6800 0 0 4 &PIC 91
2327 p) Marvell Discovery CPU Error nodes
2329 Represent the Discovery's CPU error handler device.
2331 Required properties:
2332 - compatible : "marvell,mv64360-cpu-error"
2333 - reg : Offset and length of the register set for this device
2334 - interrupts : the interrupt number for this device
2335 - interrupt-parent : the phandle for the interrupt controller
2336 that services interrupts for this device.
2338 Example Discovery CPU Error node:
2340 compatible = "marvell,mv64360-cpu-error";
2341 reg = <0x70 0x10 0x128 0x28>;
2343 interrupt-parent = <&PIC>;
2347 q) Marvell Discovery SRAM Controller nodes
2349 Represent the Discovery's SRAM controller device.
2351 Required properties:
2352 - compatible : "marvell,mv64360-sram-ctrl"
2353 - reg : Offset and length of the register set for this device
2354 - interrupts : the interrupt number for this device
2355 - interrupt-parent : the phandle for the interrupt controller
2356 that services interrupts for this device.
2358 Example Discovery SRAM Controller node:
2360 compatible = "marvell,mv64360-sram-ctrl";
2363 interrupt-parent = <&PIC>;
2367 r) Marvell Discovery PCI Error Handler nodes
2369 Represent the Discovery's PCI error handler device.
2371 Required properties:
2372 - compatible : "marvell,mv64360-pci-error"
2373 - reg : Offset and length of the register set for this device
2374 - interrupts : the interrupt number for this device
2375 - interrupt-parent : the phandle for the interrupt controller
2376 that services interrupts for this device.
2378 Example Discovery PCI Error Handler node:
2380 compatible = "marvell,mv64360-pci-error";
2381 reg = <0x1d40 0x40 0xc28 0x4>;
2383 interrupt-parent = <&PIC>;
2387 s) Marvell Discovery Memory Controller nodes
2389 Represent the Discovery's memory controller device.
2391 Required properties:
2392 - compatible : "marvell,mv64360-mem-ctrl"
2393 - reg : Offset and length of the register set for this device
2394 - interrupts : the interrupt number for this device
2395 - interrupt-parent : the phandle for the interrupt controller
2396 that services interrupts for this device.
2398 Example Discovery Memory Controller node:
2400 compatible = "marvell,mv64360-mem-ctrl";
2401 reg = <0x1400 0x60>;
2403 interrupt-parent = <&PIC>;
2407 VIII - Specifying interrupt information for devices
2408 ===================================================
2410 The device tree represents the busses and devices of a hardware
2411 system in a form similar to the physical bus topology of the
2414 In addition, a logical 'interrupt tree' exists which represents the
2415 hierarchy and routing of interrupts in the hardware.
2417 The interrupt tree model is fully described in the
2418 document "Open Firmware Recommended Practice: Interrupt
2419 Mapping Version 0.9". The document is available at:
2420 <http://playground.sun.com/1275/practice>.
2422 1) interrupts property
2423 ----------------------
2425 Devices that generate interrupts to a single interrupt controller
2426 should use the conventional OF representation described in the
2427 OF interrupt mapping documentation.
2429 Each device which generates interrupts must have an 'interrupt'
2430 property. The interrupt property value is an arbitrary number of
2431 of 'interrupt specifier' values which describe the interrupt or
2432 interrupts for the device.
2434 The encoding of an interrupt specifier is determined by the
2435 interrupt domain in which the device is located in the
2436 interrupt tree. The root of an interrupt domain specifies in
2437 its #interrupt-cells property the number of 32-bit cells
2438 required to encode an interrupt specifier. See the OF interrupt
2439 mapping documentation for a detailed description of domains.
2441 For example, the binding for the OpenPIC interrupt controller
2442 specifies an #interrupt-cells value of 2 to encode the interrupt
2443 number and level/sense information. All interrupt children in an
2444 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
2447 The PCI bus binding specifies a #interrupt-cell value of 1 to encode
2448 which interrupt pin (INTA,INTB,INTC,INTD) is used.
2450 2) interrupt-parent property
2451 ----------------------------
2453 The interrupt-parent property is specified to define an explicit
2454 link between a device node and its interrupt parent in
2455 the interrupt tree. The value of interrupt-parent is the
2456 phandle of the parent node.
2458 If the interrupt-parent property is not defined for a node, it's
2459 interrupt parent is assumed to be an ancestor in the node's
2460 _device tree_ hierarchy.
2462 3) OpenPIC Interrupt Controllers
2463 --------------------------------
2465 OpenPIC interrupt controllers require 2 cells to encode
2466 interrupt information. The first cell defines the interrupt
2467 number. The second cell defines the sense and level
2470 Sense and level information should be encoded as follows:
2472 0 = low to high edge sensitive type enabled
2473 1 = active low level sensitive type enabled
2474 2 = active high level sensitive type enabled
2475 3 = high to low edge sensitive type enabled
2477 4) ISA Interrupt Controllers
2478 ----------------------------
2480 ISA PIC interrupt controllers require 2 cells to encode
2481 interrupt information. The first cell defines the interrupt
2482 number. The second cell defines the sense and level
2485 ISA PIC interrupt controllers should adhere to the ISA PIC
2486 encodings listed below:
2488 0 = active low level sensitive type enabled
2489 1 = active high level sensitive type enabled
2490 2 = high to low edge sensitive type enabled
2491 3 = low to high edge sensitive type enabled
2493 IX - Specifying GPIO information for devices
2494 ============================================
2499 Nodes that makes use of GPIOs should define them using `gpios' property,
2500 format of which is: <&gpio-controller1-phandle gpio1-specifier
2501 &gpio-controller2-phandle gpio2-specifier
2502 0 /* holes are permitted, means no GPIO 3 */
2503 &gpio-controller4-phandle gpio4-specifier
2506 Note that gpio-specifier length is controller dependent.
2508 gpio-specifier may encode: bank, pin position inside the bank,
2509 whether pin is open-drain and whether pin is logically inverted.
2511 Example of the node using GPIOs:
2514 gpios = <&qe_pio_e 18 0>;
2517 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
2518 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2520 2) gpio-controller nodes
2521 ------------------------
2523 Every GPIO controller node must have #gpio-cells property defined,
2524 this information will be used to translate gpio-specifiers.
2526 Example of two SOC GPIO banks defined as gpio-controller nodes:
2528 qe_pio_a: gpio-controller@1400 {
2530 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
2531 reg = <0x1400 0x18>;
2535 qe_pio_e: gpio-controller@1460 {
2537 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
2538 reg = <0x1460 0x18>;
2542 X - Specifying Device Power Management Information (sleep property)
2543 ===================================================================
2545 Devices on SOCs often have mechanisms for placing devices into low-power
2546 states that are decoupled from the devices' own register blocks. Sometimes,
2547 this information is more complicated than a cell-index property can
2548 reasonably describe. Thus, each device controlled in such a manner
2549 may contain a "sleep" property which describes these connections.
2551 The sleep property consists of one or more sleep resources, each of
2552 which consists of a phandle to a sleep controller, followed by a
2553 controller-specific sleep specifier of zero or more cells.
2555 The semantics of what type of low power modes are possible are defined
2556 by the sleep controller. Some examples of the types of low power modes
2557 that may be supported are:
2559 - Dynamic: The device may be disabled or enabled at any time.
2560 - System Suspend: The device may request to be disabled or remain
2561 awake during system suspend, but will not be disabled until then.
2562 - Permanent: The device is disabled permanently (until the next hard
2565 Some devices may share a clock domain with each other, such that they should
2566 only be suspended when none of the devices are in use. Where reasonable,
2567 such nodes should be placed on a virtual bus, where the bus has the sleep
2568 property. If the clock domain is shared among devices that cannot be
2569 reasonably grouped in this manner, then create a virtual sleep controller
2570 (similar to an interrupt nexus, except that defining a standardized
2571 sleep-map should wait until its necessity is demonstrated).
2573 Appendix A - Sample SOC node for MPC8540
2574 ========================================
2577 #address-cells = <1>;
2579 compatible = "fsl,mpc8540-ccsr", "simple-bus";
2580 device_type = "soc";
2581 ranges = <0x00000000 0xe0000000 0x00100000>
2582 bus-frequency = <0>;
2583 interrupt-parent = <&pic>;
2586 #address-cells = <1>;
2588 device_type = "network";
2590 compatible = "gianfar", "simple-bus";
2591 reg = <0x24000 0x1000>;
2592 local-mac-address = [ 00 E0 0C 00 73 00 ];
2593 interrupts = <29 2 30 2 34 2>;
2594 phy-handle = <&phy0>;
2595 sleep = <&pmc 00000080>;
2599 reg = <0x24520 0x20>;
2600 compatible = "fsl,gianfar-mdio";
2602 phy0: ethernet-phy@0 {
2605 device_type = "ethernet-phy";
2608 phy1: ethernet-phy@1 {
2611 device_type = "ethernet-phy";
2614 phy3: ethernet-phy@3 {
2617 device_type = "ethernet-phy";
2623 device_type = "network";
2625 compatible = "gianfar";
2626 reg = <0x25000 0x1000>;
2627 local-mac-address = [ 00 E0 0C 00 73 01 ];
2628 interrupts = <13 2 14 2 18 2>;
2629 phy-handle = <&phy1>;
2630 sleep = <&pmc 00000040>;
2634 device_type = "network";
2636 compatible = "gianfar";
2637 reg = <0x26000 0x1000>;
2638 local-mac-address = [ 00 E0 0C 00 73 02 ];
2639 interrupts = <41 2>;
2640 phy-handle = <&phy3>;
2641 sleep = <&pmc 00000020>;
2645 #address-cells = <1>;
2647 compatible = "fsl,mpc8540-duart", "simple-bus";
2648 sleep = <&pmc 00000002>;
2652 device_type = "serial";
2653 compatible = "ns16550";
2654 reg = <0x4500 0x100>;
2655 clock-frequency = <0>;
2656 interrupts = <42 2>;
2660 device_type = "serial";
2661 compatible = "ns16550";
2662 reg = <0x4600 0x100>;
2663 clock-frequency = <0>;
2664 interrupts = <42 2>;
2669 interrupt-controller;
2670 #address-cells = <0>;
2671 #interrupt-cells = <2>;
2672 reg = <0x40000 0x40000>;
2673 compatible = "chrp,open-pic";
2674 device_type = "open-pic";
2678 interrupts = <43 2>;
2679 reg = <0x3000 0x100>;
2680 compatible = "fsl-i2c";
2682 sleep = <&pmc 00000004>;
2686 compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";
2687 reg = <0xe0070 0x20>;