1 Booting the Linux/ppc kernel without Open Firmware
2 --------------------------------------------------
4 (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
6 (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
7 Freescale Semiconductor, FSL SOC and 32-bit additions
8 (c) 2006 MontaVista Software, Inc.
9 Flash chip node definition
15 1) Entry point for arch/powerpc
18 II - The DT block format
20 2) Device tree generalities
21 3) Device tree "structure" block
22 4) Device tree "strings" block
24 III - Required content of the device tree
25 1) Note about cells and address representation
26 2) Note about "compatible" properties
27 3) Note about "name" properties
28 4) Note about node and property names and character set
29 5) Required nodes and properties
33 d) the /memory node(s)
35 f) the /soc<SOCname> node
37 IV - "dtc", the device tree compiler
39 V - Recommendations for a bootloader
41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification
45 b) Gianfar-compatible ethernet nodes
47 d) Interrupt controllers
49 f) Freescale SOC USB controllers
50 g) Freescale SOC SEC Security Engines
51 h) Board Control and Status (BCSR)
52 i) Freescale QUICC Engine module (QE)
53 j) CFI or JEDEC memory-mapped NOR flash
54 k) Global Utilities Block
55 l) Freescale Communications Processor Module
56 m) Chipselect/Local Bus
57 n) 4xx/Axon EMAC ethernet nodes
59 p) Freescale Synchronous Serial Interface
60 q) USB EHCI controllers
63 VII - Marvell Discovery mv64[345]6x System Controller chips
64 1) The /system-controller node
65 2) Child nodes of /system-controller
66 a) Marvell Discovery MDIO bus
67 b) Marvell Discovery ethernet controller
68 c) Marvell Discovery PHY nodes
69 d) Marvell Discovery SDMA nodes
70 e) Marvell Discovery BRG nodes
71 f) Marvell Discovery CUNIT nodes
72 g) Marvell Discovery MPSCROUTING nodes
73 h) Marvell Discovery MPSCINTR nodes
74 i) Marvell Discovery MPSC nodes
75 j) Marvell Discovery Watch Dog Timer nodes
76 k) Marvell Discovery I2C nodes
77 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
78 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
79 n) Marvell Discovery GPP (General Purpose Pins) nodes
80 o) Marvell Discovery PCI host bridge node
81 p) Marvell Discovery CPU Error nodes
82 q) Marvell Discovery SRAM Controller nodes
83 r) Marvell Discovery PCI Error Handler nodes
84 s) Marvell Discovery Memory Controller nodes
86 VIII - Specifying interrupt information for devices
87 1) interrupts property
88 2) interrupt-parent property
89 3) OpenPIC Interrupt Controllers
90 4) ISA Interrupt Controllers
92 VIII - Specifying GPIO information for devices
94 2) gpio-controller nodes
96 Appendix A - Sample SOC node for MPC8540
102 May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
104 May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
105 clarifies the fact that a lot of things are
106 optional, the kernel only requires a very
107 small device tree, though it is encouraged
108 to provide an as complete one as possible.
110 May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
112 - Define version 3 and new format version 16
113 for the DT block (version 16 needs kernel
114 patches, will be fwd separately).
115 String block now has a size, and full path
116 is replaced by unit name for more
118 linux,phandle is made optional, only nodes
119 that are referenced by other nodes need it.
120 "name" property is now automatically
121 deduced from the unit name
123 June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
124 OF_DT_END_NODE in structure definition.
125 - Change version 16 format to always align
126 property data to 4 bytes. Since tokens are
127 already aligned, that means no specific
128 required alignment between property size
129 and property data. The old style variable
130 alignment would make it impossible to do
131 "simple" insertion of properties using
132 memmove (thanks Milton for
133 noticing). Updated kernel patch as well
134 - Correct a few more alignment constraints
135 - Add a chapter about the device-tree
136 compiler and the textural representation of
137 the tree that can be "compiled" by dtc.
139 November 21, 2005: Rev 0.5
140 - Additions/generalizations for 32-bit
141 - Changed to reflect the new arch/powerpc
147 - Add some definitions of interrupt tree (simple/complex)
148 - Add some definitions for PCI host bridges
149 - Add some common address format examples
150 - Add definitions for standard properties and "compatible"
151 names for cells that are not already defined by the existing
153 - Compare FSL SOC use of PCI to standard and make sure no new
154 node definition required.
155 - Add more information about node definitions for SOC devices
156 that currently have no standard, like the FSL CPM.
162 During the recent development of the Linux/ppc64 kernel, and more
163 specifically, the addition of new platform types outside of the old
164 IBM pSeries/iSeries pair, it was decided to enforce some strict rules
165 regarding the kernel entry and bootloader <-> kernel interfaces, in
166 order to avoid the degeneration that had become the ppc32 kernel entry
167 point and the way a new platform should be added to the kernel. The
168 legacy iSeries platform breaks those rules as it predates this scheme,
169 but no new board support will be accepted in the main tree that
170 doesn't follows them properly. In addition, since the advent of the
171 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
172 platforms and 32-bit platforms which move into arch/powerpc will be
173 required to use these rules as well.
175 The main requirement that will be defined in more detail below is
176 the presence of a device-tree whose format is defined after Open
177 Firmware specification. However, in order to make life easier
178 to embedded board vendors, the kernel doesn't require the device-tree
179 to represent every device in the system and only requires some nodes
180 and properties to be present. This will be described in detail in
181 section III, but, for example, the kernel does not require you to
182 create a node for every PCI device in the system. It is a requirement
183 to have a node for PCI host bridges in order to provide interrupt
184 routing informations and memory/IO ranges, among others. It is also
185 recommended to define nodes for on chip devices and other busses that
186 don't specifically fit in an existing OF specification. This creates a
187 great flexibility in the way the kernel can then probe those and match
188 drivers to device, without having to hard code all sorts of tables. It
189 also makes it more flexible for board vendors to do minor hardware
190 upgrades without significantly impacting the kernel code or cluttering
191 it with special cases.
194 1) Entry point for arch/powerpc
195 -------------------------------
197 There is one and one single entry point to the kernel, at the start
198 of the kernel image. That entry point supports two calling
201 a) Boot from Open Firmware. If your firmware is compatible
202 with Open Firmware (IEEE 1275) or provides an OF compatible
203 client interface API (support for "interpret" callback of
204 forth words isn't required), you can enter the kernel with:
206 r5 : OF callback pointer as defined by IEEE 1275
207 bindings to powerpc. Only the 32-bit client interface
208 is currently supported
210 r3, r4 : address & length of an initrd if any or 0
212 The MMU is either on or off; the kernel will run the
213 trampoline located in arch/powerpc/kernel/prom_init.c to
214 extract the device-tree and other information from open
215 firmware and build a flattened device-tree as described
216 in b). prom_init() will then re-enter the kernel using
217 the second method. This trampoline code runs in the
218 context of the firmware, which is supposed to handle all
219 exceptions during that time.
221 b) Direct entry with a flattened device-tree block. This entry
222 point is called by a) after the OF trampoline and can also be
223 called directly by a bootloader that does not support the Open
224 Firmware client interface. It is also used by "kexec" to
225 implement "hot" booting of a new kernel from a previous
226 running one. This method is what I will describe in more
227 details in this document, as method a) is simply standard Open
228 Firmware, and thus should be implemented according to the
229 various standard documents defining it and its binding to the
230 PowerPC platform. The entry point definition then becomes:
232 r3 : physical pointer to the device-tree block
233 (defined in chapter II) in RAM
235 r4 : physical pointer to the kernel itself. This is
236 used by the assembly code to properly disable the MMU
237 in case you are entering the kernel with MMU enabled
238 and a non-1:1 mapping.
240 r5 : NULL (as to differentiate with method a)
242 Note about SMP entry: Either your firmware puts your other
243 CPUs in some sleep loop or spin loop in ROM where you can get
244 them out via a soft reset or some other means, in which case
245 you don't need to care, or you'll have to enter the kernel
246 with all CPUs. The way to do that with method b) will be
247 described in a later revision of this document.
255 Board supports (platforms) are not exclusive config options. An
256 arbitrary set of board supports can be built in a single kernel
257 image. The kernel will "know" what set of functions to use for a
258 given platform based on the content of the device-tree. Thus, you
261 a) add your platform support as a _boolean_ option in
262 arch/powerpc/Kconfig, following the example of PPC_PSERIES,
263 PPC_PMAC and PPC_MAPLE. The later is probably a good
264 example of a board support to start from.
266 b) create your main platform file as
267 "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
268 to the Makefile under the condition of your CONFIG_
269 option. This file will define a structure of type "ppc_md"
270 containing the various callbacks that the generic code will
271 use to get to your platform specific code
273 c) Add a reference to your "ppc_md" structure in the
274 "machines" table in arch/powerpc/kernel/setup_64.c if you are
277 d) request and get assigned a platform number (see PLATFORM_*
278 constants in include/asm-powerpc/processor.h
280 32-bit embedded kernels:
282 Currently, board support is essentially an exclusive config option.
283 The kernel is configured for a single platform. Part of the reason
284 for this is to keep kernels on embedded systems small and efficient;
285 part of this is due to the fact the code is already that way. In the
286 future, a kernel may support multiple platforms, but only if the
287 platforms feature the same core architecture. A single kernel build
288 cannot support both configurations with Book E and configurations
289 with classic Powerpc architectures.
291 32-bit embedded platforms that are moved into arch/powerpc using a
292 flattened device tree should adopt the merged tree practice of
293 setting ppc_md up dynamically, even though the kernel is currently
294 built with support for only a single platform at a time. This allows
295 unification of the setup code, and will make it easier to go to a
296 multiple-platform-support model in the future.
298 NOTE: I believe the above will be true once Ben's done with the merge
299 of the boot sequences.... someone speak up if this is wrong!
301 To add a 32-bit embedded platform support, follow the instructions
302 for 64-bit platforms above, with the exception that the Kconfig
303 option should be set up such that the kernel builds exclusively for
304 the platform selected. The processor type for the platform should
305 enable another config option to select the specific board
308 NOTE: If Ben doesn't merge the setup files, may need to change this to
312 I will describe later the boot process and various callbacks that
313 your platform should implement.
316 II - The DT block format
317 ========================
320 This chapter defines the actual format of the flattened device-tree
321 passed to the kernel. The actual content of it and kernel requirements
322 are described later. You can find example of code manipulating that
323 format in various places, including arch/powerpc/kernel/prom_init.c
324 which will generate a flattened device-tree from the Open Firmware
325 representation, or the fs2dt utility which is part of the kexec tools
326 which will generate one from a filesystem representation. It is
327 expected that a bootloader like uboot provides a bit more support,
328 that will be discussed later as well.
330 Note: The block has to be in main memory. It has to be accessible in
331 both real mode and virtual mode with no mapping other than main
332 memory. If you are writing a simple flash bootloader, it should copy
333 the block to RAM before passing it to the kernel.
339 The kernel is entered with r3 pointing to an area of memory that is
340 roughly described in include/asm-powerpc/prom.h by the structure
343 struct boot_param_header {
344 u32 magic; /* magic word OF_DT_HEADER */
345 u32 totalsize; /* total size of DT block */
346 u32 off_dt_struct; /* offset to structure */
347 u32 off_dt_strings; /* offset to strings */
348 u32 off_mem_rsvmap; /* offset to memory reserve map
350 u32 version; /* format version */
351 u32 last_comp_version; /* last compatible version */
353 /* version 2 fields below */
354 u32 boot_cpuid_phys; /* Which physical CPU id we're
356 /* version 3 fields below */
357 u32 size_dt_strings; /* size of the strings block */
359 /* version 17 fields below */
360 u32 size_dt_struct; /* size of the DT structure block */
363 Along with the constants:
365 /* Definitions used by the flattened device tree */
366 #define OF_DT_HEADER 0xd00dfeed /* 4: version,
368 #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
370 #define OF_DT_END_NODE 0x2 /* End node */
371 #define OF_DT_PROP 0x3 /* Property: name off,
373 #define OF_DT_END 0x9
375 All values in this header are in big endian format, the various
376 fields in this header are defined more precisely below. All
377 "offset" values are in bytes from the start of the header; that is
378 from the value of r3.
382 This is a magic value that "marks" the beginning of the
383 device-tree block header. It contains the value 0xd00dfeed and is
384 defined by the constant OF_DT_HEADER
388 This is the total size of the DT block including the header. The
389 "DT" block should enclose all data structures defined in this
390 chapter (who are pointed to by offsets in this header). That is,
391 the device-tree structure, strings, and the memory reserve map.
395 This is an offset from the beginning of the header to the start
396 of the "structure" part the device tree. (see 2) device tree)
400 This is an offset from the beginning of the header to the start
401 of the "strings" part of the device-tree
405 This is an offset from the beginning of the header to the start
406 of the reserved memory map. This map is a list of pairs of 64-
407 bit integers. Each pair is a physical address and a size. The
408 list is terminated by an entry of size 0. This map provides the
409 kernel with a list of physical memory areas that are "reserved"
410 and thus not to be used for memory allocations, especially during
411 early initialization. The kernel needs to allocate memory during
412 boot for things like un-flattening the device-tree, allocating an
413 MMU hash table, etc... Those allocations must be done in such a
414 way to avoid overriding critical things like, on Open Firmware
415 capable machines, the RTAS instance, or on some pSeries, the TCE
416 tables used for the iommu. Typically, the reserve map should
417 contain _at least_ this DT block itself (header,total_size). If
418 you are passing an initrd to the kernel, you should reserve it as
419 well. You do not need to reserve the kernel image itself. The map
420 should be 64-bit aligned.
424 This is the version of this structure. Version 1 stops
425 here. Version 2 adds an additional field boot_cpuid_phys.
426 Version 3 adds the size of the strings block, allowing the kernel
427 to reallocate it easily at boot and free up the unused flattened
428 structure after expansion. Version 16 introduces a new more
429 "compact" format for the tree itself that is however not backward
430 compatible. Version 17 adds an additional field, size_dt_struct,
431 allowing it to be reallocated or moved more easily (this is
432 particularly useful for bootloaders which need to make
433 adjustments to a device tree based on probed information). You
434 should always generate a structure of the highest version defined
435 at the time of your implementation. Currently that is version 17,
436 unless you explicitly aim at being backward compatible.
440 Last compatible version. This indicates down to what version of
441 the DT block you are backward compatible. For example, version 2
442 is backward compatible with version 1 (that is, a kernel build
443 for version 1 will be able to boot with a version 2 format). You
444 should put a 1 in this field if you generate a device tree of
445 version 1 to 3, or 16 if you generate a tree of version 16 or 17
446 using the new unit name format.
450 This field only exist on version 2 headers. It indicate which
451 physical CPU ID is calling the kernel entry point. This is used,
452 among others, by kexec. If you are on an SMP system, this value
453 should match the content of the "reg" property of the CPU node in
454 the device-tree corresponding to the CPU calling the kernel entry
455 point (see further chapters for more informations on the required
456 device-tree contents)
460 This field only exists on version 3 and later headers. It
461 gives the size of the "strings" section of the device tree (which
462 starts at the offset given by off_dt_strings).
466 This field only exists on version 17 and later headers. It gives
467 the size of the "structure" section of the device tree (which
468 starts at the offset given by off_dt_struct).
470 So the typical layout of a DT block (though the various parts don't
471 need to be in that order) looks like this (addresses go from top to
475 ------------------------------
476 r3 -> | struct boot_param_header |
477 ------------------------------
478 | (alignment gap) (*) |
479 ------------------------------
480 | memory reserve map |
481 ------------------------------
483 ------------------------------
485 | device-tree structure |
487 ------------------------------
489 ------------------------------
491 | device-tree strings |
493 -----> ------------------------------
498 (*) The alignment gaps are not necessarily present; their presence
499 and size are dependent on the various alignment requirements of
500 the individual data blocks.
503 2) Device tree generalities
504 ---------------------------
506 This device-tree itself is separated in two different blocks, a
507 structure block and a strings block. Both need to be aligned to a 4
510 First, let's quickly describe the device-tree concept before detailing
511 the storage format. This chapter does _not_ describe the detail of the
512 required types of nodes & properties for the kernel, this is done
513 later in chapter III.
515 The device-tree layout is strongly inherited from the definition of
516 the Open Firmware IEEE 1275 device-tree. It's basically a tree of
517 nodes, each node having two or more named properties. A property can
520 It is a tree, so each node has one and only one parent except for the
521 root node who has no parent.
523 A node has 2 names. The actual node name is generally contained in a
524 property of type "name" in the node property list whose value is a
525 zero terminated string and is mandatory for version 1 to 3 of the
526 format definition (as it is in Open Firmware). Version 16 makes it
527 optional as it can generate it from the unit name defined below.
529 There is also a "unit name" that is used to differentiate nodes with
530 the same name at the same level, it is usually made of the node
531 names, the "@" sign, and a "unit address", which definition is
532 specific to the bus type the node sits on.
534 The unit name doesn't exist as a property per-se but is included in
535 the device-tree structure. It is typically used to represent "path" in
536 the device-tree. More details about the actual format of these will be
539 The kernel powerpc generic code does not make any formal use of the
540 unit address (though some board support code may do) so the only real
541 requirement here for the unit address is to ensure uniqueness of
542 the node unit name at a given level of the tree. Nodes with no notion
543 of address and no possible sibling of the same name (like /memory or
544 /cpus) may omit the unit address in the context of this specification,
545 or use the "@0" default unit address. The unit name is used to define
546 a node "full path", which is the concatenation of all parent node
547 unit names separated with "/".
549 The root node doesn't have a defined name, and isn't required to have
550 a name property either if you are using version 3 or earlier of the
551 format. It also has no unit address (no @ symbol followed by a unit
552 address). The root node unit name is thus an empty string. The full
553 path to the root node is "/".
555 Every node which actually represents an actual device (that is, a node
556 which isn't only a virtual "container" for more nodes, like "/cpus"
557 is) is also required to have a "device_type" property indicating the
560 Finally, every node that can be referenced from a property in another
561 node is required to have a "linux,phandle" property. Real open
562 firmware implementations provide a unique "phandle" value for every
563 node that the "prom_init()" trampoline code turns into
564 "linux,phandle" properties. However, this is made optional if the
565 flattened device tree is used directly. An example of a node
566 referencing another node via "phandle" is when laying out the
567 interrupt tree which will be described in a further version of this
570 This "linux, phandle" property is a 32-bit value that uniquely
571 identifies a node. You are free to use whatever values or system of
572 values, internal pointers, or whatever to generate these, the only
573 requirement is that every node for which you provide that property has
574 a unique value for it.
576 Here is an example of a simple device-tree. In this example, an "o"
577 designates a node followed by the node unit name. Properties are
578 presented with their name followed by their content. "content"
579 represents an ASCII string (zero terminated) value, while <content>
580 represents a 32-bit hexadecimal value. The various nodes in this
581 example will be discussed in a later chapter. At this point, it is
582 only meant to give you a idea of what a device-tree looks like. I have
583 purposefully kept the "name" and "linux,phandle" properties which
584 aren't necessary in order to give you a better idea of what the tree
585 looks like in practice.
588 |- name = "device-tree"
589 |- model = "MyBoardName"
590 |- compatible = "MyBoardFamilyName"
591 |- #address-cells = <2>
593 |- linux,phandle = <0>
597 | | - linux,phandle = <1>
598 | | - #address-cells = <1>
599 | | - #size-cells = <0>
602 | |- name = "PowerPC,970"
603 | |- device_type = "cpu"
605 | |- clock-frequency = <5f5e1000>
607 | |- linux,phandle = <2>
611 | |- device_type = "memory"
612 | |- reg = <00000000 00000000 00000000 20000000>
613 | |- linux,phandle = <3>
617 |- bootargs = "root=/dev/sda2"
618 |- linux,phandle = <4>
620 This tree is almost a minimal tree. It pretty much contains the
621 minimal set of required nodes and properties to boot a linux kernel;
622 that is, some basic model informations at the root, the CPUs, and the
623 physical memory layout. It also includes misc information passed
624 through /chosen, like in this example, the platform type (mandatory)
625 and the kernel command line arguments (optional).
627 The /cpus/PowerPC,970@0/64-bit property is an example of a
628 property without a value. All other properties have a value. The
629 significance of the #address-cells and #size-cells properties will be
630 explained in chapter IV which defines precisely the required nodes and
631 properties and their content.
634 3) Device tree "structure" block
636 The structure of the device tree is a linearized tree structure. The
637 "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
638 ends that node definition. Child nodes are simply defined before
639 "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
640 bit value. The tree has to be "finished" with a OF_DT_END token
642 Here's the basic structure of a single node:
644 * token OF_DT_BEGIN_NODE (that is 0x00000001)
645 * for version 1 to 3, this is the node full path as a zero
646 terminated string, starting with "/". For version 16 and later,
647 this is the node unit name only (or an empty string for the
649 * [align gap to next 4 bytes boundary]
651 * token OF_DT_PROP (that is 0x00000003)
652 * 32-bit value of property value size in bytes (or 0 if no
654 * 32-bit value of offset in string block of property name
655 * property value data if any
656 * [align gap to next 4 bytes boundary]
657 * [child nodes if any]
658 * token OF_DT_END_NODE (that is 0x00000002)
660 So the node content can be summarized as a start token, a full path,
661 a list of properties, a list of child nodes, and an end token. Every
662 child node is a full node structure itself as defined above.
664 NOTE: The above definition requires that all property definitions for
665 a particular node MUST precede any subnode definitions for that node.
666 Although the structure would not be ambiguous if properties and
667 subnodes were intermingled, the kernel parser requires that the
668 properties come first (up until at least 2.6.22). Any tools
669 manipulating a flattened tree must take care to preserve this
672 4) Device tree "strings" block
674 In order to save space, property names, which are generally redundant,
675 are stored separately in the "strings" block. This block is simply the
676 whole bunch of zero terminated strings for all property names
677 concatenated together. The device-tree property definitions in the
678 structure block will contain offset values from the beginning of the
682 III - Required content of the device tree
683 =========================================
685 WARNING: All "linux,*" properties defined in this document apply only
686 to a flattened device-tree. If your platform uses a real
687 implementation of Open Firmware or an implementation compatible with
688 the Open Firmware client interface, those properties will be created
689 by the trampoline code in the kernel's prom_init() file. For example,
690 that's where you'll have to add code to detect your board model and
691 set the platform number. However, when using the flattened device-tree
692 entry point, there is no prom_init() pass, and thus you have to
693 provide those properties yourself.
696 1) Note about cells and address representation
697 ----------------------------------------------
699 The general rule is documented in the various Open Firmware
700 documentations. If you choose to describe a bus with the device-tree
701 and there exist an OF bus binding, then you should follow the
702 specification. However, the kernel does not require every single
703 device or bus to be described by the device tree.
705 In general, the format of an address for a device is defined by the
706 parent bus type, based on the #address-cells and #size-cells
707 properties. Note that the parent's parent definitions of #address-cells
708 and #size-cells are not inhereted so every node with children must specify
709 them. The kernel requires the root node to have those properties defining
710 addresses format for devices directly mapped on the processor bus.
712 Those 2 properties define 'cells' for representing an address and a
713 size. A "cell" is a 32-bit number. For example, if both contain 2
714 like the example tree given above, then an address and a size are both
715 composed of 2 cells, and each is a 64-bit number (cells are
716 concatenated and expected to be in big endian format). Another example
717 is the way Apple firmware defines them, with 2 cells for an address
718 and one cell for a size. Most 32-bit implementations should define
719 #address-cells and #size-cells to 1, which represents a 32-bit value.
720 Some 32-bit processors allow for physical addresses greater than 32
721 bits; these processors should define #address-cells as 2.
723 "reg" properties are always a tuple of the type "address size" where
724 the number of cells of address and size is specified by the bus
725 #address-cells and #size-cells. When a bus supports various address
726 spaces and other flags relative to a given address allocation (like
727 prefetchable, etc...) those flags are usually added to the top level
728 bits of the physical address. For example, a PCI physical address is
729 made of 3 cells, the bottom two containing the actual address itself
730 while the top cell contains address space indication, flags, and pci
731 bus & device numbers.
733 For busses that support dynamic allocation, it's the accepted practice
734 to then not provide the address in "reg" (keep it 0) though while
735 providing a flag indicating the address is dynamically allocated, and
736 then, to provide a separate "assigned-addresses" property that
737 contains the fully allocated addresses. See the PCI OF bindings for
740 In general, a simple bus with no address space bits and no dynamic
741 allocation is preferred if it reflects your hardware, as the existing
742 kernel address parsing functions will work out of the box. If you
743 define a bus type with a more complex address format, including things
744 like address space bits, you'll have to add a bus translator to the
745 prom_parse.c file of the recent kernels for your bus type.
747 The "reg" property only defines addresses and sizes (if #size-cells is
748 non-0) within a given bus. In order to translate addresses upward
749 (that is into parent bus addresses, and possibly into CPU physical
750 addresses), all busses must contain a "ranges" property. If the
751 "ranges" property is missing at a given level, it's assumed that
752 translation isn't possible, i.e., the registers are not visible on the
753 parent bus. The format of the "ranges" property for a bus is a list
756 bus address, parent bus address, size
758 "bus address" is in the format of the bus this bus node is defining,
759 that is, for a PCI bridge, it would be a PCI address. Thus, (bus
760 address, size) defines a range of addresses for child devices. "parent
761 bus address" is in the format of the parent bus of this bus. For
762 example, for a PCI host controller, that would be a CPU address. For a
763 PCI<->ISA bridge, that would be a PCI address. It defines the base
764 address in the parent bus where the beginning of that range is mapped.
766 For a new 64-bit powerpc board, I recommend either the 2/2 format or
767 Apple's 2/1 format which is slightly more compact since sizes usually
768 fit in a single 32-bit word. New 32-bit powerpc boards should use a
769 1/1 format, unless the processor supports physical addresses greater
770 than 32-bits, in which case a 2/1 format is recommended.
772 Alternatively, the "ranges" property may be empty, indicating that the
773 registers are visible on the parent bus using an identity mapping
774 translation. In other words, the parent bus address space is the same
775 as the child bus address space.
777 2) Note about "compatible" properties
778 -------------------------------------
780 These properties are optional, but recommended in devices and the root
781 node. The format of a "compatible" property is a list of concatenated
782 zero terminated strings. They allow a device to express its
783 compatibility with a family of similar devices, in some cases,
784 allowing a single driver to match against several devices regardless
785 of their actual names.
787 3) Note about "name" properties
788 -------------------------------
790 While earlier users of Open Firmware like OldWorld macintoshes tended
791 to use the actual device name for the "name" property, it's nowadays
792 considered a good practice to use a name that is closer to the device
793 class (often equal to device_type). For example, nowadays, ethernet
794 controllers are named "ethernet", an additional "model" property
795 defining precisely the chip type/model, and "compatible" property
796 defining the family in case a single driver can driver more than one
797 of these chips. However, the kernel doesn't generally put any
798 restriction on the "name" property; it is simply considered good
799 practice to follow the standard and its evolutions as closely as
802 Note also that the new format version 16 makes the "name" property
803 optional. If it's absent for a node, then the node's unit name is then
804 used to reconstruct the name. That is, the part of the unit name
805 before the "@" sign is used (or the entire unit name if no "@" sign
808 4) Note about node and property names and character set
809 -------------------------------------------------------
811 While open firmware provides more flexible usage of 8859-1, this
812 specification enforces more strict rules. Nodes and properties should
813 be comprised only of ASCII characters 'a' to 'z', '0' to
814 '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
815 allow uppercase characters 'A' to 'Z' (property names should be
816 lowercase. The fact that vendors like Apple don't respect this rule is
817 irrelevant here). Additionally, node and property names should always
818 begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
821 The maximum number of characters for both nodes and property names
822 is 31. In the case of node names, this is only the leftmost part of
823 a unit name (the pure "name" property), it doesn't include the unit
824 address which can extend beyond that limit.
827 5) Required nodes and properties
828 --------------------------------
829 These are all that are currently required. However, it is strongly
830 recommended that you expose PCI host bridges as documented in the
831 PCI binding to open firmware, and your interrupt tree as documented
832 in OF interrupt tree specification.
836 The root node requires some properties to be present:
838 - model : this is your board name/model
839 - #address-cells : address representation for "root" devices
840 - #size-cells: the size representation for "root" devices
841 - device_type : This property shouldn't be necessary. However, if
842 you decide to create a device_type for your root node, make sure it
843 is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
844 one for 64-bit, or a CHRP-type machine for 32-bit as this will
845 matched by the kernel this way.
847 Additionally, some recommended properties are:
849 - compatible : the board "family" generally finds its way here,
850 for example, if you have 2 board models with a similar layout,
851 that typically get driven by the same platform code in the
852 kernel, you would use a different "model" property but put a
853 value in "compatible". The kernel doesn't directly use that
854 value but it is generally useful.
856 The root node is also generally where you add additional properties
857 specific to your board like the serial number if any, that sort of
858 thing. It is recommended that if you add any "custom" property whose
859 name may clash with standard defined ones, you prefix them with your
860 vendor name and a comma.
864 This node is the parent of all individual CPU nodes. It doesn't
865 have any specific requirements, though it's generally good practice
868 #address-cells = <00000001>
869 #size-cells = <00000000>
871 This defines that the "address" for a CPU is a single cell, and has
872 no meaningful size. This is not necessary but the kernel will assume
873 that format when reading the "reg" properties of a CPU node, see
878 So under /cpus, you are supposed to create a node for every CPU on
879 the machine. There is no specific restriction on the name of the
880 CPU, though It's common practice to call it PowerPC,<name>. For
881 example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
885 - device_type : has to be "cpu"
886 - reg : This is the physical CPU number, it's a single 32-bit cell
887 and is also used as-is as the unit number for constructing the
888 unit name in the full path. For example, with 2 CPUs, you would
890 /cpus/PowerPC,970FX@0
891 /cpus/PowerPC,970FX@1
892 (unit addresses do not require leading zeroes)
893 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
894 - i-cache-block-size : one cell, L1 instruction cache block size in
896 - d-cache-size : one cell, size of L1 data cache in bytes
897 - i-cache-size : one cell, size of L1 instruction cache in bytes
899 (*) The cache "block" size is the size on which the cache management
900 instructions operate. Historically, this document used the cache
901 "line" size here which is incorrect. The kernel will prefer the cache
902 block size and will fallback to cache line size for backward
905 Recommended properties:
907 - timebase-frequency : a cell indicating the frequency of the
908 timebase in Hz. This is not directly used by the generic code,
909 but you are welcome to copy/paste the pSeries code for setting
910 the kernel timebase/decrementer calibration based on this
912 - clock-frequency : a cell indicating the CPU core clock frequency
913 in Hz. A new property will be defined for 64-bit values, but if
914 your frequency is < 4Ghz, one cell is enough. Here as well as
915 for the above, the common code doesn't use that property, but
916 you are welcome to re-use the pSeries or Maple one. A future
917 kernel version might provide a common function for this.
918 - d-cache-line-size : one cell, L1 data cache line size in bytes
919 if different from the block size
920 - i-cache-line-size : one cell, L1 instruction cache line size in
921 bytes if different from the block size
923 You are welcome to add any property you find relevant to your board,
924 like some information about the mechanism used to soft-reset the
925 CPUs. For example, Apple puts the GPIO number for CPU soft reset
926 lines in there as a "soft-reset" property since they start secondary
927 CPUs by soft-resetting them.
930 d) the /memory node(s)
932 To define the physical memory layout of your board, you should
933 create one or more memory node(s). You can either create a single
934 node with all memory ranges in its reg property, or you can create
935 several nodes, as you wish. The unit address (@ part) used for the
936 full path is the address of the first range of memory defined by a
937 given node. If you use a single memory node, this will typically be
942 - device_type : has to be "memory"
943 - reg : This property contains all the physical memory ranges of
944 your board. It's a list of addresses/sizes concatenated
945 together, with the number of cells of each defined by the
946 #address-cells and #size-cells of the root node. For example,
947 with both of these properties being 2 like in the example given
948 earlier, a 970 based machine with 6Gb of RAM could typically
949 have a "reg" property here that looks like:
951 00000000 00000000 00000000 80000000
952 00000001 00000000 00000001 00000000
954 That is a range starting at 0 of 0x80000000 bytes and a range
955 starting at 0x100000000 and of 0x100000000 bytes. You can see
956 that there is no memory covering the IO hole between 2Gb and
957 4Gb. Some vendors prefer splitting those ranges into smaller
958 segments, but the kernel doesn't care.
962 This node is a bit "special". Normally, that's where open firmware
963 puts some variable environment information, like the arguments, or
964 the default input/output devices.
966 This specification makes a few of these mandatory, but also defines
967 some linux-specific properties that would be normally constructed by
968 the prom_init() trampoline when booting with an OF client interface,
969 but that you have to provide yourself when using the flattened format.
971 Recommended properties:
973 - bootargs : This zero-terminated string is passed as the kernel
975 - linux,stdout-path : This is the full path to your standard
976 console device if any. Typically, if you have serial devices on
977 your board, you may want to put the full path to the one set as
978 the default console in the firmware here, for the kernel to pick
979 it up as its own default console. If you look at the function
980 set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
981 that the kernel tries to find out the default console and has
982 knowledge of various types like 8250 serial ports. You may want
983 to extend this function to add your own.
985 Note that u-boot creates and fills in the chosen node for platforms
988 (Note: a practice that is now obsolete was to include a property
989 under /chosen called interrupt-controller which had a phandle value
990 that pointed to the main interrupt controller)
992 f) the /soc<SOCname> node
994 This node is used to represent a system-on-a-chip (SOC) and must be
995 present if the processor is a SOC. The top-level soc node contains
996 information that is global to all devices on the SOC. The node name
997 should contain a unit address for the SOC, which is the base address
998 of the memory-mapped register set for the SOC. The name of an soc
999 node should start with "soc", and the remainder of the name should
1000 represent the part number for the soc. For example, the MPC8540's
1001 soc node would be called "soc8540".
1003 Required properties:
1005 - device_type : Should be "soc"
1006 - ranges : Should be defined as specified in 1) to describe the
1007 translation of SOC addresses for memory mapped SOC registers.
1008 - bus-frequency: Contains the bus frequency for the SOC node.
1009 Typically, the value of this field is filled in by the boot
1013 Recommended properties:
1015 - reg : This property defines the address and size of the
1016 memory-mapped registers that are used for the SOC node itself.
1017 It does not include the child device registers - these will be
1018 defined inside each child node. The address specified in the
1019 "reg" property should match the unit address of the SOC node.
1020 - #address-cells : Address representation for "soc" devices. The
1021 format of this field may vary depending on whether or not the
1022 device registers are memory mapped. For memory mapped
1023 registers, this field represents the number of cells needed to
1024 represent the address of the registers. For SOCs that do not
1025 use MMIO, a special address format should be defined that
1026 contains enough cells to represent the required information.
1027 See 1) above for more details on defining #address-cells.
1028 - #size-cells : Size representation for "soc" devices
1029 - #interrupt-cells : Defines the width of cells used to represent
1030 interrupts. Typically this value is <2>, which includes a
1031 32-bit number that represents the interrupt number, and a
1032 32-bit number that represents the interrupt sense and level.
1033 This field is only needed if the SOC contains an interrupt
1036 The SOC node may contain child nodes for each SOC device that the
1037 platform uses. Nodes should not be created for devices which exist
1038 on the SOC but are not used by a particular platform. See chapter VI
1039 for more information on how to specify devices that are part of a SOC.
1041 Example SOC node for the MPC8540:
1044 #address-cells = <1>;
1046 #interrupt-cells = <2>;
1047 device_type = "soc";
1048 ranges = <00000000 e0000000 00100000>
1049 reg = <e0000000 00003000>;
1050 bus-frequency = <0>;
1055 IV - "dtc", the device tree compiler
1056 ====================================
1059 dtc source code can be found at
1060 <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
1062 WARNING: This version is still in early development stage; the
1063 resulting device-tree "blobs" have not yet been validated with the
1064 kernel. The current generated bloc lacks a useful reserve map (it will
1065 be fixed to generate an empty one, it's up to the bootloader to fill
1066 it up) among others. The error handling needs work, bugs are lurking,
1069 dtc basically takes a device-tree in a given format and outputs a
1070 device-tree in another format. The currently supported formats are:
1075 - "dtb": "blob" format, that is a flattened device-tree block
1077 header all in a binary blob.
1078 - "dts": "source" format. This is a text file containing a
1079 "source" for a device-tree. The format is defined later in this
1081 - "fs" format. This is a representation equivalent to the
1082 output of /proc/device-tree, that is nodes are directories and
1083 properties are files
1088 - "dtb": "blob" format
1089 - "dts": "source" format
1090 - "asm": assembly language file. This is a file that can be
1091 sourced by gas to generate a device-tree "blob". That file can
1092 then simply be added to your Makefile. Additionally, the
1093 assembly file exports some symbols that can be used.
1096 The syntax of the dtc tool is
1098 dtc [-I <input-format>] [-O <output-format>]
1099 [-o output-filename] [-V output_version] input_filename
1102 The "output_version" defines what version of the "blob" format will be
1103 generated. Supported versions are 1,2,3 and 16. The default is
1104 currently version 3 but that may change in the future to version 16.
1106 Additionally, dtc performs various sanity checks on the tree, like the
1107 uniqueness of linux, phandle properties, validity of strings, etc...
1109 The format of the .dts "source" file is "C" like, supports C and C++
1115 The above is the "device-tree" definition. It's the only statement
1116 supported currently at the toplevel.
1119 property1 = "string_value"; /* define a property containing a 0
1123 property2 = <1234abcd>; /* define a property containing a
1124 * numerical 32-bit value (hexadecimal)
1127 property3 = <12345678 12345678 deadbeef>;
1128 /* define a property containing 3
1129 * numerical 32-bit values (cells) in
1132 property4 = [0a 0b 0c 0d de ea ad be ef];
1133 /* define a property whose content is
1134 * an arbitrary array of bytes
1137 childnode@addresss { /* define a child node named "childnode"
1138 * whose unit name is "childnode at
1142 childprop = "hello\n"; /* define a property "childprop" of
1143 * childnode (in this case, a string)
1148 Nodes can contain other nodes etc... thus defining the hierarchical
1149 structure of the tree.
1151 Strings support common escape sequences from C: "\n", "\t", "\r",
1152 "\(octal value)", "\x(hex value)".
1154 It is also suggested that you pipe your source file through cpp (gcc
1155 preprocessor) so you can use #include's, #define for constants, etc...
1157 Finally, various options are planned but not yet implemented, like
1158 automatic generation of phandles, labels (exported to the asm file so
1159 you can point to a property content and change it easily from whatever
1160 you link the device-tree with), label or path instead of numeric value
1161 in some cells to "point" to a node (replaced by a phandle at compile
1162 time), export of reserve map address to the asm file, ability to
1163 specify reserve map content at compile time, etc...
1165 We may provide a .h include file with common definitions of that
1166 proves useful for some properties (like building PCI properties or
1167 interrupt maps) though it may be better to add a notion of struct
1168 definitions to the compiler...
1171 V - Recommendations for a bootloader
1172 ====================================
1175 Here are some various ideas/recommendations that have been proposed
1176 while all this has been defined and implemented.
1178 - The bootloader may want to be able to use the device-tree itself
1179 and may want to manipulate it (to add/edit some properties,
1180 like physical memory size or kernel arguments). At this point, 2
1181 choices can be made. Either the bootloader works directly on the
1182 flattened format, or the bootloader has its own internal tree
1183 representation with pointers (similar to the kernel one) and
1184 re-flattens the tree when booting the kernel. The former is a bit
1185 more difficult to edit/modify, the later requires probably a bit
1186 more code to handle the tree structure. Note that the structure
1187 format has been designed so it's relatively easy to "insert"
1188 properties or nodes or delete them by just memmoving things
1189 around. It contains no internal offsets or pointers for this
1192 - An example of code for iterating nodes & retrieving properties
1193 directly from the flattened tree format can be found in the kernel
1194 file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
1195 its usage in early_init_devtree(), and the corresponding various
1196 early_init_dt_scan_*() callbacks. That code can be re-used in a
1197 GPL bootloader, and as the author of that code, I would be happy
1198 to discuss possible free licensing to any vendor who wishes to
1199 integrate all or part of this code into a non-GPL bootloader.
1203 VI - System-on-a-chip devices and nodes
1204 =======================================
1206 Many companies are now starting to develop system-on-a-chip
1207 processors, where the processor core (CPU) and many peripheral devices
1208 exist on a single piece of silicon. For these SOCs, an SOC node
1209 should be used that defines child nodes for the devices that make
1210 up the SOC. While platforms are not required to use this model in
1211 order to boot the kernel, it is highly encouraged that all SOC
1212 implementations define as complete a flat-device-tree as possible to
1213 describe the devices on the SOC. This will allow for the
1214 genericization of much of the kernel code.
1217 1) Defining child nodes of an SOC
1218 ---------------------------------
1220 Each device that is part of an SOC may have its own node entry inside
1221 the SOC node. For each device that is included in the SOC, the unit
1222 address property represents the address offset for this device's
1223 memory-mapped registers in the parent's address space. The parent's
1224 address space is defined by the "ranges" property in the top-level soc
1225 node. The "reg" property for each node that exists directly under the
1226 SOC node should contain the address mapping from the child address space
1227 to the parent SOC address space and the size of the device's
1228 memory-mapped register file.
1230 For many devices that may exist inside an SOC, there are predefined
1231 specifications for the format of the device tree node. All SOC child
1232 nodes should follow these specifications, except where noted in this
1235 See appendix A for an example partial SOC node definition for the
1239 2) Representing devices without a current OF specification
1240 ----------------------------------------------------------
1242 Currently, there are many devices on SOCs that do not have a standard
1243 representation pre-defined as part of the open firmware
1244 specifications, mainly because the boards that contain these SOCs are
1245 not currently booted using open firmware. This section contains
1246 descriptions for the SOC devices for which new nodes have been
1247 defined; this list will expand as more and more SOC-containing
1248 platforms are moved over to use the flattened-device-tree model.
1252 Required properties:
1254 - device_type : Should be "ethernet-phy"
1255 - interrupts : <a b> where a is the interrupt number and b is a
1256 field that represents an encoding of the sense and level
1257 information for the interrupt. This should be encoded based on
1258 the information in section 2) depending on the type of interrupt
1259 controller you have.
1260 - interrupt-parent : the phandle for the interrupt controller that
1261 services interrupts for this device.
1262 - reg : The ID number for the phy, usually a small integer
1263 - linux,phandle : phandle for this node; likely referenced by an
1264 ethernet controller node.
1270 linux,phandle = <2452000>
1271 interrupt-parent = <40000>;
1272 interrupts = <35 1>;
1274 device_type = "ethernet-phy";
1278 b) Interrupt controllers
1280 Some SOC devices contain interrupt controllers that are different
1281 from the standard Open PIC specification. The SOC device nodes for
1282 these types of controllers should be specified just like a standard
1283 OpenPIC controller. Sense and level information should be encoded
1284 as specified in section 2) of this chapter for each device that
1285 specifies an interrupt.
1290 linux,phandle = <40000>;
1291 interrupt-controller;
1292 #address-cells = <0>;
1293 reg = <40000 40000>;
1294 compatible = "chrp,open-pic";
1295 device_type = "open-pic";
1298 c) CFI or JEDEC memory-mapped NOR flash
1300 Flash chips (Memory Technology Devices) are often used for solid state
1301 file systems on embedded devices.
1303 - compatible : should contain the specific model of flash chip(s)
1304 used, if known, followed by either "cfi-flash" or "jedec-flash"
1305 - reg : Address range of the flash chip
1306 - bank-width : Width (in bytes) of the flash bank. Equal to the
1307 device width times the number of interleaved chips.
1308 - device-width : (optional) Width of a single flash chip. If
1309 omitted, assumed to be equal to 'bank-width'.
1310 - #address-cells, #size-cells : Must be present if the flash has
1311 sub-nodes representing partitions (see below). In this case
1312 both #address-cells and #size-cells must be equal to 1.
1314 For JEDEC compatible devices, the following additional properties
1317 - vendor-id : Contains the flash chip's vendor id (1 byte).
1318 - device-id : Contains the flash chip's device id (1 byte).
1320 In addition to the information on the flash bank itself, the
1321 device tree may optionally contain additional information
1322 describing partitions of the flash address space. This can be
1323 used on platforms which have strong conventions about which
1324 portions of the flash are used for what purposes, but which don't
1325 use an on-flash partition table such as RedBoot.
1327 Each partition is represented as a sub-node of the flash device.
1328 Each node's name represents the name of the corresponding
1329 partition of the flash device.
1332 - reg : The partition's offset and size within the flash bank.
1333 - label : (optional) The label / name for this flash partition.
1334 If omitted, the label is taken from the node name (excluding
1336 - read-only : (optional) This parameter, if present, is a hint to
1337 Linux that this flash partition should only be mounted
1338 read-only. This is usually used for flash partitions
1339 containing early-boot firmware images or data which should not
1345 compatible = "amd,am29lv128ml", "cfi-flash";
1346 reg = <ff000000 01000000>;
1349 #address-cells = <1>;
1357 reg = <f80000 80000>;
1362 d) 4xx/Axon EMAC ethernet nodes
1364 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1365 the Axon bridge. To operate this needs to interact with a ths
1366 special McMAL DMA controller, and sometimes an RGMII or ZMII
1367 interface. In addition to the nodes and properties described
1368 below, the node for the OPB bus on which the EMAC sits must have a
1369 correct clock-frequency property.
1371 i) The EMAC node itself
1373 Required properties:
1374 - device_type : "network"
1376 - compatible : compatible list, contains 2 entries, first is
1377 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1378 405gp, Axon) and second is either "ibm,emac" or
1379 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1381 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1382 - interrupt-parent : optional, if needed for interrupt mapping
1383 - reg : <registers mapping>
1384 - local-mac-address : 6 bytes, MAC address
1385 - mal-device : phandle of the associated McMAL node
1386 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1388 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1390 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1391 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1393 - max-frame-size : 1 cell, maximum frame size supported in bytes
1394 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1397 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1400 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1402 For Axon, 0x00000010
1403 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1405 For Axon, 0x00000100 (I think ...)
1406 - phy-mode : string, mode of operations of the PHY interface.
1407 Supported values are: "mii", "rmii", "smii", "rgmii",
1408 "tbi", "gmii", rtbi", "sgmii".
1409 For Axon on CAB, it is "rgmii"
1410 - mdio-device : 1 cell, required iff using shared MDIO registers
1411 (440EP). phandle of the EMAC to use to drive the
1412 MDIO lines for the PHY used by this EMAC.
1413 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1414 the ZMII device node
1415 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1416 channel or 0xffffffff if ZMII is only used for MDIO.
1417 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1418 of the RGMII device node.
1419 For Axon: phandle of plb5/plb4/opb/rgmii
1420 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1421 RGMII channel is used by this EMAC.
1422 Fox Axon: present, whatever value is appropriate for each
1423 EMAC, that is the content of the current (bogus) "phy-port"
1426 Optional properties:
1427 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1428 a search is performed.
1429 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1430 for, used if phy-address is absent. bit 0x00000001 is
1432 For Axon it can be absent, thouugh my current driver
1433 doesn't handle phy-address yet so for now, keep
1435 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1436 operations (if absent the value is the same as
1437 rx-fifo-size). For Axon, either absent or 2048.
1438 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1439 operations (if absent the value is the same as
1440 tx-fifo-size). For Axon, either absent or 2048.
1441 - tah-device : 1 cell, optional. If connected to a TAH engine for
1442 offload, phandle of the TAH device node.
1443 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1448 EMAC0: ethernet@40000800 {
1449 device_type = "network";
1450 compatible = "ibm,emac-440gp", "ibm,emac";
1451 interrupt-parent = <&UIC1>;
1452 interrupts = <1c 4 1d 4>;
1453 reg = <40000800 70>;
1454 local-mac-address = [00 04 AC E3 1B 1E];
1455 mal-device = <&MAL0>;
1456 mal-tx-channel = <0 1>;
1457 mal-rx-channel = <0>;
1459 max-frame-size = <5dc>;
1460 rx-fifo-size = <1000>;
1461 tx-fifo-size = <800>;
1463 phy-map = <00000001>;
1464 zmii-device = <&ZMII0>;
1470 Required properties:
1471 - device_type : "dma-controller"
1472 - compatible : compatible list, containing 2 entries, first is
1473 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1474 emac) and the second is either "ibm,mcmal" or
1476 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1477 - interrupts : <interrupt mapping for the MAL interrupts sources:
1478 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1479 For Axon: This is _different_ from the current
1480 firmware. We use the "delayed" interrupts for txeob
1481 and rxeob. Thus we end up with mapping those 5 MPIC
1482 interrupts, all level positive sensitive: 10, 11, 32,
1484 - dcr-reg : < DCR registers range >
1485 - dcr-parent : if needed for dcr-reg
1486 - num-tx-chans : 1 cell, number of Tx channels
1487 - num-rx-chans : 1 cell, number of Rx channels
1491 Required properties:
1492 - compatible : compatible list, containing 2 entries, first is
1493 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1494 EMAC) and the second is "ibm,zmii".
1495 For Axon, there is no ZMII node.
1496 - reg : <registers mapping>
1500 Required properties:
1501 - compatible : compatible list, containing 2 entries, first is
1502 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1503 EMAC) and the second is "ibm,rgmii".
1504 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1505 - reg : <registers mapping>
1506 - revision : as provided by the RGMII new version register if
1508 For Axon: 0x0000012a
1512 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
1513 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
1514 of standard device types (network, serial, etc.) and miscellanious
1515 devices (gpio, LCD, spi, etc). Also, since these devices are
1516 implemented within the fpga fabric every instance of the device can be
1517 synthesised with different options that change the behaviour.
1519 Each IP-core has a set of parameters which the FPGA designer can use to
1520 control how the core is synthesized. Historically, the EDK tool would
1521 extract the device parameters relevant to device drivers and copy them
1522 into an 'xparameters.h' in the form of #define symbols. This tells the
1523 device drivers how the IP cores are configured, but it requres the kernel
1524 to be recompiled every time the FPGA bitstream is resynthesized.
1526 The new approach is to export the parameters into the device tree and
1527 generate a new device tree each time the FPGA bitstream changes. The
1528 parameters which used to be exported as #defines will now become
1529 properties of the device node. In general, device nodes for IP-cores
1530 will take the following form:
1532 (name): (generic-name)@(base-address) {
1533 compatible = "xlnx,(ip-core-name)-(HW_VER)"
1534 [, (list of compatible devices), ...];
1535 reg = <(baseaddr) (size)>;
1536 interrupt-parent = <&interrupt-controller-phandle>;
1537 interrupts = < ... >;
1538 xlnx,(parameter1) = "(string-value)";
1539 xlnx,(parameter2) = <(int-value)>;
1542 (generic-name): an open firmware-style name that describes the
1543 generic class of device. Preferably, this is one word, such
1544 as 'serial' or 'ethernet'.
1545 (ip-core-name): the name of the ip block (given after the BEGIN
1546 directive in system.mhs). Should be in lowercase
1547 and all underscores '_' converted to dashes '-'.
1548 (name): is derived from the "PARAMETER INSTANCE" value.
1549 (parameter#): C_* parameters from system.mhs. The C_ prefix is
1550 dropped from the parameter name, the name is converted
1551 to lowercase and all underscore '_' characters are
1552 converted to dashes '-'.
1553 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
1554 (HW_VER): from the HW_VER parameter.
1555 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
1557 Typically, the compatible list will include the exact IP core version
1558 followed by an older IP core version which implements the same
1559 interface or any other device with the same interface.
1561 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
1563 For example, the following block from system.mhs:
1566 PARAMETER INSTANCE = opb_uartlite_0
1567 PARAMETER HW_VER = 1.00.b
1568 PARAMETER C_BAUDRATE = 115200
1569 PARAMETER C_DATA_BITS = 8
1570 PARAMETER C_ODD_PARITY = 0
1571 PARAMETER C_USE_PARITY = 0
1572 PARAMETER C_CLK_FREQ = 50000000
1573 PARAMETER C_BASEADDR = 0xEC100000
1574 PARAMETER C_HIGHADDR = 0xEC10FFFF
1575 BUS_INTERFACE SOPB = opb_7
1576 PORT OPB_Clk = CLK_50MHz
1577 PORT Interrupt = opb_uartlite_0_Interrupt
1578 PORT RX = opb_uartlite_0_RX
1579 PORT TX = opb_uartlite_0_TX
1580 PORT OPB_Rst = sys_bus_reset_0
1583 becomes the following device tree node:
1585 opb_uartlite_0: serial@ec100000 {
1586 device_type = "serial";
1587 compatible = "xlnx,opb-uartlite-1.00.b";
1588 reg = <ec100000 10000>;
1589 interrupt-parent = <&opb_intc_0>;
1590 interrupts = <1 0>; // got this from the opb_intc parameters
1591 current-speed = <d#115200>; // standard serial device prop
1592 clock-frequency = <d#50000000>; // standard serial device prop
1593 xlnx,data-bits = <8>;
1594 xlnx,odd-parity = <0>;
1595 xlnx,use-parity = <0>;
1598 Some IP cores actually implement 2 or more logical devices. In
1599 this case, the device should still describe the whole IP core with
1600 a single node and add a child node for each logical device. The
1601 ranges property can be used to translate from parent IP-core to the
1602 registers of each device. In addition, the parent node should be
1603 compatible with the bus type 'xlnx,compound', and should contain
1604 #address-cells and #size-cells, as with any other bus. (Note: this
1605 makes the assumption that both logical devices have the same bus
1606 binding. If this is not true, then separate nodes should be used
1607 for each logical device). The 'cell-index' property can be used to
1608 enumerate logical devices within an IP core. For example, the
1609 following is the system.mhs entry for the dual ps2 controller found
1610 on the ml403 reference design.
1612 BEGIN opb_ps2_dual_ref
1613 PARAMETER INSTANCE = opb_ps2_dual_ref_0
1614 PARAMETER HW_VER = 1.00.a
1615 PARAMETER C_BASEADDR = 0xA9000000
1616 PARAMETER C_HIGHADDR = 0xA9001FFF
1617 BUS_INTERFACE SOPB = opb_v20_0
1618 PORT Sys_Intr1 = ps2_1_intr
1619 PORT Sys_Intr2 = ps2_2_intr
1620 PORT Clkin1 = ps2_clk_rx_1
1621 PORT Clkin2 = ps2_clk_rx_2
1622 PORT Clkpd1 = ps2_clk_tx_1
1623 PORT Clkpd2 = ps2_clk_tx_2
1624 PORT Rx1 = ps2_d_rx_1
1625 PORT Rx2 = ps2_d_rx_2
1626 PORT Txpd1 = ps2_d_tx_1
1627 PORT Txpd2 = ps2_d_tx_2
1630 It would result in the following device tree nodes:
1632 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
1633 #address-cells = <1>;
1635 compatible = "xlnx,compound";
1636 ranges = <0 a9000000 2000>;
1637 // If this device had extra parameters, then they would
1640 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1642 interrupt-parent = <&opb_intc_0>;
1647 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1649 interrupt-parent = <&opb_intc_0>;
1655 Also, the system.mhs file defines bus attachments from the processor
1656 to the devices. The device tree structure should reflect the bus
1657 attachments. Again an example; this system.mhs fragment:
1659 BEGIN ppc405_virtex4
1660 PARAMETER INSTANCE = ppc405_0
1661 PARAMETER HW_VER = 1.01.a
1662 BUS_INTERFACE DPLB = plb_v34_0
1663 BUS_INTERFACE IPLB = plb_v34_0
1667 PARAMETER INSTANCE = opb_intc_0
1668 PARAMETER HW_VER = 1.00.c
1669 PARAMETER C_BASEADDR = 0xD1000FC0
1670 PARAMETER C_HIGHADDR = 0xD1000FDF
1671 BUS_INTERFACE SOPB = opb_v20_0
1675 PARAMETER INSTANCE = opb_uart16550_0
1676 PARAMETER HW_VER = 1.00.d
1677 PARAMETER C_BASEADDR = 0xa0000000
1678 PARAMETER C_HIGHADDR = 0xa0001FFF
1679 BUS_INTERFACE SOPB = opb_v20_0
1683 PARAMETER INSTANCE = plb_v34_0
1684 PARAMETER HW_VER = 1.02.a
1687 BEGIN plb_bram_if_cntlr
1688 PARAMETER INSTANCE = plb_bram_if_cntlr_0
1689 PARAMETER HW_VER = 1.00.b
1690 PARAMETER C_BASEADDR = 0xFFFF0000
1691 PARAMETER C_HIGHADDR = 0xFFFFFFFF
1692 BUS_INTERFACE SPLB = plb_v34_0
1695 BEGIN plb2opb_bridge
1696 PARAMETER INSTANCE = plb2opb_bridge_0
1697 PARAMETER HW_VER = 1.01.a
1698 PARAMETER C_RNG0_BASEADDR = 0x20000000
1699 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
1700 PARAMETER C_RNG1_BASEADDR = 0x60000000
1701 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
1702 PARAMETER C_RNG2_BASEADDR = 0x80000000
1703 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
1704 PARAMETER C_RNG3_BASEADDR = 0xC0000000
1705 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
1706 BUS_INTERFACE SPLB = plb_v34_0
1707 BUS_INTERFACE MOPB = opb_v20_0
1710 Gives this device tree (some properties removed for clarity):
1713 #address-cells = <1>;
1715 compatible = "xlnx,plb-v34-1.02.a";
1716 device_type = "ibm,plb";
1717 ranges; // 1:1 translation
1719 plb_bram_if_cntrl_0: bram@ffff0000 {
1720 reg = <ffff0000 10000>;
1724 #address-cells = <1>;
1726 ranges = <20000000 20000000 20000000
1727 60000000 60000000 20000000
1728 80000000 80000000 40000000
1729 c0000000 c0000000 20000000>;
1731 opb_uart16550_0: serial@a0000000 {
1732 reg = <a00000000 2000>;
1735 opb_intc_0: interrupt-controller@d1000fc0 {
1736 reg = <d1000fc0 20>;
1741 That covers the general approach to binding xilinx IP cores into the
1742 device tree. The following are bindings for specific devices:
1744 i) Xilinx ML300 Framebuffer
1746 Simple framebuffer device from the ML300 reference design (also on the
1747 ML403 reference design as well as others).
1749 Optional properties:
1750 - resolution = <xres yres> : pixel resolution of framebuffer. Some
1751 implementations use a different resolution.
1752 Default is <d#640 d#480>
1753 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
1754 Default is <d#1024 d#480>.
1755 - rotate-display (empty) : rotate display 180 degrees.
1757 ii) Xilinx SystemACE
1759 The Xilinx SystemACE device is used to program FPGAs from an FPGA
1760 bitstream stored on a CF card. It can also be used as a generic CF
1763 Optional properties:
1764 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
1766 iii) Xilinx EMAC and Xilinx TEMAC
1768 Xilinx Ethernet devices. In addition to general xilinx properties
1769 listed above, nodes for these devices should include a phy-handle
1770 property, and may include other common network device properties
1771 like local-mac-address.
1775 Xilinx uartlite devices are simple fixed speed serial ports.
1778 - current-speed : Baud rate of uartlite
1782 Xilinx hwicap devices provide access to the configuration logic
1783 of the FPGA through the Internal Configuration Access Port
1784 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
1785 readback of the configuration information, and some control over
1786 'warm boots' of the FPGA fabric.
1788 Required properties:
1789 - xlnx,family : The family of the FPGA, necessary since the
1790 capabilities of the underlying ICAP hardware
1791 differ between different families. May be
1792 'virtex2p', 'virtex4', or 'virtex5'.
1794 vi) Xilinx Uart 16550
1796 Xilinx UART 16550 devices are very similar to the NS16550 but with
1797 different register spacing and an offset from the base address.
1800 - clock-frequency : Frequency of the clock input
1801 - reg-offset : A value of 3 is required
1802 - reg-shift : A value of 2 is required
1804 f) USB EHCI controllers
1806 Required properties:
1807 - compatible : should be "usb-ehci".
1808 - reg : should contain at least address and length of the standard EHCI
1809 register set for the device. Optional platform-dependent registers
1810 (debug-port or other) can be also specified here, but only after
1811 definition of standard EHCI registers.
1812 - interrupts : one EHCI interrupt should be described here.
1813 If device registers are implemented in big endian mode, the device
1814 node should have "big-endian-regs" property.
1815 If controller implementation operates with big endian descriptors,
1816 "big-endian-desc" property should be specified.
1817 If both big endian registers and descriptors are used by the controller
1818 implementation, "big-endian" property can be specified instead of having
1819 both "big-endian-regs" and "big-endian-desc".
1821 Example (Sequoia 440EPx):
1823 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
1824 interrupt-parent = <&UIC0>;
1825 interrupts = <1a 4>;
1826 reg = <0 e0000300 90 0 e0000390 70>;
1830 r) Freescale Display Interface Unit
1832 The Freescale DIU is a LCD controller, with proper hardware, it can also
1835 Required properties:
1836 - compatible : should be "fsl-diu".
1837 - reg : should contain at least address and length of the DIU register
1839 - Interrupts : one DIU interrupt should be describe here.
1841 Example (MPC8610HPCD)
1843 compatible = "fsl,diu";
1844 reg = <0x2c000 100>;
1845 interrupts = <72 2>;
1846 interrupt-parent = <&mpic>;
1849 s) Freescale on board FPGA
1851 This is the memory-mapped registers for on board FPGA.
1853 Required properities:
1854 - compatible : should be "fsl,fpga-pixis".
1855 - reg : should contain the address and the lenght of the FPPGA register
1858 Example (MPC8610HPCD)
1859 board-control@e8000000 {
1860 compatible = "fsl,fpga-pixis";
1861 reg = <0xe8000000 32>;
1866 Currently defined compatibles:
1869 MDC and MDIO lines connected to GPIO controllers are listed in the
1870 gpios property as described in section VIII.1 in the following order:
1877 compatible = "virtual,mdio-gpio";
1878 #address-cells = <1>;
1880 gpios = <&qe_pio_a 11
1884 VII - Marvell Discovery mv64[345]6x System Controller chips
1885 ===========================================================
1887 The Marvell mv64[345]60 series of system controller chips contain
1888 many of the peripherals needed to implement a complete computer
1889 system. In this section, we define device tree nodes to describe
1890 the system controller chip itself and each of the peripherals
1891 which it contains. Compatible string values for each node are
1892 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
1894 1) The /system-controller node
1896 This node is used to represent the system-controller and must be
1897 present when the system uses a system contller chip. The top-level
1898 system-controller node contains information that is global to all
1899 devices within the system controller chip. The node name begins
1900 with "system-controller" followed by the unit address, which is
1901 the base address of the memory-mapped register set for the system
1904 Required properties:
1906 - ranges : Describes the translation of system controller addresses
1907 for memory mapped registers.
1908 - clock-frequency: Contains the main clock frequency for the system
1910 - reg : This property defines the address and size of the
1911 memory-mapped registers contained within the system controller
1912 chip. The address specified in the "reg" property should match
1913 the unit address of the system-controller node.
1914 - #address-cells : Address representation for system controller
1915 devices. This field represents the number of cells needed to
1916 represent the address of the memory-mapped registers of devices
1917 within the system controller chip.
1918 - #size-cells : Size representation for for the memory-mapped
1919 registers within the system controller chip.
1920 - #interrupt-cells : Defines the width of cells used to represent
1923 Optional properties:
1925 - model : The specific model of the system controller chip. Such
1926 as, "mv64360", "mv64460", or "mv64560".
1927 - compatible : A string identifying the compatibility identifiers
1928 of the system controller chip.
1930 The system-controller node contains child nodes for each system
1931 controller device that the platform uses. Nodes should not be created
1932 for devices which exist on the system controller chip but are not used
1934 Example Marvell Discovery mv64360 system-controller node:
1936 system-controller@f1000000 { /* Marvell Discovery mv64360 */
1937 #address-cells = <1>;
1939 model = "mv64360"; /* Default */
1940 compatible = "marvell,mv64360";
1941 clock-frequency = <133333333>;
1942 reg = <0xf1000000 0x10000>;
1943 virtual-reg = <0xf1000000>;
1944 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
1945 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
1946 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
1947 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
1948 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
1950 [ child node definitions... ]
1953 2) Child nodes of /system-controller
1955 a) Marvell Discovery MDIO bus
1957 The MDIO is a bus to which the PHY devices are connected. For each
1958 device that exists on this bus, a child node should be created. See
1959 the definition of the PHY node below for an example of how to define
1962 Required properties:
1963 - #address-cells : Should be <1>
1964 - #size-cells : Should be <0>
1965 - device_type : Should be "mdio"
1966 - compatible : Should be "marvell,mv64360-mdio"
1971 #address-cells = <1>;
1973 device_type = "mdio";
1974 compatible = "marvell,mv64360-mdio";
1982 b) Marvell Discovery ethernet controller
1984 The Discover ethernet controller is described with two levels
1985 of nodes. The first level describes an ethernet silicon block
1986 and the second level describes up to 3 ethernet nodes within
1987 that block. The reason for the multiple levels is that the
1988 registers for the node are interleaved within a single set
1989 of registers. The "ethernet-block" level describes the
1990 shared register set, and the "ethernet" nodes describe ethernet
1991 port-specific properties.
1995 Required properties:
1996 - #address-cells : <1>
1998 - compatible : "marvell,mv64360-eth-block"
1999 - reg : Offset and length of the register set for this block
2001 Example Discovery Ethernet block node:
2002 ethernet-block@2000 {
2003 #address-cells = <1>;
2005 compatible = "marvell,mv64360-eth-block";
2006 reg = <0x2000 0x2000>;
2014 Required properties:
2015 - device_type : Should be "network".
2016 - compatible : Should be "marvell,mv64360-eth".
2017 - reg : Should be <0>, <1>, or <2>, according to which registers
2018 within the silicon block the device uses.
2019 - interrupts : <a> where a is the interrupt number for the port.
2020 - interrupt-parent : the phandle for the interrupt controller
2021 that services interrupts for this device.
2022 - phy : the phandle for the PHY connected to this ethernet
2024 - local-mac-address : 6 bytes, MAC address
2026 Example Discovery Ethernet port node:
2028 device_type = "network";
2029 compatible = "marvell,mv64360-eth";
2032 interrupt-parent = <&PIC>;
2034 local-mac-address = [ 00 00 00 00 00 00 ];
2039 c) Marvell Discovery PHY nodes
2041 Required properties:
2042 - device_type : Should be "ethernet-phy"
2043 - interrupts : <a> where a is the interrupt number for this phy.
2044 - interrupt-parent : the phandle for the interrupt controller that
2045 services interrupts for this device.
2046 - reg : The ID number for the phy, usually a small integer
2048 Example Discovery PHY node:
2050 device_type = "ethernet-phy";
2051 compatible = "broadcom,bcm5421";
2052 interrupts = <76>; /* GPP 12 */
2053 interrupt-parent = <&PIC>;
2058 d) Marvell Discovery SDMA nodes
2060 Represent DMA hardware associated with the MPSC (multiprotocol
2061 serial controllers).
2063 Required properties:
2064 - compatible : "marvell,mv64360-sdma"
2065 - reg : Offset and length of the register set for this device
2066 - interrupts : <a> where a is the interrupt number for the DMA
2068 - interrupt-parent : the phandle for the interrupt controller
2069 that services interrupts for this device.
2071 Example Discovery SDMA node:
2073 compatible = "marvell,mv64360-sdma";
2074 reg = <0x4000 0xc18>;
2075 virtual-reg = <0xf1004000>;
2077 interrupt-parent = <&PIC>;
2081 e) Marvell Discovery BRG nodes
2083 Represent baud rate generator hardware associated with the MPSC
2084 (multiprotocol serial controllers).
2086 Required properties:
2087 - compatible : "marvell,mv64360-brg"
2088 - reg : Offset and length of the register set for this device
2089 - clock-src : A value from 0 to 15 which selects the clock
2090 source for the baud rate generator. This value corresponds
2091 to the CLKS value in the BRGx configuration register. See
2092 the mv64x60 User's Manual.
2093 - clock-frequence : The frequency (in Hz) of the baud rate
2094 generator's input clock.
2095 - current-speed : The current speed setting (presumably by
2096 firmware) of the baud rate generator.
2098 Example Discovery BRG node:
2100 compatible = "marvell,mv64360-brg";
2103 clock-frequency = <133333333>;
2104 current-speed = <9600>;
2108 f) Marvell Discovery CUNIT nodes
2110 Represent the Serial Communications Unit device hardware.
2112 Required properties:
2113 - reg : Offset and length of the register set for this device
2115 Example Discovery CUNIT node:
2117 reg = <0xf200 0x200>;
2121 g) Marvell Discovery MPSCROUTING nodes
2123 Represent the Discovery's MPSC routing hardware
2125 Required properties:
2126 - reg : Offset and length of the register set for this device
2128 Example Discovery CUNIT node:
2134 h) Marvell Discovery MPSCINTR nodes
2136 Represent the Discovery's MPSC DMA interrupt hardware registers
2137 (SDMA cause and mask registers).
2139 Required properties:
2140 - reg : Offset and length of the register set for this device
2142 Example Discovery MPSCINTR node:
2144 reg = <0xb800 0x100>;
2148 i) Marvell Discovery MPSC nodes
2150 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
2153 Required properties:
2154 - device_type : "serial"
2155 - compatible : "marvell,mv64360-mpsc"
2156 - reg : Offset and length of the register set for this device
2157 - sdma : the phandle for the SDMA node used by this port
2158 - brg : the phandle for the BRG node used by this port
2159 - cunit : the phandle for the CUNIT node used by this port
2160 - mpscrouting : the phandle for the MPSCROUTING node used by this port
2161 - mpscintr : the phandle for the MPSCINTR node used by this port
2162 - cell-index : the hardware index of this cell in the MPSC core
2163 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
2165 - interrupts : <a> where a is the interrupt number for the MPSC.
2166 - interrupt-parent : the phandle for the interrupt controller
2167 that services interrupts for this device.
2169 Example Discovery MPSCINTR node:
2171 device_type = "serial";
2172 compatible = "marvell,mv64360-mpsc";
2173 reg = <0x8000 0x38>;
2174 virtual-reg = <0xf1008000>;
2178 mpscrouting = <&MPSCROUTING>;
2179 mpscintr = <&MPSCINTR>;
2183 interrupt-parent = <&PIC>;
2187 j) Marvell Discovery Watch Dog Timer nodes
2189 Represent the Discovery's watchdog timer hardware
2191 Required properties:
2192 - compatible : "marvell,mv64360-wdt"
2193 - reg : Offset and length of the register set for this device
2195 Example Discovery Watch Dog Timer node:
2197 compatible = "marvell,mv64360-wdt";
2202 k) Marvell Discovery I2C nodes
2204 Represent the Discovery's I2C hardware
2206 Required properties:
2207 - device_type : "i2c"
2208 - compatible : "marvell,mv64360-i2c"
2209 - reg : Offset and length of the register set for this device
2210 - interrupts : <a> where a is the interrupt number for the I2C.
2211 - interrupt-parent : the phandle for the interrupt controller
2212 that services interrupts for this device.
2214 Example Discovery I2C node:
2215 compatible = "marvell,mv64360-i2c";
2216 reg = <0xc000 0x20>;
2217 virtual-reg = <0xf100c000>;
2219 interrupt-parent = <&PIC>;
2223 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
2225 Represent the Discovery's PIC hardware
2227 Required properties:
2228 - #interrupt-cells : <1>
2229 - #address-cells : <0>
2230 - compatible : "marvell,mv64360-pic"
2231 - reg : Offset and length of the register set for this device
2232 - interrupt-controller
2234 Example Discovery PIC node:
2236 #interrupt-cells = <1>;
2237 #address-cells = <0>;
2238 compatible = "marvell,mv64360-pic";
2240 interrupt-controller;
2244 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
2246 Represent the Discovery's MPP hardware
2248 Required properties:
2249 - compatible : "marvell,mv64360-mpp"
2250 - reg : Offset and length of the register set for this device
2252 Example Discovery MPP node:
2254 compatible = "marvell,mv64360-mpp";
2255 reg = <0xf000 0x10>;
2259 n) Marvell Discovery GPP (General Purpose Pins) nodes
2261 Represent the Discovery's GPP hardware
2263 Required properties:
2264 - compatible : "marvell,mv64360-gpp"
2265 - reg : Offset and length of the register set for this device
2267 Example Discovery GPP node:
2269 compatible = "marvell,mv64360-gpp";
2270 reg = <0xf100 0x20>;
2274 o) Marvell Discovery PCI host bridge node
2276 Represents the Discovery's PCI host bridge device. The properties
2277 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
2278 1275-1994. A typical value for the compatible property is
2279 "marvell,mv64360-pci".
2281 Example Discovery PCI host bridge node
2283 #address-cells = <3>;
2285 #interrupt-cells = <1>;
2286 device_type = "pci";
2287 compatible = "marvell,mv64360-pci";
2289 ranges = <0x01000000 0x0 0x0
2290 0x88000000 0x0 0x01000000
2291 0x02000000 0x0 0x80000000
2292 0x80000000 0x0 0x08000000>;
2293 bus-range = <0 255>;
2294 clock-frequency = <66000000>;
2295 interrupt-parent = <&PIC>;
2296 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2299 0x5000 0 0 1 &PIC 80
2300 0x5000 0 0 2 &PIC 81
2301 0x5000 0 0 3 &PIC 91
2302 0x5000 0 0 4 &PIC 93
2305 0x5800 0 0 1 &PIC 91
2306 0x5800 0 0 2 &PIC 93
2307 0x5800 0 0 3 &PIC 80
2308 0x5800 0 0 4 &PIC 81
2311 0x6000 0 0 1 &PIC 91
2312 0x6000 0 0 2 &PIC 93
2313 0x6000 0 0 3 &PIC 80
2314 0x6000 0 0 4 &PIC 81
2317 0x6800 0 0 1 &PIC 93
2318 0x6800 0 0 2 &PIC 80
2319 0x6800 0 0 3 &PIC 81
2320 0x6800 0 0 4 &PIC 91
2325 p) Marvell Discovery CPU Error nodes
2327 Represent the Discovery's CPU error handler device.
2329 Required properties:
2330 - compatible : "marvell,mv64360-cpu-error"
2331 - reg : Offset and length of the register set for this device
2332 - interrupts : the interrupt number for this device
2333 - interrupt-parent : the phandle for the interrupt controller
2334 that services interrupts for this device.
2336 Example Discovery CPU Error node:
2338 compatible = "marvell,mv64360-cpu-error";
2339 reg = <0x70 0x10 0x128 0x28>;
2341 interrupt-parent = <&PIC>;
2345 q) Marvell Discovery SRAM Controller nodes
2347 Represent the Discovery's SRAM controller device.
2349 Required properties:
2350 - compatible : "marvell,mv64360-sram-ctrl"
2351 - reg : Offset and length of the register set for this device
2352 - interrupts : the interrupt number for this device
2353 - interrupt-parent : the phandle for the interrupt controller
2354 that services interrupts for this device.
2356 Example Discovery SRAM Controller node:
2358 compatible = "marvell,mv64360-sram-ctrl";
2361 interrupt-parent = <&PIC>;
2365 r) Marvell Discovery PCI Error Handler nodes
2367 Represent the Discovery's PCI error handler device.
2369 Required properties:
2370 - compatible : "marvell,mv64360-pci-error"
2371 - reg : Offset and length of the register set for this device
2372 - interrupts : the interrupt number for this device
2373 - interrupt-parent : the phandle for the interrupt controller
2374 that services interrupts for this device.
2376 Example Discovery PCI Error Handler node:
2378 compatible = "marvell,mv64360-pci-error";
2379 reg = <0x1d40 0x40 0xc28 0x4>;
2381 interrupt-parent = <&PIC>;
2385 s) Marvell Discovery Memory Controller nodes
2387 Represent the Discovery's memory controller device.
2389 Required properties:
2390 - compatible : "marvell,mv64360-mem-ctrl"
2391 - reg : Offset and length of the register set for this device
2392 - interrupts : the interrupt number for this device
2393 - interrupt-parent : the phandle for the interrupt controller
2394 that services interrupts for this device.
2396 Example Discovery Memory Controller node:
2398 compatible = "marvell,mv64360-mem-ctrl";
2399 reg = <0x1400 0x60>;
2401 interrupt-parent = <&PIC>;
2405 VIII - Specifying interrupt information for devices
2406 ===================================================
2408 The device tree represents the busses and devices of a hardware
2409 system in a form similar to the physical bus topology of the
2412 In addition, a logical 'interrupt tree' exists which represents the
2413 hierarchy and routing of interrupts in the hardware.
2415 The interrupt tree model is fully described in the
2416 document "Open Firmware Recommended Practice: Interrupt
2417 Mapping Version 0.9". The document is available at:
2418 <http://playground.sun.com/1275/practice>.
2420 1) interrupts property
2421 ----------------------
2423 Devices that generate interrupts to a single interrupt controller
2424 should use the conventional OF representation described in the
2425 OF interrupt mapping documentation.
2427 Each device which generates interrupts must have an 'interrupt'
2428 property. The interrupt property value is an arbitrary number of
2429 of 'interrupt specifier' values which describe the interrupt or
2430 interrupts for the device.
2432 The encoding of an interrupt specifier is determined by the
2433 interrupt domain in which the device is located in the
2434 interrupt tree. The root of an interrupt domain specifies in
2435 its #interrupt-cells property the number of 32-bit cells
2436 required to encode an interrupt specifier. See the OF interrupt
2437 mapping documentation for a detailed description of domains.
2439 For example, the binding for the OpenPIC interrupt controller
2440 specifies an #interrupt-cells value of 2 to encode the interrupt
2441 number and level/sense information. All interrupt children in an
2442 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
2445 The PCI bus binding specifies a #interrupt-cell value of 1 to encode
2446 which interrupt pin (INTA,INTB,INTC,INTD) is used.
2448 2) interrupt-parent property
2449 ----------------------------
2451 The interrupt-parent property is specified to define an explicit
2452 link between a device node and its interrupt parent in
2453 the interrupt tree. The value of interrupt-parent is the
2454 phandle of the parent node.
2456 If the interrupt-parent property is not defined for a node, it's
2457 interrupt parent is assumed to be an ancestor in the node's
2458 _device tree_ hierarchy.
2460 3) OpenPIC Interrupt Controllers
2461 --------------------------------
2463 OpenPIC interrupt controllers require 2 cells to encode
2464 interrupt information. The first cell defines the interrupt
2465 number. The second cell defines the sense and level
2468 Sense and level information should be encoded as follows:
2470 0 = low to high edge sensitive type enabled
2471 1 = active low level sensitive type enabled
2472 2 = active high level sensitive type enabled
2473 3 = high to low edge sensitive type enabled
2475 4) ISA Interrupt Controllers
2476 ----------------------------
2478 ISA PIC interrupt controllers require 2 cells to encode
2479 interrupt information. The first cell defines the interrupt
2480 number. The second cell defines the sense and level
2483 ISA PIC interrupt controllers should adhere to the ISA PIC
2484 encodings listed below:
2486 0 = active low level sensitive type enabled
2487 1 = active high level sensitive type enabled
2488 2 = high to low edge sensitive type enabled
2489 3 = low to high edge sensitive type enabled
2491 VIII - Specifying GPIO information for devices
2492 ==============================================
2497 Nodes that makes use of GPIOs should define them using `gpios' property,
2498 format of which is: <&gpio-controller1-phandle gpio1-specifier
2499 &gpio-controller2-phandle gpio2-specifier
2500 0 /* holes are permitted, means no GPIO 3 */
2501 &gpio-controller4-phandle gpio4-specifier
2504 Note that gpio-specifier length is controller dependent.
2506 gpio-specifier may encode: bank, pin position inside the bank,
2507 whether pin is open-drain and whether pin is logically inverted.
2509 Example of the node using GPIOs:
2512 gpios = <&qe_pio_e 18 0>;
2515 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
2516 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2518 2) gpio-controller nodes
2519 ------------------------
2521 Every GPIO controller node must have #gpio-cells property defined,
2522 this information will be used to translate gpio-specifiers.
2524 Example of two SOC GPIO banks defined as gpio-controller nodes:
2526 qe_pio_a: gpio-controller@1400 {
2528 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
2529 reg = <0x1400 0x18>;
2533 qe_pio_e: gpio-controller@1460 {
2535 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
2536 reg = <0x1460 0x18>;
2540 Appendix A - Sample SOC node for MPC8540
2541 ========================================
2543 Note that the #address-cells and #size-cells for the SoC node
2544 in this example have been explicitly listed; these are likely
2545 not necessary as they are usually the same as the root node.
2548 #address-cells = <1>;
2550 #interrupt-cells = <2>;
2551 device_type = "soc";
2552 ranges = <00000000 e0000000 00100000>
2553 reg = <e0000000 00003000>;
2554 bus-frequency = <0>;
2558 device_type = "mdio";
2559 compatible = "gianfar";
2562 linux,phandle = <2452000>
2563 interrupt-parent = <40000>;
2564 interrupts = <35 1>;
2566 device_type = "ethernet-phy";
2570 linux,phandle = <2452001>
2571 interrupt-parent = <40000>;
2572 interrupts = <35 1>;
2574 device_type = "ethernet-phy";
2578 linux,phandle = <2452002>
2579 interrupt-parent = <40000>;
2580 interrupts = <35 1>;
2582 device_type = "ethernet-phy";
2589 device_type = "network";
2591 compatible = "gianfar";
2593 mac-address = [ 00 E0 0C 00 73 00 ];
2594 interrupts = <d 3 e 3 12 3>;
2595 interrupt-parent = <40000>;
2596 phy-handle = <2452000>;
2600 #address-cells = <1>;
2602 device_type = "network";
2604 compatible = "gianfar";
2606 mac-address = [ 00 E0 0C 00 73 01 ];
2607 interrupts = <13 3 14 3 18 3>;
2608 interrupt-parent = <40000>;
2609 phy-handle = <2452001>;
2613 #address-cells = <1>;
2615 device_type = "network";
2617 compatible = "gianfar";
2619 mac-address = [ 00 E0 0C 00 73 02 ];
2620 interrupts = <19 3>;
2621 interrupt-parent = <40000>;
2622 phy-handle = <2452002>;
2626 device_type = "serial";
2627 compatible = "ns16550";
2629 clock-frequency = <0>;
2630 interrupts = <1a 3>;
2631 interrupt-parent = <40000>;
2635 linux,phandle = <40000>;
2636 interrupt-controller;
2637 #address-cells = <0>;
2638 reg = <40000 40000>;
2639 compatible = "chrp,open-pic";
2640 device_type = "open-pic";
2644 interrupt-parent = <40000>;
2645 interrupts = <1b 3>;
2647 device_type = "i2c";
2648 compatible = "fsl-i2c";