1 Booting the Linux/ppc kernel without Open Firmware
2 --------------------------------------------------
4 (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
6 (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
7 Freescale Semiconductor, FSL SOC and 32-bit additions
8 (c) 2006 MontaVista Software, Inc.
9 Flash chip node definition
15 1) Entry point for arch/powerpc
18 II - The DT block format
20 2) Device tree generalities
21 3) Device tree "structure" block
22 4) Device tree "strings" block
24 III - Required content of the device tree
25 1) Note about cells and address representation
26 2) Note about "compatible" properties
27 3) Note about "name" properties
28 4) Note about node and property names and character set
29 5) Required nodes and properties
33 d) the /memory node(s)
35 f) the /soc<SOCname> node
37 IV - "dtc", the device tree compiler
39 V - Recommendations for a bootloader
41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification
45 b) Interrupt controllers
46 c) CFI or JEDEC memory-mapped NOR flash
47 d) 4xx/Axon EMAC ethernet nodes
49 f) USB EHCI controllers
51 VII - Marvell Discovery mv64[345]6x System Controller chips
52 1) The /system-controller node
53 2) Child nodes of /system-controller
54 a) Marvell Discovery MDIO bus
55 b) Marvell Discovery ethernet controller
56 c) Marvell Discovery PHY nodes
57 d) Marvell Discovery SDMA nodes
58 e) Marvell Discovery BRG nodes
59 f) Marvell Discovery CUNIT nodes
60 g) Marvell Discovery MPSCROUTING nodes
61 h) Marvell Discovery MPSCINTR nodes
62 i) Marvell Discovery MPSC nodes
63 j) Marvell Discovery Watch Dog Timer nodes
64 k) Marvell Discovery I2C nodes
65 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
66 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
67 n) Marvell Discovery GPP (General Purpose Pins) nodes
68 o) Marvell Discovery PCI host bridge node
69 p) Marvell Discovery CPU Error nodes
70 q) Marvell Discovery SRAM Controller nodes
71 r) Marvell Discovery PCI Error Handler nodes
72 s) Marvell Discovery Memory Controller nodes
74 VIII - Specifying interrupt information for devices
75 1) interrupts property
76 2) interrupt-parent property
77 3) OpenPIC Interrupt Controllers
78 4) ISA Interrupt Controllers
80 VIII - Specifying GPIO information for devices
82 2) gpio-controller nodes
84 Appendix A - Sample SOC node for MPC8540
90 May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
92 May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
93 clarifies the fact that a lot of things are
94 optional, the kernel only requires a very
95 small device tree, though it is encouraged
96 to provide an as complete one as possible.
98 May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
100 - Define version 3 and new format version 16
101 for the DT block (version 16 needs kernel
102 patches, will be fwd separately).
103 String block now has a size, and full path
104 is replaced by unit name for more
106 linux,phandle is made optional, only nodes
107 that are referenced by other nodes need it.
108 "name" property is now automatically
109 deduced from the unit name
111 June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
112 OF_DT_END_NODE in structure definition.
113 - Change version 16 format to always align
114 property data to 4 bytes. Since tokens are
115 already aligned, that means no specific
116 required alignment between property size
117 and property data. The old style variable
118 alignment would make it impossible to do
119 "simple" insertion of properties using
120 memmove (thanks Milton for
121 noticing). Updated kernel patch as well
122 - Correct a few more alignment constraints
123 - Add a chapter about the device-tree
124 compiler and the textural representation of
125 the tree that can be "compiled" by dtc.
127 November 21, 2005: Rev 0.5
128 - Additions/generalizations for 32-bit
129 - Changed to reflect the new arch/powerpc
135 - Add some definitions of interrupt tree (simple/complex)
136 - Add some definitions for PCI host bridges
137 - Add some common address format examples
138 - Add definitions for standard properties and "compatible"
139 names for cells that are not already defined by the existing
141 - Compare FSL SOC use of PCI to standard and make sure no new
142 node definition required.
143 - Add more information about node definitions for SOC devices
144 that currently have no standard, like the FSL CPM.
150 During the recent development of the Linux/ppc64 kernel, and more
151 specifically, the addition of new platform types outside of the old
152 IBM pSeries/iSeries pair, it was decided to enforce some strict rules
153 regarding the kernel entry and bootloader <-> kernel interfaces, in
154 order to avoid the degeneration that had become the ppc32 kernel entry
155 point and the way a new platform should be added to the kernel. The
156 legacy iSeries platform breaks those rules as it predates this scheme,
157 but no new board support will be accepted in the main tree that
158 doesn't follows them properly. In addition, since the advent of the
159 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
160 platforms and 32-bit platforms which move into arch/powerpc will be
161 required to use these rules as well.
163 The main requirement that will be defined in more detail below is
164 the presence of a device-tree whose format is defined after Open
165 Firmware specification. However, in order to make life easier
166 to embedded board vendors, the kernel doesn't require the device-tree
167 to represent every device in the system and only requires some nodes
168 and properties to be present. This will be described in detail in
169 section III, but, for example, the kernel does not require you to
170 create a node for every PCI device in the system. It is a requirement
171 to have a node for PCI host bridges in order to provide interrupt
172 routing informations and memory/IO ranges, among others. It is also
173 recommended to define nodes for on chip devices and other busses that
174 don't specifically fit in an existing OF specification. This creates a
175 great flexibility in the way the kernel can then probe those and match
176 drivers to device, without having to hard code all sorts of tables. It
177 also makes it more flexible for board vendors to do minor hardware
178 upgrades without significantly impacting the kernel code or cluttering
179 it with special cases.
182 1) Entry point for arch/powerpc
183 -------------------------------
185 There is one and one single entry point to the kernel, at the start
186 of the kernel image. That entry point supports two calling
189 a) Boot from Open Firmware. If your firmware is compatible
190 with Open Firmware (IEEE 1275) or provides an OF compatible
191 client interface API (support for "interpret" callback of
192 forth words isn't required), you can enter the kernel with:
194 r5 : OF callback pointer as defined by IEEE 1275
195 bindings to powerpc. Only the 32-bit client interface
196 is currently supported
198 r3, r4 : address & length of an initrd if any or 0
200 The MMU is either on or off; the kernel will run the
201 trampoline located in arch/powerpc/kernel/prom_init.c to
202 extract the device-tree and other information from open
203 firmware and build a flattened device-tree as described
204 in b). prom_init() will then re-enter the kernel using
205 the second method. This trampoline code runs in the
206 context of the firmware, which is supposed to handle all
207 exceptions during that time.
209 b) Direct entry with a flattened device-tree block. This entry
210 point is called by a) after the OF trampoline and can also be
211 called directly by a bootloader that does not support the Open
212 Firmware client interface. It is also used by "kexec" to
213 implement "hot" booting of a new kernel from a previous
214 running one. This method is what I will describe in more
215 details in this document, as method a) is simply standard Open
216 Firmware, and thus should be implemented according to the
217 various standard documents defining it and its binding to the
218 PowerPC platform. The entry point definition then becomes:
220 r3 : physical pointer to the device-tree block
221 (defined in chapter II) in RAM
223 r4 : physical pointer to the kernel itself. This is
224 used by the assembly code to properly disable the MMU
225 in case you are entering the kernel with MMU enabled
226 and a non-1:1 mapping.
228 r5 : NULL (as to differentiate with method a)
230 Note about SMP entry: Either your firmware puts your other
231 CPUs in some sleep loop or spin loop in ROM where you can get
232 them out via a soft reset or some other means, in which case
233 you don't need to care, or you'll have to enter the kernel
234 with all CPUs. The way to do that with method b) will be
235 described in a later revision of this document.
243 Board supports (platforms) are not exclusive config options. An
244 arbitrary set of board supports can be built in a single kernel
245 image. The kernel will "know" what set of functions to use for a
246 given platform based on the content of the device-tree. Thus, you
249 a) add your platform support as a _boolean_ option in
250 arch/powerpc/Kconfig, following the example of PPC_PSERIES,
251 PPC_PMAC and PPC_MAPLE. The later is probably a good
252 example of a board support to start from.
254 b) create your main platform file as
255 "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
256 to the Makefile under the condition of your CONFIG_
257 option. This file will define a structure of type "ppc_md"
258 containing the various callbacks that the generic code will
259 use to get to your platform specific code
261 c) Add a reference to your "ppc_md" structure in the
262 "machines" table in arch/powerpc/kernel/setup_64.c if you are
265 d) request and get assigned a platform number (see PLATFORM_*
266 constants in include/asm-powerpc/processor.h
268 32-bit embedded kernels:
270 Currently, board support is essentially an exclusive config option.
271 The kernel is configured for a single platform. Part of the reason
272 for this is to keep kernels on embedded systems small and efficient;
273 part of this is due to the fact the code is already that way. In the
274 future, a kernel may support multiple platforms, but only if the
275 platforms feature the same core architecture. A single kernel build
276 cannot support both configurations with Book E and configurations
277 with classic Powerpc architectures.
279 32-bit embedded platforms that are moved into arch/powerpc using a
280 flattened device tree should adopt the merged tree practice of
281 setting ppc_md up dynamically, even though the kernel is currently
282 built with support for only a single platform at a time. This allows
283 unification of the setup code, and will make it easier to go to a
284 multiple-platform-support model in the future.
286 NOTE: I believe the above will be true once Ben's done with the merge
287 of the boot sequences.... someone speak up if this is wrong!
289 To add a 32-bit embedded platform support, follow the instructions
290 for 64-bit platforms above, with the exception that the Kconfig
291 option should be set up such that the kernel builds exclusively for
292 the platform selected. The processor type for the platform should
293 enable another config option to select the specific board
296 NOTE: If Ben doesn't merge the setup files, may need to change this to
300 I will describe later the boot process and various callbacks that
301 your platform should implement.
304 II - The DT block format
305 ========================
308 This chapter defines the actual format of the flattened device-tree
309 passed to the kernel. The actual content of it and kernel requirements
310 are described later. You can find example of code manipulating that
311 format in various places, including arch/powerpc/kernel/prom_init.c
312 which will generate a flattened device-tree from the Open Firmware
313 representation, or the fs2dt utility which is part of the kexec tools
314 which will generate one from a filesystem representation. It is
315 expected that a bootloader like uboot provides a bit more support,
316 that will be discussed later as well.
318 Note: The block has to be in main memory. It has to be accessible in
319 both real mode and virtual mode with no mapping other than main
320 memory. If you are writing a simple flash bootloader, it should copy
321 the block to RAM before passing it to the kernel.
327 The kernel is entered with r3 pointing to an area of memory that is
328 roughly described in include/asm-powerpc/prom.h by the structure
331 struct boot_param_header {
332 u32 magic; /* magic word OF_DT_HEADER */
333 u32 totalsize; /* total size of DT block */
334 u32 off_dt_struct; /* offset to structure */
335 u32 off_dt_strings; /* offset to strings */
336 u32 off_mem_rsvmap; /* offset to memory reserve map
338 u32 version; /* format version */
339 u32 last_comp_version; /* last compatible version */
341 /* version 2 fields below */
342 u32 boot_cpuid_phys; /* Which physical CPU id we're
344 /* version 3 fields below */
345 u32 size_dt_strings; /* size of the strings block */
347 /* version 17 fields below */
348 u32 size_dt_struct; /* size of the DT structure block */
351 Along with the constants:
353 /* Definitions used by the flattened device tree */
354 #define OF_DT_HEADER 0xd00dfeed /* 4: version,
356 #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
358 #define OF_DT_END_NODE 0x2 /* End node */
359 #define OF_DT_PROP 0x3 /* Property: name off,
361 #define OF_DT_END 0x9
363 All values in this header are in big endian format, the various
364 fields in this header are defined more precisely below. All
365 "offset" values are in bytes from the start of the header; that is
366 from the value of r3.
370 This is a magic value that "marks" the beginning of the
371 device-tree block header. It contains the value 0xd00dfeed and is
372 defined by the constant OF_DT_HEADER
376 This is the total size of the DT block including the header. The
377 "DT" block should enclose all data structures defined in this
378 chapter (who are pointed to by offsets in this header). That is,
379 the device-tree structure, strings, and the memory reserve map.
383 This is an offset from the beginning of the header to the start
384 of the "structure" part the device tree. (see 2) device tree)
388 This is an offset from the beginning of the header to the start
389 of the "strings" part of the device-tree
393 This is an offset from the beginning of the header to the start
394 of the reserved memory map. This map is a list of pairs of 64-
395 bit integers. Each pair is a physical address and a size. The
396 list is terminated by an entry of size 0. This map provides the
397 kernel with a list of physical memory areas that are "reserved"
398 and thus not to be used for memory allocations, especially during
399 early initialization. The kernel needs to allocate memory during
400 boot for things like un-flattening the device-tree, allocating an
401 MMU hash table, etc... Those allocations must be done in such a
402 way to avoid overriding critical things like, on Open Firmware
403 capable machines, the RTAS instance, or on some pSeries, the TCE
404 tables used for the iommu. Typically, the reserve map should
405 contain _at least_ this DT block itself (header,total_size). If
406 you are passing an initrd to the kernel, you should reserve it as
407 well. You do not need to reserve the kernel image itself. The map
408 should be 64-bit aligned.
412 This is the version of this structure. Version 1 stops
413 here. Version 2 adds an additional field boot_cpuid_phys.
414 Version 3 adds the size of the strings block, allowing the kernel
415 to reallocate it easily at boot and free up the unused flattened
416 structure after expansion. Version 16 introduces a new more
417 "compact" format for the tree itself that is however not backward
418 compatible. Version 17 adds an additional field, size_dt_struct,
419 allowing it to be reallocated or moved more easily (this is
420 particularly useful for bootloaders which need to make
421 adjustments to a device tree based on probed information). You
422 should always generate a structure of the highest version defined
423 at the time of your implementation. Currently that is version 17,
424 unless you explicitly aim at being backward compatible.
428 Last compatible version. This indicates down to what version of
429 the DT block you are backward compatible. For example, version 2
430 is backward compatible with version 1 (that is, a kernel build
431 for version 1 will be able to boot with a version 2 format). You
432 should put a 1 in this field if you generate a device tree of
433 version 1 to 3, or 16 if you generate a tree of version 16 or 17
434 using the new unit name format.
438 This field only exist on version 2 headers. It indicate which
439 physical CPU ID is calling the kernel entry point. This is used,
440 among others, by kexec. If you are on an SMP system, this value
441 should match the content of the "reg" property of the CPU node in
442 the device-tree corresponding to the CPU calling the kernel entry
443 point (see further chapters for more informations on the required
444 device-tree contents)
448 This field only exists on version 3 and later headers. It
449 gives the size of the "strings" section of the device tree (which
450 starts at the offset given by off_dt_strings).
454 This field only exists on version 17 and later headers. It gives
455 the size of the "structure" section of the device tree (which
456 starts at the offset given by off_dt_struct).
458 So the typical layout of a DT block (though the various parts don't
459 need to be in that order) looks like this (addresses go from top to
463 ------------------------------
464 r3 -> | struct boot_param_header |
465 ------------------------------
466 | (alignment gap) (*) |
467 ------------------------------
468 | memory reserve map |
469 ------------------------------
471 ------------------------------
473 | device-tree structure |
475 ------------------------------
477 ------------------------------
479 | device-tree strings |
481 -----> ------------------------------
486 (*) The alignment gaps are not necessarily present; their presence
487 and size are dependent on the various alignment requirements of
488 the individual data blocks.
491 2) Device tree generalities
492 ---------------------------
494 This device-tree itself is separated in two different blocks, a
495 structure block and a strings block. Both need to be aligned to a 4
498 First, let's quickly describe the device-tree concept before detailing
499 the storage format. This chapter does _not_ describe the detail of the
500 required types of nodes & properties for the kernel, this is done
501 later in chapter III.
503 The device-tree layout is strongly inherited from the definition of
504 the Open Firmware IEEE 1275 device-tree. It's basically a tree of
505 nodes, each node having two or more named properties. A property can
508 It is a tree, so each node has one and only one parent except for the
509 root node who has no parent.
511 A node has 2 names. The actual node name is generally contained in a
512 property of type "name" in the node property list whose value is a
513 zero terminated string and is mandatory for version 1 to 3 of the
514 format definition (as it is in Open Firmware). Version 16 makes it
515 optional as it can generate it from the unit name defined below.
517 There is also a "unit name" that is used to differentiate nodes with
518 the same name at the same level, it is usually made of the node
519 names, the "@" sign, and a "unit address", which definition is
520 specific to the bus type the node sits on.
522 The unit name doesn't exist as a property per-se but is included in
523 the device-tree structure. It is typically used to represent "path" in
524 the device-tree. More details about the actual format of these will be
527 The kernel powerpc generic code does not make any formal use of the
528 unit address (though some board support code may do) so the only real
529 requirement here for the unit address is to ensure uniqueness of
530 the node unit name at a given level of the tree. Nodes with no notion
531 of address and no possible sibling of the same name (like /memory or
532 /cpus) may omit the unit address in the context of this specification,
533 or use the "@0" default unit address. The unit name is used to define
534 a node "full path", which is the concatenation of all parent node
535 unit names separated with "/".
537 The root node doesn't have a defined name, and isn't required to have
538 a name property either if you are using version 3 or earlier of the
539 format. It also has no unit address (no @ symbol followed by a unit
540 address). The root node unit name is thus an empty string. The full
541 path to the root node is "/".
543 Every node which actually represents an actual device (that is, a node
544 which isn't only a virtual "container" for more nodes, like "/cpus"
545 is) is also required to have a "device_type" property indicating the
548 Finally, every node that can be referenced from a property in another
549 node is required to have a "linux,phandle" property. Real open
550 firmware implementations provide a unique "phandle" value for every
551 node that the "prom_init()" trampoline code turns into
552 "linux,phandle" properties. However, this is made optional if the
553 flattened device tree is used directly. An example of a node
554 referencing another node via "phandle" is when laying out the
555 interrupt tree which will be described in a further version of this
558 This "linux, phandle" property is a 32-bit value that uniquely
559 identifies a node. You are free to use whatever values or system of
560 values, internal pointers, or whatever to generate these, the only
561 requirement is that every node for which you provide that property has
562 a unique value for it.
564 Here is an example of a simple device-tree. In this example, an "o"
565 designates a node followed by the node unit name. Properties are
566 presented with their name followed by their content. "content"
567 represents an ASCII string (zero terminated) value, while <content>
568 represents a 32-bit hexadecimal value. The various nodes in this
569 example will be discussed in a later chapter. At this point, it is
570 only meant to give you a idea of what a device-tree looks like. I have
571 purposefully kept the "name" and "linux,phandle" properties which
572 aren't necessary in order to give you a better idea of what the tree
573 looks like in practice.
576 |- name = "device-tree"
577 |- model = "MyBoardName"
578 |- compatible = "MyBoardFamilyName"
579 |- #address-cells = <2>
581 |- linux,phandle = <0>
585 | | - linux,phandle = <1>
586 | | - #address-cells = <1>
587 | | - #size-cells = <0>
590 | |- name = "PowerPC,970"
591 | |- device_type = "cpu"
593 | |- clock-frequency = <5f5e1000>
595 | |- linux,phandle = <2>
599 | |- device_type = "memory"
600 | |- reg = <00000000 00000000 00000000 20000000>
601 | |- linux,phandle = <3>
605 |- bootargs = "root=/dev/sda2"
606 |- linux,phandle = <4>
608 This tree is almost a minimal tree. It pretty much contains the
609 minimal set of required nodes and properties to boot a linux kernel;
610 that is, some basic model informations at the root, the CPUs, and the
611 physical memory layout. It also includes misc information passed
612 through /chosen, like in this example, the platform type (mandatory)
613 and the kernel command line arguments (optional).
615 The /cpus/PowerPC,970@0/64-bit property is an example of a
616 property without a value. All other properties have a value. The
617 significance of the #address-cells and #size-cells properties will be
618 explained in chapter IV which defines precisely the required nodes and
619 properties and their content.
622 3) Device tree "structure" block
624 The structure of the device tree is a linearized tree structure. The
625 "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
626 ends that node definition. Child nodes are simply defined before
627 "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
628 bit value. The tree has to be "finished" with a OF_DT_END token
630 Here's the basic structure of a single node:
632 * token OF_DT_BEGIN_NODE (that is 0x00000001)
633 * for version 1 to 3, this is the node full path as a zero
634 terminated string, starting with "/". For version 16 and later,
635 this is the node unit name only (or an empty string for the
637 * [align gap to next 4 bytes boundary]
639 * token OF_DT_PROP (that is 0x00000003)
640 * 32-bit value of property value size in bytes (or 0 if no
642 * 32-bit value of offset in string block of property name
643 * property value data if any
644 * [align gap to next 4 bytes boundary]
645 * [child nodes if any]
646 * token OF_DT_END_NODE (that is 0x00000002)
648 So the node content can be summarized as a start token, a full path,
649 a list of properties, a list of child nodes, and an end token. Every
650 child node is a full node structure itself as defined above.
652 NOTE: The above definition requires that all property definitions for
653 a particular node MUST precede any subnode definitions for that node.
654 Although the structure would not be ambiguous if properties and
655 subnodes were intermingled, the kernel parser requires that the
656 properties come first (up until at least 2.6.22). Any tools
657 manipulating a flattened tree must take care to preserve this
660 4) Device tree "strings" block
662 In order to save space, property names, which are generally redundant,
663 are stored separately in the "strings" block. This block is simply the
664 whole bunch of zero terminated strings for all property names
665 concatenated together. The device-tree property definitions in the
666 structure block will contain offset values from the beginning of the
670 III - Required content of the device tree
671 =========================================
673 WARNING: All "linux,*" properties defined in this document apply only
674 to a flattened device-tree. If your platform uses a real
675 implementation of Open Firmware or an implementation compatible with
676 the Open Firmware client interface, those properties will be created
677 by the trampoline code in the kernel's prom_init() file. For example,
678 that's where you'll have to add code to detect your board model and
679 set the platform number. However, when using the flattened device-tree
680 entry point, there is no prom_init() pass, and thus you have to
681 provide those properties yourself.
684 1) Note about cells and address representation
685 ----------------------------------------------
687 The general rule is documented in the various Open Firmware
688 documentations. If you choose to describe a bus with the device-tree
689 and there exist an OF bus binding, then you should follow the
690 specification. However, the kernel does not require every single
691 device or bus to be described by the device tree.
693 In general, the format of an address for a device is defined by the
694 parent bus type, based on the #address-cells and #size-cells
695 properties. Note that the parent's parent definitions of #address-cells
696 and #size-cells are not inhereted so every node with children must specify
697 them. The kernel requires the root node to have those properties defining
698 addresses format for devices directly mapped on the processor bus.
700 Those 2 properties define 'cells' for representing an address and a
701 size. A "cell" is a 32-bit number. For example, if both contain 2
702 like the example tree given above, then an address and a size are both
703 composed of 2 cells, and each is a 64-bit number (cells are
704 concatenated and expected to be in big endian format). Another example
705 is the way Apple firmware defines them, with 2 cells for an address
706 and one cell for a size. Most 32-bit implementations should define
707 #address-cells and #size-cells to 1, which represents a 32-bit value.
708 Some 32-bit processors allow for physical addresses greater than 32
709 bits; these processors should define #address-cells as 2.
711 "reg" properties are always a tuple of the type "address size" where
712 the number of cells of address and size is specified by the bus
713 #address-cells and #size-cells. When a bus supports various address
714 spaces and other flags relative to a given address allocation (like
715 prefetchable, etc...) those flags are usually added to the top level
716 bits of the physical address. For example, a PCI physical address is
717 made of 3 cells, the bottom two containing the actual address itself
718 while the top cell contains address space indication, flags, and pci
719 bus & device numbers.
721 For busses that support dynamic allocation, it's the accepted practice
722 to then not provide the address in "reg" (keep it 0) though while
723 providing a flag indicating the address is dynamically allocated, and
724 then, to provide a separate "assigned-addresses" property that
725 contains the fully allocated addresses. See the PCI OF bindings for
728 In general, a simple bus with no address space bits and no dynamic
729 allocation is preferred if it reflects your hardware, as the existing
730 kernel address parsing functions will work out of the box. If you
731 define a bus type with a more complex address format, including things
732 like address space bits, you'll have to add a bus translator to the
733 prom_parse.c file of the recent kernels for your bus type.
735 The "reg" property only defines addresses and sizes (if #size-cells is
736 non-0) within a given bus. In order to translate addresses upward
737 (that is into parent bus addresses, and possibly into CPU physical
738 addresses), all busses must contain a "ranges" property. If the
739 "ranges" property is missing at a given level, it's assumed that
740 translation isn't possible, i.e., the registers are not visible on the
741 parent bus. The format of the "ranges" property for a bus is a list
744 bus address, parent bus address, size
746 "bus address" is in the format of the bus this bus node is defining,
747 that is, for a PCI bridge, it would be a PCI address. Thus, (bus
748 address, size) defines a range of addresses for child devices. "parent
749 bus address" is in the format of the parent bus of this bus. For
750 example, for a PCI host controller, that would be a CPU address. For a
751 PCI<->ISA bridge, that would be a PCI address. It defines the base
752 address in the parent bus where the beginning of that range is mapped.
754 For a new 64-bit powerpc board, I recommend either the 2/2 format or
755 Apple's 2/1 format which is slightly more compact since sizes usually
756 fit in a single 32-bit word. New 32-bit powerpc boards should use a
757 1/1 format, unless the processor supports physical addresses greater
758 than 32-bits, in which case a 2/1 format is recommended.
760 Alternatively, the "ranges" property may be empty, indicating that the
761 registers are visible on the parent bus using an identity mapping
762 translation. In other words, the parent bus address space is the same
763 as the child bus address space.
765 2) Note about "compatible" properties
766 -------------------------------------
768 These properties are optional, but recommended in devices and the root
769 node. The format of a "compatible" property is a list of concatenated
770 zero terminated strings. They allow a device to express its
771 compatibility with a family of similar devices, in some cases,
772 allowing a single driver to match against several devices regardless
773 of their actual names.
775 3) Note about "name" properties
776 -------------------------------
778 While earlier users of Open Firmware like OldWorld macintoshes tended
779 to use the actual device name for the "name" property, it's nowadays
780 considered a good practice to use a name that is closer to the device
781 class (often equal to device_type). For example, nowadays, ethernet
782 controllers are named "ethernet", an additional "model" property
783 defining precisely the chip type/model, and "compatible" property
784 defining the family in case a single driver can driver more than one
785 of these chips. However, the kernel doesn't generally put any
786 restriction on the "name" property; it is simply considered good
787 practice to follow the standard and its evolutions as closely as
790 Note also that the new format version 16 makes the "name" property
791 optional. If it's absent for a node, then the node's unit name is then
792 used to reconstruct the name. That is, the part of the unit name
793 before the "@" sign is used (or the entire unit name if no "@" sign
796 4) Note about node and property names and character set
797 -------------------------------------------------------
799 While open firmware provides more flexible usage of 8859-1, this
800 specification enforces more strict rules. Nodes and properties should
801 be comprised only of ASCII characters 'a' to 'z', '0' to
802 '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
803 allow uppercase characters 'A' to 'Z' (property names should be
804 lowercase. The fact that vendors like Apple don't respect this rule is
805 irrelevant here). Additionally, node and property names should always
806 begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
809 The maximum number of characters for both nodes and property names
810 is 31. In the case of node names, this is only the leftmost part of
811 a unit name (the pure "name" property), it doesn't include the unit
812 address which can extend beyond that limit.
815 5) Required nodes and properties
816 --------------------------------
817 These are all that are currently required. However, it is strongly
818 recommended that you expose PCI host bridges as documented in the
819 PCI binding to open firmware, and your interrupt tree as documented
820 in OF interrupt tree specification.
824 The root node requires some properties to be present:
826 - model : this is your board name/model
827 - #address-cells : address representation for "root" devices
828 - #size-cells: the size representation for "root" devices
829 - device_type : This property shouldn't be necessary. However, if
830 you decide to create a device_type for your root node, make sure it
831 is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
832 one for 64-bit, or a CHRP-type machine for 32-bit as this will
833 matched by the kernel this way.
835 Additionally, some recommended properties are:
837 - compatible : the board "family" generally finds its way here,
838 for example, if you have 2 board models with a similar layout,
839 that typically get driven by the same platform code in the
840 kernel, you would use a different "model" property but put a
841 value in "compatible". The kernel doesn't directly use that
842 value but it is generally useful.
844 The root node is also generally where you add additional properties
845 specific to your board like the serial number if any, that sort of
846 thing. It is recommended that if you add any "custom" property whose
847 name may clash with standard defined ones, you prefix them with your
848 vendor name and a comma.
852 This node is the parent of all individual CPU nodes. It doesn't
853 have any specific requirements, though it's generally good practice
856 #address-cells = <00000001>
857 #size-cells = <00000000>
859 This defines that the "address" for a CPU is a single cell, and has
860 no meaningful size. This is not necessary but the kernel will assume
861 that format when reading the "reg" properties of a CPU node, see
866 So under /cpus, you are supposed to create a node for every CPU on
867 the machine. There is no specific restriction on the name of the
868 CPU, though It's common practice to call it PowerPC,<name>. For
869 example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
873 - device_type : has to be "cpu"
874 - reg : This is the physical CPU number, it's a single 32-bit cell
875 and is also used as-is as the unit number for constructing the
876 unit name in the full path. For example, with 2 CPUs, you would
878 /cpus/PowerPC,970FX@0
879 /cpus/PowerPC,970FX@1
880 (unit addresses do not require leading zeroes)
881 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
882 - i-cache-block-size : one cell, L1 instruction cache block size in
884 - d-cache-size : one cell, size of L1 data cache in bytes
885 - i-cache-size : one cell, size of L1 instruction cache in bytes
887 (*) The cache "block" size is the size on which the cache management
888 instructions operate. Historically, this document used the cache
889 "line" size here which is incorrect. The kernel will prefer the cache
890 block size and will fallback to cache line size for backward
893 Recommended properties:
895 - timebase-frequency : a cell indicating the frequency of the
896 timebase in Hz. This is not directly used by the generic code,
897 but you are welcome to copy/paste the pSeries code for setting
898 the kernel timebase/decrementer calibration based on this
900 - clock-frequency : a cell indicating the CPU core clock frequency
901 in Hz. A new property will be defined for 64-bit values, but if
902 your frequency is < 4Ghz, one cell is enough. Here as well as
903 for the above, the common code doesn't use that property, but
904 you are welcome to re-use the pSeries or Maple one. A future
905 kernel version might provide a common function for this.
906 - d-cache-line-size : one cell, L1 data cache line size in bytes
907 if different from the block size
908 - i-cache-line-size : one cell, L1 instruction cache line size in
909 bytes if different from the block size
911 You are welcome to add any property you find relevant to your board,
912 like some information about the mechanism used to soft-reset the
913 CPUs. For example, Apple puts the GPIO number for CPU soft reset
914 lines in there as a "soft-reset" property since they start secondary
915 CPUs by soft-resetting them.
918 d) the /memory node(s)
920 To define the physical memory layout of your board, you should
921 create one or more memory node(s). You can either create a single
922 node with all memory ranges in its reg property, or you can create
923 several nodes, as you wish. The unit address (@ part) used for the
924 full path is the address of the first range of memory defined by a
925 given node. If you use a single memory node, this will typically be
930 - device_type : has to be "memory"
931 - reg : This property contains all the physical memory ranges of
932 your board. It's a list of addresses/sizes concatenated
933 together, with the number of cells of each defined by the
934 #address-cells and #size-cells of the root node. For example,
935 with both of these properties being 2 like in the example given
936 earlier, a 970 based machine with 6Gb of RAM could typically
937 have a "reg" property here that looks like:
939 00000000 00000000 00000000 80000000
940 00000001 00000000 00000001 00000000
942 That is a range starting at 0 of 0x80000000 bytes and a range
943 starting at 0x100000000 and of 0x100000000 bytes. You can see
944 that there is no memory covering the IO hole between 2Gb and
945 4Gb. Some vendors prefer splitting those ranges into smaller
946 segments, but the kernel doesn't care.
950 This node is a bit "special". Normally, that's where open firmware
951 puts some variable environment information, like the arguments, or
952 the default input/output devices.
954 This specification makes a few of these mandatory, but also defines
955 some linux-specific properties that would be normally constructed by
956 the prom_init() trampoline when booting with an OF client interface,
957 but that you have to provide yourself when using the flattened format.
959 Recommended properties:
961 - bootargs : This zero-terminated string is passed as the kernel
963 - linux,stdout-path : This is the full path to your standard
964 console device if any. Typically, if you have serial devices on
965 your board, you may want to put the full path to the one set as
966 the default console in the firmware here, for the kernel to pick
967 it up as its own default console. If you look at the function
968 set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
969 that the kernel tries to find out the default console and has
970 knowledge of various types like 8250 serial ports. You may want
971 to extend this function to add your own.
973 Note that u-boot creates and fills in the chosen node for platforms
976 (Note: a practice that is now obsolete was to include a property
977 under /chosen called interrupt-controller which had a phandle value
978 that pointed to the main interrupt controller)
980 f) the /soc<SOCname> node
982 This node is used to represent a system-on-a-chip (SOC) and must be
983 present if the processor is a SOC. The top-level soc node contains
984 information that is global to all devices on the SOC. The node name
985 should contain a unit address for the SOC, which is the base address
986 of the memory-mapped register set for the SOC. The name of an soc
987 node should start with "soc", and the remainder of the name should
988 represent the part number for the soc. For example, the MPC8540's
989 soc node would be called "soc8540".
993 - device_type : Should be "soc"
994 - ranges : Should be defined as specified in 1) to describe the
995 translation of SOC addresses for memory mapped SOC registers.
996 - bus-frequency: Contains the bus frequency for the SOC node.
997 Typically, the value of this field is filled in by the boot
1001 Recommended properties:
1003 - reg : This property defines the address and size of the
1004 memory-mapped registers that are used for the SOC node itself.
1005 It does not include the child device registers - these will be
1006 defined inside each child node. The address specified in the
1007 "reg" property should match the unit address of the SOC node.
1008 - #address-cells : Address representation for "soc" devices. The
1009 format of this field may vary depending on whether or not the
1010 device registers are memory mapped. For memory mapped
1011 registers, this field represents the number of cells needed to
1012 represent the address of the registers. For SOCs that do not
1013 use MMIO, a special address format should be defined that
1014 contains enough cells to represent the required information.
1015 See 1) above for more details on defining #address-cells.
1016 - #size-cells : Size representation for "soc" devices
1017 - #interrupt-cells : Defines the width of cells used to represent
1018 interrupts. Typically this value is <2>, which includes a
1019 32-bit number that represents the interrupt number, and a
1020 32-bit number that represents the interrupt sense and level.
1021 This field is only needed if the SOC contains an interrupt
1024 The SOC node may contain child nodes for each SOC device that the
1025 platform uses. Nodes should not be created for devices which exist
1026 on the SOC but are not used by a particular platform. See chapter VI
1027 for more information on how to specify devices that are part of a SOC.
1029 Example SOC node for the MPC8540:
1032 #address-cells = <1>;
1034 #interrupt-cells = <2>;
1035 device_type = "soc";
1036 ranges = <00000000 e0000000 00100000>
1037 reg = <e0000000 00003000>;
1038 bus-frequency = <0>;
1043 IV - "dtc", the device tree compiler
1044 ====================================
1047 dtc source code can be found at
1048 <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
1050 WARNING: This version is still in early development stage; the
1051 resulting device-tree "blobs" have not yet been validated with the
1052 kernel. The current generated bloc lacks a useful reserve map (it will
1053 be fixed to generate an empty one, it's up to the bootloader to fill
1054 it up) among others. The error handling needs work, bugs are lurking,
1057 dtc basically takes a device-tree in a given format and outputs a
1058 device-tree in another format. The currently supported formats are:
1063 - "dtb": "blob" format, that is a flattened device-tree block
1065 header all in a binary blob.
1066 - "dts": "source" format. This is a text file containing a
1067 "source" for a device-tree. The format is defined later in this
1069 - "fs" format. This is a representation equivalent to the
1070 output of /proc/device-tree, that is nodes are directories and
1071 properties are files
1076 - "dtb": "blob" format
1077 - "dts": "source" format
1078 - "asm": assembly language file. This is a file that can be
1079 sourced by gas to generate a device-tree "blob". That file can
1080 then simply be added to your Makefile. Additionally, the
1081 assembly file exports some symbols that can be used.
1084 The syntax of the dtc tool is
1086 dtc [-I <input-format>] [-O <output-format>]
1087 [-o output-filename] [-V output_version] input_filename
1090 The "output_version" defines what version of the "blob" format will be
1091 generated. Supported versions are 1,2,3 and 16. The default is
1092 currently version 3 but that may change in the future to version 16.
1094 Additionally, dtc performs various sanity checks on the tree, like the
1095 uniqueness of linux, phandle properties, validity of strings, etc...
1097 The format of the .dts "source" file is "C" like, supports C and C++
1103 The above is the "device-tree" definition. It's the only statement
1104 supported currently at the toplevel.
1107 property1 = "string_value"; /* define a property containing a 0
1111 property2 = <1234abcd>; /* define a property containing a
1112 * numerical 32-bit value (hexadecimal)
1115 property3 = <12345678 12345678 deadbeef>;
1116 /* define a property containing 3
1117 * numerical 32-bit values (cells) in
1120 property4 = [0a 0b 0c 0d de ea ad be ef];
1121 /* define a property whose content is
1122 * an arbitrary array of bytes
1125 childnode@addresss { /* define a child node named "childnode"
1126 * whose unit name is "childnode at
1130 childprop = "hello\n"; /* define a property "childprop" of
1131 * childnode (in this case, a string)
1136 Nodes can contain other nodes etc... thus defining the hierarchical
1137 structure of the tree.
1139 Strings support common escape sequences from C: "\n", "\t", "\r",
1140 "\(octal value)", "\x(hex value)".
1142 It is also suggested that you pipe your source file through cpp (gcc
1143 preprocessor) so you can use #include's, #define for constants, etc...
1145 Finally, various options are planned but not yet implemented, like
1146 automatic generation of phandles, labels (exported to the asm file so
1147 you can point to a property content and change it easily from whatever
1148 you link the device-tree with), label or path instead of numeric value
1149 in some cells to "point" to a node (replaced by a phandle at compile
1150 time), export of reserve map address to the asm file, ability to
1151 specify reserve map content at compile time, etc...
1153 We may provide a .h include file with common definitions of that
1154 proves useful for some properties (like building PCI properties or
1155 interrupt maps) though it may be better to add a notion of struct
1156 definitions to the compiler...
1159 V - Recommendations for a bootloader
1160 ====================================
1163 Here are some various ideas/recommendations that have been proposed
1164 while all this has been defined and implemented.
1166 - The bootloader may want to be able to use the device-tree itself
1167 and may want to manipulate it (to add/edit some properties,
1168 like physical memory size or kernel arguments). At this point, 2
1169 choices can be made. Either the bootloader works directly on the
1170 flattened format, or the bootloader has its own internal tree
1171 representation with pointers (similar to the kernel one) and
1172 re-flattens the tree when booting the kernel. The former is a bit
1173 more difficult to edit/modify, the later requires probably a bit
1174 more code to handle the tree structure. Note that the structure
1175 format has been designed so it's relatively easy to "insert"
1176 properties or nodes or delete them by just memmoving things
1177 around. It contains no internal offsets or pointers for this
1180 - An example of code for iterating nodes & retrieving properties
1181 directly from the flattened tree format can be found in the kernel
1182 file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
1183 its usage in early_init_devtree(), and the corresponding various
1184 early_init_dt_scan_*() callbacks. That code can be re-used in a
1185 GPL bootloader, and as the author of that code, I would be happy
1186 to discuss possible free licensing to any vendor who wishes to
1187 integrate all or part of this code into a non-GPL bootloader.
1191 VI - System-on-a-chip devices and nodes
1192 =======================================
1194 Many companies are now starting to develop system-on-a-chip
1195 processors, where the processor core (CPU) and many peripheral devices
1196 exist on a single piece of silicon. For these SOCs, an SOC node
1197 should be used that defines child nodes for the devices that make
1198 up the SOC. While platforms are not required to use this model in
1199 order to boot the kernel, it is highly encouraged that all SOC
1200 implementations define as complete a flat-device-tree as possible to
1201 describe the devices on the SOC. This will allow for the
1202 genericization of much of the kernel code.
1205 1) Defining child nodes of an SOC
1206 ---------------------------------
1208 Each device that is part of an SOC may have its own node entry inside
1209 the SOC node. For each device that is included in the SOC, the unit
1210 address property represents the address offset for this device's
1211 memory-mapped registers in the parent's address space. The parent's
1212 address space is defined by the "ranges" property in the top-level soc
1213 node. The "reg" property for each node that exists directly under the
1214 SOC node should contain the address mapping from the child address space
1215 to the parent SOC address space and the size of the device's
1216 memory-mapped register file.
1218 For many devices that may exist inside an SOC, there are predefined
1219 specifications for the format of the device tree node. All SOC child
1220 nodes should follow these specifications, except where noted in this
1223 See appendix A for an example partial SOC node definition for the
1227 2) Representing devices without a current OF specification
1228 ----------------------------------------------------------
1230 Currently, there are many devices on SOCs that do not have a standard
1231 representation pre-defined as part of the open firmware
1232 specifications, mainly because the boards that contain these SOCs are
1233 not currently booted using open firmware. This section contains
1234 descriptions for the SOC devices for which new nodes have been
1235 defined; this list will expand as more and more SOC-containing
1236 platforms are moved over to use the flattened-device-tree model.
1240 Required properties:
1242 - device_type : Should be "ethernet-phy"
1243 - interrupts : <a b> where a is the interrupt number and b is a
1244 field that represents an encoding of the sense and level
1245 information for the interrupt. This should be encoded based on
1246 the information in section 2) depending on the type of interrupt
1247 controller you have.
1248 - interrupt-parent : the phandle for the interrupt controller that
1249 services interrupts for this device.
1250 - reg : The ID number for the phy, usually a small integer
1251 - linux,phandle : phandle for this node; likely referenced by an
1252 ethernet controller node.
1258 linux,phandle = <2452000>
1259 interrupt-parent = <40000>;
1260 interrupts = <35 1>;
1262 device_type = "ethernet-phy";
1266 b) Interrupt controllers
1268 Some SOC devices contain interrupt controllers that are different
1269 from the standard Open PIC specification. The SOC device nodes for
1270 these types of controllers should be specified just like a standard
1271 OpenPIC controller. Sense and level information should be encoded
1272 as specified in section 2) of this chapter for each device that
1273 specifies an interrupt.
1278 linux,phandle = <40000>;
1279 interrupt-controller;
1280 #address-cells = <0>;
1281 reg = <40000 40000>;
1282 compatible = "chrp,open-pic";
1283 device_type = "open-pic";
1286 c) CFI or JEDEC memory-mapped NOR flash
1288 Flash chips (Memory Technology Devices) are often used for solid state
1289 file systems on embedded devices.
1291 - compatible : should contain the specific model of flash chip(s)
1292 used, if known, followed by either "cfi-flash" or "jedec-flash"
1293 - reg : Address range of the flash chip
1294 - bank-width : Width (in bytes) of the flash bank. Equal to the
1295 device width times the number of interleaved chips.
1296 - device-width : (optional) Width of a single flash chip. If
1297 omitted, assumed to be equal to 'bank-width'.
1298 - #address-cells, #size-cells : Must be present if the flash has
1299 sub-nodes representing partitions (see below). In this case
1300 both #address-cells and #size-cells must be equal to 1.
1302 For JEDEC compatible devices, the following additional properties
1305 - vendor-id : Contains the flash chip's vendor id (1 byte).
1306 - device-id : Contains the flash chip's device id (1 byte).
1308 In addition to the information on the flash bank itself, the
1309 device tree may optionally contain additional information
1310 describing partitions of the flash address space. This can be
1311 used on platforms which have strong conventions about which
1312 portions of the flash are used for what purposes, but which don't
1313 use an on-flash partition table such as RedBoot.
1315 Each partition is represented as a sub-node of the flash device.
1316 Each node's name represents the name of the corresponding
1317 partition of the flash device.
1320 - reg : The partition's offset and size within the flash bank.
1321 - label : (optional) The label / name for this flash partition.
1322 If omitted, the label is taken from the node name (excluding
1324 - read-only : (optional) This parameter, if present, is a hint to
1325 Linux that this flash partition should only be mounted
1326 read-only. This is usually used for flash partitions
1327 containing early-boot firmware images or data which should not
1333 compatible = "amd,am29lv128ml", "cfi-flash";
1334 reg = <ff000000 01000000>;
1337 #address-cells = <1>;
1345 reg = <f80000 80000>;
1350 d) 4xx/Axon EMAC ethernet nodes
1352 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1353 the Axon bridge. To operate this needs to interact with a ths
1354 special McMAL DMA controller, and sometimes an RGMII or ZMII
1355 interface. In addition to the nodes and properties described
1356 below, the node for the OPB bus on which the EMAC sits must have a
1357 correct clock-frequency property.
1359 i) The EMAC node itself
1361 Required properties:
1362 - device_type : "network"
1364 - compatible : compatible list, contains 2 entries, first is
1365 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1366 405gp, Axon) and second is either "ibm,emac" or
1367 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1369 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1370 - interrupt-parent : optional, if needed for interrupt mapping
1371 - reg : <registers mapping>
1372 - local-mac-address : 6 bytes, MAC address
1373 - mal-device : phandle of the associated McMAL node
1374 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1376 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1378 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1379 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1381 - max-frame-size : 1 cell, maximum frame size supported in bytes
1382 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1385 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1388 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1390 For Axon, 0x00000010
1391 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1393 For Axon, 0x00000100 (I think ...)
1394 - phy-mode : string, mode of operations of the PHY interface.
1395 Supported values are: "mii", "rmii", "smii", "rgmii",
1396 "tbi", "gmii", rtbi", "sgmii".
1397 For Axon on CAB, it is "rgmii"
1398 - mdio-device : 1 cell, required iff using shared MDIO registers
1399 (440EP). phandle of the EMAC to use to drive the
1400 MDIO lines for the PHY used by this EMAC.
1401 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1402 the ZMII device node
1403 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1404 channel or 0xffffffff if ZMII is only used for MDIO.
1405 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1406 of the RGMII device node.
1407 For Axon: phandle of plb5/plb4/opb/rgmii
1408 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1409 RGMII channel is used by this EMAC.
1410 Fox Axon: present, whatever value is appropriate for each
1411 EMAC, that is the content of the current (bogus) "phy-port"
1414 Optional properties:
1415 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1416 a search is performed.
1417 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1418 for, used if phy-address is absent. bit 0x00000001 is
1420 For Axon it can be absent, thouugh my current driver
1421 doesn't handle phy-address yet so for now, keep
1423 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1424 operations (if absent the value is the same as
1425 rx-fifo-size). For Axon, either absent or 2048.
1426 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1427 operations (if absent the value is the same as
1428 tx-fifo-size). For Axon, either absent or 2048.
1429 - tah-device : 1 cell, optional. If connected to a TAH engine for
1430 offload, phandle of the TAH device node.
1431 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1436 EMAC0: ethernet@40000800 {
1437 device_type = "network";
1438 compatible = "ibm,emac-440gp", "ibm,emac";
1439 interrupt-parent = <&UIC1>;
1440 interrupts = <1c 4 1d 4>;
1441 reg = <40000800 70>;
1442 local-mac-address = [00 04 AC E3 1B 1E];
1443 mal-device = <&MAL0>;
1444 mal-tx-channel = <0 1>;
1445 mal-rx-channel = <0>;
1447 max-frame-size = <5dc>;
1448 rx-fifo-size = <1000>;
1449 tx-fifo-size = <800>;
1451 phy-map = <00000001>;
1452 zmii-device = <&ZMII0>;
1458 Required properties:
1459 - device_type : "dma-controller"
1460 - compatible : compatible list, containing 2 entries, first is
1461 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1462 emac) and the second is either "ibm,mcmal" or
1464 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1465 - interrupts : <interrupt mapping for the MAL interrupts sources:
1466 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1467 For Axon: This is _different_ from the current
1468 firmware. We use the "delayed" interrupts for txeob
1469 and rxeob. Thus we end up with mapping those 5 MPIC
1470 interrupts, all level positive sensitive: 10, 11, 32,
1472 - dcr-reg : < DCR registers range >
1473 - dcr-parent : if needed for dcr-reg
1474 - num-tx-chans : 1 cell, number of Tx channels
1475 - num-rx-chans : 1 cell, number of Rx channels
1479 Required properties:
1480 - compatible : compatible list, containing 2 entries, first is
1481 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1482 EMAC) and the second is "ibm,zmii".
1483 For Axon, there is no ZMII node.
1484 - reg : <registers mapping>
1488 Required properties:
1489 - compatible : compatible list, containing 2 entries, first is
1490 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1491 EMAC) and the second is "ibm,rgmii".
1492 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1493 - reg : <registers mapping>
1494 - revision : as provided by the RGMII new version register if
1496 For Axon: 0x0000012a
1500 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
1501 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
1502 of standard device types (network, serial, etc.) and miscellanious
1503 devices (gpio, LCD, spi, etc). Also, since these devices are
1504 implemented within the fpga fabric every instance of the device can be
1505 synthesised with different options that change the behaviour.
1507 Each IP-core has a set of parameters which the FPGA designer can use to
1508 control how the core is synthesized. Historically, the EDK tool would
1509 extract the device parameters relevant to device drivers and copy them
1510 into an 'xparameters.h' in the form of #define symbols. This tells the
1511 device drivers how the IP cores are configured, but it requres the kernel
1512 to be recompiled every time the FPGA bitstream is resynthesized.
1514 The new approach is to export the parameters into the device tree and
1515 generate a new device tree each time the FPGA bitstream changes. The
1516 parameters which used to be exported as #defines will now become
1517 properties of the device node. In general, device nodes for IP-cores
1518 will take the following form:
1520 (name): (generic-name)@(base-address) {
1521 compatible = "xlnx,(ip-core-name)-(HW_VER)"
1522 [, (list of compatible devices), ...];
1523 reg = <(baseaddr) (size)>;
1524 interrupt-parent = <&interrupt-controller-phandle>;
1525 interrupts = < ... >;
1526 xlnx,(parameter1) = "(string-value)";
1527 xlnx,(parameter2) = <(int-value)>;
1530 (generic-name): an open firmware-style name that describes the
1531 generic class of device. Preferably, this is one word, such
1532 as 'serial' or 'ethernet'.
1533 (ip-core-name): the name of the ip block (given after the BEGIN
1534 directive in system.mhs). Should be in lowercase
1535 and all underscores '_' converted to dashes '-'.
1536 (name): is derived from the "PARAMETER INSTANCE" value.
1537 (parameter#): C_* parameters from system.mhs. The C_ prefix is
1538 dropped from the parameter name, the name is converted
1539 to lowercase and all underscore '_' characters are
1540 converted to dashes '-'.
1541 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
1542 (HW_VER): from the HW_VER parameter.
1543 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
1545 Typically, the compatible list will include the exact IP core version
1546 followed by an older IP core version which implements the same
1547 interface or any other device with the same interface.
1549 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
1551 For example, the following block from system.mhs:
1554 PARAMETER INSTANCE = opb_uartlite_0
1555 PARAMETER HW_VER = 1.00.b
1556 PARAMETER C_BAUDRATE = 115200
1557 PARAMETER C_DATA_BITS = 8
1558 PARAMETER C_ODD_PARITY = 0
1559 PARAMETER C_USE_PARITY = 0
1560 PARAMETER C_CLK_FREQ = 50000000
1561 PARAMETER C_BASEADDR = 0xEC100000
1562 PARAMETER C_HIGHADDR = 0xEC10FFFF
1563 BUS_INTERFACE SOPB = opb_7
1564 PORT OPB_Clk = CLK_50MHz
1565 PORT Interrupt = opb_uartlite_0_Interrupt
1566 PORT RX = opb_uartlite_0_RX
1567 PORT TX = opb_uartlite_0_TX
1568 PORT OPB_Rst = sys_bus_reset_0
1571 becomes the following device tree node:
1573 opb_uartlite_0: serial@ec100000 {
1574 device_type = "serial";
1575 compatible = "xlnx,opb-uartlite-1.00.b";
1576 reg = <ec100000 10000>;
1577 interrupt-parent = <&opb_intc_0>;
1578 interrupts = <1 0>; // got this from the opb_intc parameters
1579 current-speed = <d#115200>; // standard serial device prop
1580 clock-frequency = <d#50000000>; // standard serial device prop
1581 xlnx,data-bits = <8>;
1582 xlnx,odd-parity = <0>;
1583 xlnx,use-parity = <0>;
1586 Some IP cores actually implement 2 or more logical devices. In
1587 this case, the device should still describe the whole IP core with
1588 a single node and add a child node for each logical device. The
1589 ranges property can be used to translate from parent IP-core to the
1590 registers of each device. In addition, the parent node should be
1591 compatible with the bus type 'xlnx,compound', and should contain
1592 #address-cells and #size-cells, as with any other bus. (Note: this
1593 makes the assumption that both logical devices have the same bus
1594 binding. If this is not true, then separate nodes should be used
1595 for each logical device). The 'cell-index' property can be used to
1596 enumerate logical devices within an IP core. For example, the
1597 following is the system.mhs entry for the dual ps2 controller found
1598 on the ml403 reference design.
1600 BEGIN opb_ps2_dual_ref
1601 PARAMETER INSTANCE = opb_ps2_dual_ref_0
1602 PARAMETER HW_VER = 1.00.a
1603 PARAMETER C_BASEADDR = 0xA9000000
1604 PARAMETER C_HIGHADDR = 0xA9001FFF
1605 BUS_INTERFACE SOPB = opb_v20_0
1606 PORT Sys_Intr1 = ps2_1_intr
1607 PORT Sys_Intr2 = ps2_2_intr
1608 PORT Clkin1 = ps2_clk_rx_1
1609 PORT Clkin2 = ps2_clk_rx_2
1610 PORT Clkpd1 = ps2_clk_tx_1
1611 PORT Clkpd2 = ps2_clk_tx_2
1612 PORT Rx1 = ps2_d_rx_1
1613 PORT Rx2 = ps2_d_rx_2
1614 PORT Txpd1 = ps2_d_tx_1
1615 PORT Txpd2 = ps2_d_tx_2
1618 It would result in the following device tree nodes:
1620 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
1621 #address-cells = <1>;
1623 compatible = "xlnx,compound";
1624 ranges = <0 a9000000 2000>;
1625 // If this device had extra parameters, then they would
1628 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1630 interrupt-parent = <&opb_intc_0>;
1635 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1637 interrupt-parent = <&opb_intc_0>;
1643 Also, the system.mhs file defines bus attachments from the processor
1644 to the devices. The device tree structure should reflect the bus
1645 attachments. Again an example; this system.mhs fragment:
1647 BEGIN ppc405_virtex4
1648 PARAMETER INSTANCE = ppc405_0
1649 PARAMETER HW_VER = 1.01.a
1650 BUS_INTERFACE DPLB = plb_v34_0
1651 BUS_INTERFACE IPLB = plb_v34_0
1655 PARAMETER INSTANCE = opb_intc_0
1656 PARAMETER HW_VER = 1.00.c
1657 PARAMETER C_BASEADDR = 0xD1000FC0
1658 PARAMETER C_HIGHADDR = 0xD1000FDF
1659 BUS_INTERFACE SOPB = opb_v20_0
1663 PARAMETER INSTANCE = opb_uart16550_0
1664 PARAMETER HW_VER = 1.00.d
1665 PARAMETER C_BASEADDR = 0xa0000000
1666 PARAMETER C_HIGHADDR = 0xa0001FFF
1667 BUS_INTERFACE SOPB = opb_v20_0
1671 PARAMETER INSTANCE = plb_v34_0
1672 PARAMETER HW_VER = 1.02.a
1675 BEGIN plb_bram_if_cntlr
1676 PARAMETER INSTANCE = plb_bram_if_cntlr_0
1677 PARAMETER HW_VER = 1.00.b
1678 PARAMETER C_BASEADDR = 0xFFFF0000
1679 PARAMETER C_HIGHADDR = 0xFFFFFFFF
1680 BUS_INTERFACE SPLB = plb_v34_0
1683 BEGIN plb2opb_bridge
1684 PARAMETER INSTANCE = plb2opb_bridge_0
1685 PARAMETER HW_VER = 1.01.a
1686 PARAMETER C_RNG0_BASEADDR = 0x20000000
1687 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
1688 PARAMETER C_RNG1_BASEADDR = 0x60000000
1689 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
1690 PARAMETER C_RNG2_BASEADDR = 0x80000000
1691 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
1692 PARAMETER C_RNG3_BASEADDR = 0xC0000000
1693 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
1694 BUS_INTERFACE SPLB = plb_v34_0
1695 BUS_INTERFACE MOPB = opb_v20_0
1698 Gives this device tree (some properties removed for clarity):
1701 #address-cells = <1>;
1703 compatible = "xlnx,plb-v34-1.02.a";
1704 device_type = "ibm,plb";
1705 ranges; // 1:1 translation
1707 plb_bram_if_cntrl_0: bram@ffff0000 {
1708 reg = <ffff0000 10000>;
1712 #address-cells = <1>;
1714 ranges = <20000000 20000000 20000000
1715 60000000 60000000 20000000
1716 80000000 80000000 40000000
1717 c0000000 c0000000 20000000>;
1719 opb_uart16550_0: serial@a0000000 {
1720 reg = <a00000000 2000>;
1723 opb_intc_0: interrupt-controller@d1000fc0 {
1724 reg = <d1000fc0 20>;
1729 That covers the general approach to binding xilinx IP cores into the
1730 device tree. The following are bindings for specific devices:
1732 i) Xilinx ML300 Framebuffer
1734 Simple framebuffer device from the ML300 reference design (also on the
1735 ML403 reference design as well as others).
1737 Optional properties:
1738 - resolution = <xres yres> : pixel resolution of framebuffer. Some
1739 implementations use a different resolution.
1740 Default is <d#640 d#480>
1741 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
1742 Default is <d#1024 d#480>.
1743 - rotate-display (empty) : rotate display 180 degrees.
1745 ii) Xilinx SystemACE
1747 The Xilinx SystemACE device is used to program FPGAs from an FPGA
1748 bitstream stored on a CF card. It can also be used as a generic CF
1751 Optional properties:
1752 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
1754 iii) Xilinx EMAC and Xilinx TEMAC
1756 Xilinx Ethernet devices. In addition to general xilinx properties
1757 listed above, nodes for these devices should include a phy-handle
1758 property, and may include other common network device properties
1759 like local-mac-address.
1763 Xilinx uartlite devices are simple fixed speed serial ports.
1766 - current-speed : Baud rate of uartlite
1770 Xilinx hwicap devices provide access to the configuration logic
1771 of the FPGA through the Internal Configuration Access Port
1772 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
1773 readback of the configuration information, and some control over
1774 'warm boots' of the FPGA fabric.
1776 Required properties:
1777 - xlnx,family : The family of the FPGA, necessary since the
1778 capabilities of the underlying ICAP hardware
1779 differ between different families. May be
1780 'virtex2p', 'virtex4', or 'virtex5'.
1782 vi) Xilinx Uart 16550
1784 Xilinx UART 16550 devices are very similar to the NS16550 but with
1785 different register spacing and an offset from the base address.
1788 - clock-frequency : Frequency of the clock input
1789 - reg-offset : A value of 3 is required
1790 - reg-shift : A value of 2 is required
1792 f) USB EHCI controllers
1794 Required properties:
1795 - compatible : should be "usb-ehci".
1796 - reg : should contain at least address and length of the standard EHCI
1797 register set for the device. Optional platform-dependent registers
1798 (debug-port or other) can be also specified here, but only after
1799 definition of standard EHCI registers.
1800 - interrupts : one EHCI interrupt should be described here.
1801 If device registers are implemented in big endian mode, the device
1802 node should have "big-endian-regs" property.
1803 If controller implementation operates with big endian descriptors,
1804 "big-endian-desc" property should be specified.
1805 If both big endian registers and descriptors are used by the controller
1806 implementation, "big-endian" property can be specified instead of having
1807 both "big-endian-regs" and "big-endian-desc".
1809 Example (Sequoia 440EPx):
1811 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
1812 interrupt-parent = <&UIC0>;
1813 interrupts = <1a 4>;
1814 reg = <0 e0000300 90 0 e0000390 70>;
1818 VII - Marvell Discovery mv64[345]6x System Controller chips
1819 ===========================================================
1821 The Marvell mv64[345]60 series of system controller chips contain
1822 many of the peripherals needed to implement a complete computer
1823 system. In this section, we define device tree nodes to describe
1824 the system controller chip itself and each of the peripherals
1825 which it contains. Compatible string values for each node are
1826 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
1828 1) The /system-controller node
1830 This node is used to represent the system-controller and must be
1831 present when the system uses a system contller chip. The top-level
1832 system-controller node contains information that is global to all
1833 devices within the system controller chip. The node name begins
1834 with "system-controller" followed by the unit address, which is
1835 the base address of the memory-mapped register set for the system
1838 Required properties:
1840 - ranges : Describes the translation of system controller addresses
1841 for memory mapped registers.
1842 - clock-frequency: Contains the main clock frequency for the system
1844 - reg : This property defines the address and size of the
1845 memory-mapped registers contained within the system controller
1846 chip. The address specified in the "reg" property should match
1847 the unit address of the system-controller node.
1848 - #address-cells : Address representation for system controller
1849 devices. This field represents the number of cells needed to
1850 represent the address of the memory-mapped registers of devices
1851 within the system controller chip.
1852 - #size-cells : Size representation for for the memory-mapped
1853 registers within the system controller chip.
1854 - #interrupt-cells : Defines the width of cells used to represent
1857 Optional properties:
1859 - model : The specific model of the system controller chip. Such
1860 as, "mv64360", "mv64460", or "mv64560".
1861 - compatible : A string identifying the compatibility identifiers
1862 of the system controller chip.
1864 The system-controller node contains child nodes for each system
1865 controller device that the platform uses. Nodes should not be created
1866 for devices which exist on the system controller chip but are not used
1868 Example Marvell Discovery mv64360 system-controller node:
1870 system-controller@f1000000 { /* Marvell Discovery mv64360 */
1871 #address-cells = <1>;
1873 model = "mv64360"; /* Default */
1874 compatible = "marvell,mv64360";
1875 clock-frequency = <133333333>;
1876 reg = <0xf1000000 0x10000>;
1877 virtual-reg = <0xf1000000>;
1878 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
1879 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
1880 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
1881 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
1882 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
1884 [ child node definitions... ]
1887 2) Child nodes of /system-controller
1889 a) Marvell Discovery MDIO bus
1891 The MDIO is a bus to which the PHY devices are connected. For each
1892 device that exists on this bus, a child node should be created. See
1893 the definition of the PHY node below for an example of how to define
1896 Required properties:
1897 - #address-cells : Should be <1>
1898 - #size-cells : Should be <0>
1899 - device_type : Should be "mdio"
1900 - compatible : Should be "marvell,mv64360-mdio"
1905 #address-cells = <1>;
1907 device_type = "mdio";
1908 compatible = "marvell,mv64360-mdio";
1916 b) Marvell Discovery ethernet controller
1918 The Discover ethernet controller is described with two levels
1919 of nodes. The first level describes an ethernet silicon block
1920 and the second level describes up to 3 ethernet nodes within
1921 that block. The reason for the multiple levels is that the
1922 registers for the node are interleaved within a single set
1923 of registers. The "ethernet-block" level describes the
1924 shared register set, and the "ethernet" nodes describe ethernet
1925 port-specific properties.
1929 Required properties:
1930 - #address-cells : <1>
1932 - compatible : "marvell,mv64360-eth-block"
1933 - reg : Offset and length of the register set for this block
1935 Example Discovery Ethernet block node:
1936 ethernet-block@2000 {
1937 #address-cells = <1>;
1939 compatible = "marvell,mv64360-eth-block";
1940 reg = <0x2000 0x2000>;
1948 Required properties:
1949 - device_type : Should be "network".
1950 - compatible : Should be "marvell,mv64360-eth".
1951 - reg : Should be <0>, <1>, or <2>, according to which registers
1952 within the silicon block the device uses.
1953 - interrupts : <a> where a is the interrupt number for the port.
1954 - interrupt-parent : the phandle for the interrupt controller
1955 that services interrupts for this device.
1956 - phy : the phandle for the PHY connected to this ethernet
1958 - local-mac-address : 6 bytes, MAC address
1960 Example Discovery Ethernet port node:
1962 device_type = "network";
1963 compatible = "marvell,mv64360-eth";
1966 interrupt-parent = <&PIC>;
1968 local-mac-address = [ 00 00 00 00 00 00 ];
1973 c) Marvell Discovery PHY nodes
1975 Required properties:
1976 - device_type : Should be "ethernet-phy"
1977 - interrupts : <a> where a is the interrupt number for this phy.
1978 - interrupt-parent : the phandle for the interrupt controller that
1979 services interrupts for this device.
1980 - reg : The ID number for the phy, usually a small integer
1982 Example Discovery PHY node:
1984 device_type = "ethernet-phy";
1985 compatible = "broadcom,bcm5421";
1986 interrupts = <76>; /* GPP 12 */
1987 interrupt-parent = <&PIC>;
1992 d) Marvell Discovery SDMA nodes
1994 Represent DMA hardware associated with the MPSC (multiprotocol
1995 serial controllers).
1997 Required properties:
1998 - compatible : "marvell,mv64360-sdma"
1999 - reg : Offset and length of the register set for this device
2000 - interrupts : <a> where a is the interrupt number for the DMA
2002 - interrupt-parent : the phandle for the interrupt controller
2003 that services interrupts for this device.
2005 Example Discovery SDMA node:
2007 compatible = "marvell,mv64360-sdma";
2008 reg = <0x4000 0xc18>;
2009 virtual-reg = <0xf1004000>;
2011 interrupt-parent = <&PIC>;
2015 e) Marvell Discovery BRG nodes
2017 Represent baud rate generator hardware associated with the MPSC
2018 (multiprotocol serial controllers).
2020 Required properties:
2021 - compatible : "marvell,mv64360-brg"
2022 - reg : Offset and length of the register set for this device
2023 - clock-src : A value from 0 to 15 which selects the clock
2024 source for the baud rate generator. This value corresponds
2025 to the CLKS value in the BRGx configuration register. See
2026 the mv64x60 User's Manual.
2027 - clock-frequence : The frequency (in Hz) of the baud rate
2028 generator's input clock.
2029 - current-speed : The current speed setting (presumably by
2030 firmware) of the baud rate generator.
2032 Example Discovery BRG node:
2034 compatible = "marvell,mv64360-brg";
2037 clock-frequency = <133333333>;
2038 current-speed = <9600>;
2042 f) Marvell Discovery CUNIT nodes
2044 Represent the Serial Communications Unit device hardware.
2046 Required properties:
2047 - reg : Offset and length of the register set for this device
2049 Example Discovery CUNIT node:
2051 reg = <0xf200 0x200>;
2055 g) Marvell Discovery MPSCROUTING nodes
2057 Represent the Discovery's MPSC routing hardware
2059 Required properties:
2060 - reg : Offset and length of the register set for this device
2062 Example Discovery CUNIT node:
2068 h) Marvell Discovery MPSCINTR nodes
2070 Represent the Discovery's MPSC DMA interrupt hardware registers
2071 (SDMA cause and mask registers).
2073 Required properties:
2074 - reg : Offset and length of the register set for this device
2076 Example Discovery MPSCINTR node:
2078 reg = <0xb800 0x100>;
2082 i) Marvell Discovery MPSC nodes
2084 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
2087 Required properties:
2088 - device_type : "serial"
2089 - compatible : "marvell,mv64360-mpsc"
2090 - reg : Offset and length of the register set for this device
2091 - sdma : the phandle for the SDMA node used by this port
2092 - brg : the phandle for the BRG node used by this port
2093 - cunit : the phandle for the CUNIT node used by this port
2094 - mpscrouting : the phandle for the MPSCROUTING node used by this port
2095 - mpscintr : the phandle for the MPSCINTR node used by this port
2096 - cell-index : the hardware index of this cell in the MPSC core
2097 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
2099 - interrupts : <a> where a is the interrupt number for the MPSC.
2100 - interrupt-parent : the phandle for the interrupt controller
2101 that services interrupts for this device.
2103 Example Discovery MPSCINTR node:
2105 device_type = "serial";
2106 compatible = "marvell,mv64360-mpsc";
2107 reg = <0x8000 0x38>;
2108 virtual-reg = <0xf1008000>;
2112 mpscrouting = <&MPSCROUTING>;
2113 mpscintr = <&MPSCINTR>;
2117 interrupt-parent = <&PIC>;
2121 j) Marvell Discovery Watch Dog Timer nodes
2123 Represent the Discovery's watchdog timer hardware
2125 Required properties:
2126 - compatible : "marvell,mv64360-wdt"
2127 - reg : Offset and length of the register set for this device
2129 Example Discovery Watch Dog Timer node:
2131 compatible = "marvell,mv64360-wdt";
2136 k) Marvell Discovery I2C nodes
2138 Represent the Discovery's I2C hardware
2140 Required properties:
2141 - device_type : "i2c"
2142 - compatible : "marvell,mv64360-i2c"
2143 - reg : Offset and length of the register set for this device
2144 - interrupts : <a> where a is the interrupt number for the I2C.
2145 - interrupt-parent : the phandle for the interrupt controller
2146 that services interrupts for this device.
2148 Example Discovery I2C node:
2149 compatible = "marvell,mv64360-i2c";
2150 reg = <0xc000 0x20>;
2151 virtual-reg = <0xf100c000>;
2153 interrupt-parent = <&PIC>;
2157 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
2159 Represent the Discovery's PIC hardware
2161 Required properties:
2162 - #interrupt-cells : <1>
2163 - #address-cells : <0>
2164 - compatible : "marvell,mv64360-pic"
2165 - reg : Offset and length of the register set for this device
2166 - interrupt-controller
2168 Example Discovery PIC node:
2170 #interrupt-cells = <1>;
2171 #address-cells = <0>;
2172 compatible = "marvell,mv64360-pic";
2174 interrupt-controller;
2178 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
2180 Represent the Discovery's MPP hardware
2182 Required properties:
2183 - compatible : "marvell,mv64360-mpp"
2184 - reg : Offset and length of the register set for this device
2186 Example Discovery MPP node:
2188 compatible = "marvell,mv64360-mpp";
2189 reg = <0xf000 0x10>;
2193 n) Marvell Discovery GPP (General Purpose Pins) nodes
2195 Represent the Discovery's GPP hardware
2197 Required properties:
2198 - compatible : "marvell,mv64360-gpp"
2199 - reg : Offset and length of the register set for this device
2201 Example Discovery GPP node:
2203 compatible = "marvell,mv64360-gpp";
2204 reg = <0xf100 0x20>;
2208 o) Marvell Discovery PCI host bridge node
2210 Represents the Discovery's PCI host bridge device. The properties
2211 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
2212 1275-1994. A typical value for the compatible property is
2213 "marvell,mv64360-pci".
2215 Example Discovery PCI host bridge node
2217 #address-cells = <3>;
2219 #interrupt-cells = <1>;
2220 device_type = "pci";
2221 compatible = "marvell,mv64360-pci";
2223 ranges = <0x01000000 0x0 0x0
2224 0x88000000 0x0 0x01000000
2225 0x02000000 0x0 0x80000000
2226 0x80000000 0x0 0x08000000>;
2227 bus-range = <0 255>;
2228 clock-frequency = <66000000>;
2229 interrupt-parent = <&PIC>;
2230 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2233 0x5000 0 0 1 &PIC 80
2234 0x5000 0 0 2 &PIC 81
2235 0x5000 0 0 3 &PIC 91
2236 0x5000 0 0 4 &PIC 93
2239 0x5800 0 0 1 &PIC 91
2240 0x5800 0 0 2 &PIC 93
2241 0x5800 0 0 3 &PIC 80
2242 0x5800 0 0 4 &PIC 81
2245 0x6000 0 0 1 &PIC 91
2246 0x6000 0 0 2 &PIC 93
2247 0x6000 0 0 3 &PIC 80
2248 0x6000 0 0 4 &PIC 81
2251 0x6800 0 0 1 &PIC 93
2252 0x6800 0 0 2 &PIC 80
2253 0x6800 0 0 3 &PIC 81
2254 0x6800 0 0 4 &PIC 91
2259 p) Marvell Discovery CPU Error nodes
2261 Represent the Discovery's CPU error handler device.
2263 Required properties:
2264 - compatible : "marvell,mv64360-cpu-error"
2265 - reg : Offset and length of the register set for this device
2266 - interrupts : the interrupt number for this device
2267 - interrupt-parent : the phandle for the interrupt controller
2268 that services interrupts for this device.
2270 Example Discovery CPU Error node:
2272 compatible = "marvell,mv64360-cpu-error";
2273 reg = <0x70 0x10 0x128 0x28>;
2275 interrupt-parent = <&PIC>;
2279 q) Marvell Discovery SRAM Controller nodes
2281 Represent the Discovery's SRAM controller device.
2283 Required properties:
2284 - compatible : "marvell,mv64360-sram-ctrl"
2285 - reg : Offset and length of the register set for this device
2286 - interrupts : the interrupt number for this device
2287 - interrupt-parent : the phandle for the interrupt controller
2288 that services interrupts for this device.
2290 Example Discovery SRAM Controller node:
2292 compatible = "marvell,mv64360-sram-ctrl";
2295 interrupt-parent = <&PIC>;
2299 r) Marvell Discovery PCI Error Handler nodes
2301 Represent the Discovery's PCI error handler device.
2303 Required properties:
2304 - compatible : "marvell,mv64360-pci-error"
2305 - reg : Offset and length of the register set for this device
2306 - interrupts : the interrupt number for this device
2307 - interrupt-parent : the phandle for the interrupt controller
2308 that services interrupts for this device.
2310 Example Discovery PCI Error Handler node:
2312 compatible = "marvell,mv64360-pci-error";
2313 reg = <0x1d40 0x40 0xc28 0x4>;
2315 interrupt-parent = <&PIC>;
2319 s) Marvell Discovery Memory Controller nodes
2321 Represent the Discovery's memory controller device.
2323 Required properties:
2324 - compatible : "marvell,mv64360-mem-ctrl"
2325 - reg : Offset and length of the register set for this device
2326 - interrupts : the interrupt number for this device
2327 - interrupt-parent : the phandle for the interrupt controller
2328 that services interrupts for this device.
2330 Example Discovery Memory Controller node:
2332 compatible = "marvell,mv64360-mem-ctrl";
2333 reg = <0x1400 0x60>;
2335 interrupt-parent = <&PIC>;
2339 VIII - Specifying interrupt information for devices
2340 ===================================================
2342 The device tree represents the busses and devices of a hardware
2343 system in a form similar to the physical bus topology of the
2346 In addition, a logical 'interrupt tree' exists which represents the
2347 hierarchy and routing of interrupts in the hardware.
2349 The interrupt tree model is fully described in the
2350 document "Open Firmware Recommended Practice: Interrupt
2351 Mapping Version 0.9". The document is available at:
2352 <http://playground.sun.com/1275/practice>.
2354 1) interrupts property
2355 ----------------------
2357 Devices that generate interrupts to a single interrupt controller
2358 should use the conventional OF representation described in the
2359 OF interrupt mapping documentation.
2361 Each device which generates interrupts must have an 'interrupt'
2362 property. The interrupt property value is an arbitrary number of
2363 of 'interrupt specifier' values which describe the interrupt or
2364 interrupts for the device.
2366 The encoding of an interrupt specifier is determined by the
2367 interrupt domain in which the device is located in the
2368 interrupt tree. The root of an interrupt domain specifies in
2369 its #interrupt-cells property the number of 32-bit cells
2370 required to encode an interrupt specifier. See the OF interrupt
2371 mapping documentation for a detailed description of domains.
2373 For example, the binding for the OpenPIC interrupt controller
2374 specifies an #interrupt-cells value of 2 to encode the interrupt
2375 number and level/sense information. All interrupt children in an
2376 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
2379 The PCI bus binding specifies a #interrupt-cell value of 1 to encode
2380 which interrupt pin (INTA,INTB,INTC,INTD) is used.
2382 2) interrupt-parent property
2383 ----------------------------
2385 The interrupt-parent property is specified to define an explicit
2386 link between a device node and its interrupt parent in
2387 the interrupt tree. The value of interrupt-parent is the
2388 phandle of the parent node.
2390 If the interrupt-parent property is not defined for a node, it's
2391 interrupt parent is assumed to be an ancestor in the node's
2392 _device tree_ hierarchy.
2394 3) OpenPIC Interrupt Controllers
2395 --------------------------------
2397 OpenPIC interrupt controllers require 2 cells to encode
2398 interrupt information. The first cell defines the interrupt
2399 number. The second cell defines the sense and level
2402 Sense and level information should be encoded as follows:
2404 0 = low to high edge sensitive type enabled
2405 1 = active low level sensitive type enabled
2406 2 = active high level sensitive type enabled
2407 3 = high to low edge sensitive type enabled
2409 4) ISA Interrupt Controllers
2410 ----------------------------
2412 ISA PIC interrupt controllers require 2 cells to encode
2413 interrupt information. The first cell defines the interrupt
2414 number. The second cell defines the sense and level
2417 ISA PIC interrupt controllers should adhere to the ISA PIC
2418 encodings listed below:
2420 0 = active low level sensitive type enabled
2421 1 = active high level sensitive type enabled
2422 2 = high to low edge sensitive type enabled
2423 3 = low to high edge sensitive type enabled
2425 VIII - Specifying GPIO information for devices
2426 ==============================================
2431 Nodes that makes use of GPIOs should define them using `gpios' property,
2432 format of which is: <&gpio-controller1-phandle gpio1-specifier
2433 &gpio-controller2-phandle gpio2-specifier
2434 0 /* holes are permitted, means no GPIO 3 */
2435 &gpio-controller4-phandle gpio4-specifier
2438 Note that gpio-specifier length is controller dependent.
2440 gpio-specifier may encode: bank, pin position inside the bank,
2441 whether pin is open-drain and whether pin is logically inverted.
2443 Example of the node using GPIOs:
2446 gpios = <&qe_pio_e 18 0>;
2449 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
2450 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2452 2) gpio-controller nodes
2453 ------------------------
2455 Every GPIO controller node must have #gpio-cells property defined,
2456 this information will be used to translate gpio-specifiers.
2458 Example of two SOC GPIO banks defined as gpio-controller nodes:
2460 qe_pio_a: gpio-controller@1400 {
2462 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
2463 reg = <0x1400 0x18>;
2467 qe_pio_e: gpio-controller@1460 {
2469 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
2470 reg = <0x1460 0x18>;
2474 Appendix A - Sample SOC node for MPC8540
2475 ========================================
2477 Note that the #address-cells and #size-cells for the SoC node
2478 in this example have been explicitly listed; these are likely
2479 not necessary as they are usually the same as the root node.
2482 #address-cells = <1>;
2484 #interrupt-cells = <2>;
2485 device_type = "soc";
2486 ranges = <00000000 e0000000 00100000>
2487 reg = <e0000000 00003000>;
2488 bus-frequency = <0>;
2492 device_type = "mdio";
2493 compatible = "gianfar";
2496 linux,phandle = <2452000>
2497 interrupt-parent = <40000>;
2498 interrupts = <35 1>;
2500 device_type = "ethernet-phy";
2504 linux,phandle = <2452001>
2505 interrupt-parent = <40000>;
2506 interrupts = <35 1>;
2508 device_type = "ethernet-phy";
2512 linux,phandle = <2452002>
2513 interrupt-parent = <40000>;
2514 interrupts = <35 1>;
2516 device_type = "ethernet-phy";
2523 device_type = "network";
2525 compatible = "gianfar";
2527 mac-address = [ 00 E0 0C 00 73 00 ];
2528 interrupts = <d 3 e 3 12 3>;
2529 interrupt-parent = <40000>;
2530 phy-handle = <2452000>;
2534 #address-cells = <1>;
2536 device_type = "network";
2538 compatible = "gianfar";
2540 mac-address = [ 00 E0 0C 00 73 01 ];
2541 interrupts = <13 3 14 3 18 3>;
2542 interrupt-parent = <40000>;
2543 phy-handle = <2452001>;
2547 #address-cells = <1>;
2549 device_type = "network";
2551 compatible = "gianfar";
2553 mac-address = [ 00 E0 0C 00 73 02 ];
2554 interrupts = <19 3>;
2555 interrupt-parent = <40000>;
2556 phy-handle = <2452002>;
2560 device_type = "serial";
2561 compatible = "ns16550";
2563 clock-frequency = <0>;
2564 interrupts = <1a 3>;
2565 interrupt-parent = <40000>;
2569 linux,phandle = <40000>;
2570 interrupt-controller;
2571 #address-cells = <0>;
2572 reg = <40000 40000>;
2573 compatible = "chrp,open-pic";
2574 device_type = "open-pic";
2578 interrupt-parent = <40000>;
2579 interrupts = <1b 3>;
2581 device_type = "i2c";
2582 compatible = "fsl-i2c";