4 This text describes the audio clocking terms in ASoC and digital audio in
5 general. Note: Audio clocking can be complex !
11 Every audio subsystem is driven by a master clock (sometimes refered to as MCLK
12 or SYSCLK). This audio master clock can be derived from a number of sources
13 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
14 audio playback and capture sample rates.
16 Some master clocks (e.g. PLL's and CPU based clocks) are configuarble in that
17 their speed can be altered by software (depending on the system use and to save
18 power). Other master clocks are fixed at at set frequency (i.e. crystals).
23 The Digital Audio Interface is usually driven by a Bit Clock (often referred to
24 as BCLK). This clock is used to drive the digital audio data across the link
25 between the codec and CPU.
27 The DAI also has a frame clock to signal the start of each audio frame. This
28 clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
29 runs at exactly the sample rate (LRC = Rate).
31 Bit Clock can be generated as follows:-
41 BCLK = LRC * Channels * Word Size
43 This relationship depends on the codec or SoC CPU in particular. ASoC can quite
44 easily match BCLK generated by division (SND_SOC_DAI_BFS_DIV) with BCLK by
45 multiplication (SND_SOC_DAI_BFS_RATE) or BCLK generated by
46 Rate * Channels * Word size (RCW or SND_SOC_DAI_BFS_RCW).
52 The ASoC core determines the clocking for each particular configuration at
53 runtime. This is to allow for dynamic audio clocking wereby the audio clock is
54 variable and depends on the system state or device usage scenario. i.e. a voice
55 call requires slower clocks (and hence less power) than MP3 playback.
57 ASoC will call the config_sysclock() function for the target machine during the
58 audio parameters configuration. The function is responsible for then clocking
59 the machine audio subsytem and returning the audio clock speed to the core.
60 This function should also call the codec and cpu DAI clock_config() functions
61 to configure their respective internal clocking if required.
64 ASoC Clocking Control Flow
65 --------------------------
67 The ASoC core will call the machine drivers config_sysclock() when most of the
68 DAI capabilities are known. The machine driver is then responsible for calling
69 the codec and/or CPU DAI drivers with the selected capabilities and the current
70 MCLK. Note that the machine driver is also resonsible for setting the MCLK (and
73 (1) Match Codec and CPU DAI capabilities. At this point we have
74 matched the majority of the DAI fields and now need to make sure this
75 mode is currently clockable.
77 (2) machine->config_sysclk() is now called with the matched DAI FS, sample
78 rate and BCLK master. This function then gets/sets the current audio
79 clock (depening on usage) and calls the codec and CPUI DAI drivers with
80 the FS, rate, BCLK master and MCLK.
82 (3) Codec/CPU DAI config_sysclock(). This function checks that the FS, rate,
83 BCLK master and MCLK are acceptable for the codec or CPU DAI. It also
84 sets the DAI internal state to work with said clocks.
86 The config_sysclk() functions for CPU, codec and machine should return the MCLK
87 on success and 0 on failure.
90 Examples (b = BCLK, l = LRC)
91 ============================
96 Simple codec that only runs at 48k @ 256FS in master mode.
98 CPU only runs as slave DAI, however it generates a variable MCLK.
102 | Codec |b -----------> | CPU |
103 | |l -----------> | |
107 The codec driver has the following config_sysclock()
109 static unsigned int config_sysclk(struct snd_soc_codec_dai *dai,
110 struct snd_soc_clock_info *info, unsigned int clk)
112 /* make sure clock is 256 * rate */
113 if(info->rate << 8 == clk) {
121 The CPU I2S DAI driver has the following config_sysclk()
123 static unsigned int config_sysclk(struct snd_soc_codec_dai *dai,
124 struct snd_soc_clock_info *info, unsigned int clk)
126 /* can we support this clk */
127 if(set_audio_clk(clk) < 0)
134 The machine driver config_sysclk() in this example is as follows:-
136 unsigned int machine_config_sysclk(struct snd_soc_pcm_runtime *rtd,
137 struct snd_soc_clock_info *info)
139 int clk = info->rate * info->fs;
141 /* check that CPU can deliver clock */
142 if(rtd->cpu_dai->config_sysclk(rtd->cpu_dai, info, clk) < 0)
145 /* can codec work with this clock */
146 return rtd->codec_dai->config_sysclk(rtd->codec_dai, info, clk);
153 Codec that can master at 8k and 48k at various FS (and hence supports a fixed
154 set of input MCLK's) and can also be slave at various FS .
156 The CPU can master at 8k and 48k @256 FS and can be slave at any FS.
158 MCLK is a 12.288MHz crystal on this machine.
162 | Codec |b <----------> | CPU |
163 | |l <----------> | |
168 The codec driver has the following config_sysclock()
170 /* supported input clocks */
171 const static int hifi_clks[] = {11289600, 12000000, 12288000,
174 static unsigned int config_hsysclk(struct snd_soc_codec_dai *dai,
175 struct snd_soc_clock_info *info, unsigned int clk)
179 /* is clk supported */
180 for(i = 0; i < ARRAY_SIZE(hifi_clks); i++) {
181 if(clk == hifi_clks[i]) {
187 /* this clk is not supported */
191 The CPU I2S DAI driver has the following config_sysclk()
193 static unsigned int config_sysclk(struct snd_soc_codec_dai *dai,
194 struct snd_soc_clock_info *info, unsigned int clk)
196 /* are we master or slave */
197 if (info->bclk_master &
198 (SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_CBM_CFS)) {
200 /* we can only master @ 256FS */
201 if(info->rate << 8 == clk) {
206 /* slave we can run at any FS */
215 The machine driver config_sysclk() in this example is as follows:-
217 unsigned int machine_config_sysclk(struct snd_soc_pcm_runtime *rtd,
218 struct snd_soc_clock_info *info)
220 int clk = 12288000; /* 12.288MHz */
222 /* who's driving the link */
223 if (info->bclk_master &
224 (SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_CBM_CFS)) {
227 /* check that CPU can work with clock */
228 if(rtd->cpu_dai->config_sysclk(rtd->cpu_dai, info, clk) < 0)
231 /* can codec work with this clock */
232 return rtd->codec_dai->config_sysclk(rtd->codec_dai, info, clk);
236 /* check that codec can work with clock */
237 if(rtd->codec_dai->config_sysclk(rtd->codec_dai, info, clk) < 0)
240 /* can CPU work with this clock */
241 return rtd->cpu_dai->config_sysclk(rtd->cpu_dai, info, clk);
250 Codec that masters at 8k ... 48k @256 FS. Codec can also be slave and
251 doesn't care about FS. The codec has an internal PLL and dividers to generate
252 the necessary internal clocks (for 256FS).
254 CPU can only be slave and doesn't care about FS.
256 MCLK is a non controllable 13MHz clock from the CPU.
261 | Codec |b <----------> | CPU |
262 | |l <----------> | |
266 The codec driver has the following config_sysclock()
268 /* valid PCM clock dividers * 2 */
269 static int pcm_divs[] = {2, 6, 11, 4, 8, 12, 16};
271 static unsigned int config_vsysclk(struct snd_soc_codec_dai *dai,
272 struct snd_soc_clock_info *info, unsigned int clk)
274 int i, j, best_clk = info->fs * info->rate;
276 /* can we run at this clk without the PLL ? */
277 for (i = 0; i < ARRAY_SIZE(pcm_divs); i++) {
278 if ((best_clk >> 1) * pcm_divs[i] == clk) {
280 dai->clk_div = pcm_divs[i];
281 dai->mclk = best_clk;
286 /* now check for PLL support */
287 for (i = 0; i < ARRAY_SIZE(pll_div); i++) {
288 if (pll_div[i].pll_in == clk) {
289 for (j = 0; j < ARRAY_SIZE(pcm_divs); j++) {
290 if (pll_div[i].pll_out == pcm_divs[j] * (best_clk >> 1)) {
292 dai->pll_out = pll_div[i].pll_out;
293 dai->clk_div = pcm_divs[j];
294 dai->mclk = best_clk;
301 /* this clk is not supported */
306 The CPU I2S DAI driver has the does not need a config_sysclk() as it can slave
309 unsigned int config_sysclk(struct snd_soc_pcm_runtime *rtd,
310 struct snd_soc_clock_info *info)
312 /* codec has pll that generates mclk from 13MHz xtal */
313 return rtd->codec_dai->config_sysclk(rtd->codec_dai, info, 13000000);