14 Fast page fault is the fast path which fixes the guest page fault out of
15 the mmu-lock on x86. Currently, the page fault can be fast only if the
16 shadow page table is present and it is caused by write-protect, that means
17 we just need change the W bit of the spte.
19 What we use to avoid all the race is the SPTE_HOST_WRITEABLE bit and
20 SPTE_MMU_WRITEABLE bit on the spte:
21 - SPTE_HOST_WRITEABLE means the gfn is writable on host.
22 - SPTE_MMU_WRITEABLE means the gfn is writable on mmu. The bit is set when
23 the gfn is writable on guest mmu and it is not write-protected by shadow
24 page write-protection.
26 On fast page fault path, we will use cmpxchg to atomically set the spte W
27 bit if spte.SPTE_HOST_WRITEABLE = 1 and spte.SPTE_WRITE_PROTECT = 1, this
28 is safe because whenever changing these bits can be detected by cmpxchg.
30 But we need carefully check these cases:
31 1): The mapping from gfn to pfn
32 The mapping from gfn to pfn may be changed since we can only ensure the pfn
33 is not changed during cmpxchg. This is a ABA problem, for example, below case
38 gfn1 is mapped to pfn1 on host
39 spte is the shadow page table entry corresponding with gpte and
43 on fast page fault path:
49 pfn1 is re-alloced for gfn2.
51 gpte is changed to point to
55 if (cmpxchg(spte, old_spte, old_spte+W)
56 mark_page_dirty(vcpu->kvm, gfn1)
59 We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap.
61 For direct sp, we can easily avoid it since the spte of direct sp is fixed
62 to gfn. For indirect sp, before we do cmpxchg, we call gfn_to_pfn_atomic()
63 to pin gfn to pfn, because after gfn_to_pfn_atomic():
64 - We have held the refcount of pfn that means the pfn can not be freed and
65 be reused for another gfn.
66 - The pfn is writable that means it can not be shared between different gfns
69 Then, we can ensure the dirty bitmaps is correctly set for a gfn.
71 Currently, to simplify the whole things, we disable fast page fault for
74 2): Dirty bit tracking
75 In the origin code, the spte can be fast updated (non-atomically) if the
76 spte is read-only and the Accessed bit has already been set since the
77 Accessed bit and Dirty bit can not be lost.
79 But it is not true after fast page fault since the spte can be marked
80 writable between reading spte and updating spte. Like below case:
87 In mmu_spte_clear_track_bits():
91 /* 'if' condition is satisfied. */
92 if (old_spte.Accssed == 1 &&
95 on fast page fault path:
97 memory write on the spte:
102 old_spte = xchg(spte, 0ull)
105 if (old_spte.Accssed == 1)
106 kvm_set_pfn_accessed(spte.pfn);
107 if (old_spte.Dirty == 1)
108 kvm_set_pfn_dirty(spte.pfn);
111 The Dirty bit is lost in this case.
113 In order to avoid this kind of issue, we always treat the spte as "volatile"
114 if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
115 the spte is always atomically updated in this case.
117 3): flush tlbs due to spte updated
118 If the spte is updated from writable to readonly, we should flush all TLBs,
119 otherwise rmap_write_protect will find a read-only spte, even though the
120 writable spte might be cached on a CPU's TLB.
122 As mentioned before, the spte can be updated to writable out of mmu-lock on
123 fast page fault path, in order to easily audit the path, we see if TLBs need
124 be flushed caused by this reason in mmu_spte_update() since this is a common
125 function to update spte (present -> present).
127 Since the spte is "volatile" if it can be updated out of mmu-lock, we always
128 atomically update the spte, the race caused by fast page fault can be avoided,
129 See the comments in spte_has_volatile_bits() and mmu_spte_update().
142 Protects: - hardware virtualization enable/disable
143 Comment: 'raw' because hardware enabling/disabling must be atomic /wrt
146 Name: kvm_arch::tsc_write_lock
149 Protects: - kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset}
151 Comment: 'raw' because updating the tsc offsets must not be preempted.
156 Protects: -shadow page/shadow tlb entry
157 Comment: it is a spinlock since it is used in mmu notifier.
162 Protects: - kvm->memslots
164 Comment: The srcu read lock must be held while accessing memslots (e.g.
165 when using gfn_to_* functions) and while accessing in-kernel
166 MMIO/PIO address->device structure mapping (kvm->buses).
167 The srcu index can be stored in kvm_vcpu->srcu_idx per vcpu
168 if it is needed by multiple functions.