6 #include <linux/spinlock.h>
7 #include <linux/dma-mapping.h>
8 #include <asm/scatterlist.h>
9 #include <asm/machvec.h>
12 * The following structure is used to manage multiple PCI busses.
18 struct pci_iommu_arena;
21 /* A controller. Used to manage multiple PCI busses. */
23 struct pci_controller {
24 struct pci_controller *next;
26 struct resource *io_space;
27 struct resource *mem_space;
29 /* The following are for reporting to userland. The invariant is
30 that if we report a BWX-capable dense memory, we do not report
31 a sparse memory at all, even if it exists. */
32 unsigned long sparse_mem_base;
33 unsigned long dense_mem_base;
34 unsigned long sparse_io_base;
35 unsigned long dense_io_base;
37 /* This one's for the kernel only. It's in KSEG somewhere. */
38 unsigned long config_space_base;
41 /* For compatibility with current (as of July 2003) pciutils
42 and XFree86. Eventually will be removed. */
43 unsigned int need_domain_info;
45 struct pci_iommu_arena *sg_pci;
46 struct pci_iommu_arena *sg_isa;
51 /* Override the logic in pci_scan_bus for skipping already-configured
54 #define pcibios_assign_all_busses() 1
56 #define PCIBIOS_MIN_IO alpha_mv.min_io_address
57 #define PCIBIOS_MIN_MEM alpha_mv.min_mem_address
59 extern void pcibios_set_master(struct pci_dev *dev);
61 extern inline void pcibios_penalize_isa_irq(int irq, int active)
63 /* We don't do dynamic PCI IRQ allocation */
68 /* The PCI address space does not equal the physical memory address space.
69 The networking and block device layers use this boolean for bounce buffer
71 #define PCI_DMA_BUS_IS_PHYS 0
73 /* Allocate and map kernel buffer using consistent mode DMA for PCI
74 device. Returns non-NULL cpu-view pointer to the buffer if
75 successful and sets *DMA_ADDRP to the pci side dma address as well,
76 else DMA_ADDRP is undefined. */
78 extern void *__pci_alloc_consistent(struct pci_dev *, size_t,
81 pci_alloc_consistent(struct pci_dev *dev, size_t size, dma_addr_t *dma)
83 return __pci_alloc_consistent(dev, size, dma, GFP_ATOMIC);
86 /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
87 be values that were returned from pci_alloc_consistent. SIZE must
88 be the same as what as passed into pci_alloc_consistent.
89 References to the memory and mappings associated with CPU_ADDR or
90 DMA_ADDR past this call are illegal. */
92 extern void pci_free_consistent(struct pci_dev *, size_t, void *, dma_addr_t);
94 /* Map a single buffer of the indicate size for PCI DMA in streaming mode.
95 The 32-bit PCI bus mastering address to use is returned. Once the device
96 is given the dma address, the device owns this memory until either
97 pci_unmap_single or pci_dma_sync_single_for_cpu is performed. */
99 extern dma_addr_t pci_map_single(struct pci_dev *, void *, size_t, int);
101 /* Likewise, but for a page instead of an address. */
102 extern dma_addr_t pci_map_page(struct pci_dev *, struct page *,
103 unsigned long, size_t, int);
105 /* Test for pci_map_single or pci_map_page having generated an error. */
108 pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t dma_addr)
110 return dma_addr == 0;
113 /* Unmap a single streaming mode DMA translation. The DMA_ADDR and
114 SIZE must match what was provided for in a previous pci_map_single
115 call. All other usages are undefined. After this call, reads by
116 the cpu to the buffer are guaranteed to see whatever the device
119 extern void pci_unmap_single(struct pci_dev *, dma_addr_t, size_t, int);
120 extern void pci_unmap_page(struct pci_dev *, dma_addr_t, size_t, int);
122 /* Map a set of buffers described by scatterlist in streaming mode for
123 PCI DMA. This is the scatter-gather version of the above
124 pci_map_single interface. Here the scatter gather list elements
125 are each tagged with the appropriate PCI dma address and length.
126 They are obtained via sg_dma_{address,length}(SG).
128 NOTE: An implementation may be able to use a smaller number of DMA
129 address/length pairs than there are SG table elements. (for
130 example via virtual mapping capabilities) The routine returns the
131 number of addr/length pairs actually used, at most nents.
133 Device ownership issues as mentioned above for pci_map_single are
136 extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int);
138 /* Unmap a set of streaming mode DMA translations. Again, cpu read
139 rules concerning calls here are the same as for pci_unmap_single()
142 extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int);
144 /* Make physical memory consistent for a single streaming mode DMA
145 translation after a transfer and device currently has ownership
148 If you perform a pci_map_single() but wish to interrogate the
149 buffer using the cpu, yet do not wish to teardown the PCI dma
150 mapping, you must call this function before doing so. At the next
151 point you give the PCI dma address back to the card, you must first
152 perform a pci_dma_sync_for_device, and then the device again owns
156 pci_dma_sync_single_for_cpu(struct pci_dev *dev, dma_addr_t dma_addr,
157 long size, int direction)
163 pci_dma_sync_single_for_device(struct pci_dev *dev, dma_addr_t dma_addr,
164 size_t size, int direction)
169 /* Make physical memory consistent for a set of streaming mode DMA
170 translations after a transfer. The same as pci_dma_sync_single_*
171 but for a scatter-gather list, same rules and usage. */
174 pci_dma_sync_sg_for_cpu(struct pci_dev *dev, struct scatterlist *sg,
175 int nents, int direction)
181 pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg,
182 int nents, int direction)
187 /* Return whether the given PCI device DMA address mask can
188 be supported properly. For example, if your device can
189 only drive the low 24-bits during PCI bus mastering, then
190 you would pass 0x00ffffff as the mask to this function. */
192 extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
195 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
196 enum pci_dma_burst_strategy *strat,
197 unsigned long *strategy_parameter)
199 unsigned long cacheline_size;
202 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
204 cacheline_size = 1024;
206 cacheline_size = (int) byte * 4;
208 *strat = PCI_DMA_BURST_BOUNDARY;
209 *strategy_parameter = cacheline_size;
213 /* TODO: integrate with include/asm-generic/pci.h ? */
214 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
216 return channel ? 15 : 14;
219 extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
222 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
223 struct pci_bus_region *region);
225 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
227 static inline int pci_proc_domain(struct pci_bus *bus)
229 struct pci_controller *hose = bus->sysdata;
230 return hose->need_domain_info;
233 struct pci_dev *alpha_gendev_to_pci(struct device *dev);
235 #endif /* __KERNEL__ */
237 /* Values for the `which' argument to sys_pciconfig_iobase. */
238 #define IOBASE_HOSE 0
239 #define IOBASE_SPARSE_MEM 1
240 #define IOBASE_DENSE_MEM 2
241 #define IOBASE_SPARSE_IO 3
242 #define IOBASE_DENSE_IO 4
243 #define IOBASE_ROOT_BUS 5
244 #define IOBASE_FROM_HOSE 0x10000
246 extern struct pci_dev *isa_bridge;
248 extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
250 extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
252 extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
253 struct vm_area_struct *vma,
254 enum pci_mmap_state mmap_state);
255 extern void pci_adjust_legacy_attr(struct pci_bus *bus,
256 enum pci_mmap_state mmap_type);
257 #define HAVE_PCI_LEGACY 1
259 extern int pci_create_resource_files(struct pci_dev *dev);
260 extern void pci_remove_resource_files(struct pci_dev *dev);
262 #endif /* __ALPHA_PCI_H */