2 * linux/arch/alpha/kernel/irq_pyxis.c
4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
6 * IRQ Code common to all PYXIS core logic chips.
9 #include <linux/init.h>
10 #include <linux/sched.h>
11 #include <linux/irq.h>
14 #include <asm/core_cia.h>
20 /* Note mask bit is true for ENABLED irqs. */
21 static unsigned long cached_irq_mask;
24 pyxis_update_irq_hw(unsigned long mask)
26 *(vulp)PYXIS_INT_MASK = mask;
28 *(vulp)PYXIS_INT_MASK;
32 pyxis_enable_irq(unsigned int irq)
34 pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
38 pyxis_disable_irq(unsigned int irq)
40 pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
44 pyxis_startup_irq(unsigned int irq)
46 pyxis_enable_irq(irq);
51 pyxis_end_irq(unsigned int irq)
53 struct irq_desc *desc = irq_to_desc(irq);
54 if (desc || !(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
55 pyxis_enable_irq(irq);
59 pyxis_mask_and_ack_irq(unsigned int irq)
61 unsigned long bit = 1UL << (irq - 16);
62 unsigned long mask = cached_irq_mask &= ~bit;
64 /* Disable the interrupt. */
65 *(vulp)PYXIS_INT_MASK = mask;
67 /* Ack PYXIS PCI interrupt. */
68 *(vulp)PYXIS_INT_REQ = bit;
70 /* Re-read to force both writes. */
71 *(vulp)PYXIS_INT_MASK;
74 static struct irq_chip pyxis_irq_type = {
76 .startup = pyxis_startup_irq,
77 .shutdown = pyxis_disable_irq,
78 .enable = pyxis_enable_irq,
79 .disable = pyxis_disable_irq,
80 .ack = pyxis_mask_and_ack_irq,
85 pyxis_device_interrupt(unsigned long vector)
90 /* Read the interrupt summary register of PYXIS */
91 pld = *(vulp)PYXIS_INT_REQ;
92 pld &= cached_irq_mask;
95 * Now for every possible bit set, work through them and call
96 * the appropriate interrupt handler.
100 pld &= pld - 1; /* clear least bit set */
102 isa_device_interrupt(vector);
109 init_pyxis_irqs(unsigned long ignore_mask)
113 *(vulp)PYXIS_INT_MASK = 0; /* disable all */
114 *(vulp)PYXIS_INT_REQ = -1; /* flush all */
117 /* Send -INTA pulses to clear any pending interrupts ...*/
120 for (i = 16; i < 48; ++i) {
121 if ((ignore_mask >> i) & 1)
123 set_irq_chip_and_handler(i, &pyxis_irq_type, alpha_do_IRQ);
124 irq_to_desc(i)->status |= IRQ_LEVEL;
127 setup_irq(16+7, &isa_cascade_irqaction);