2 * linux/arch/alpha/kernel/sys_nautilus.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1998 Richard Henderson
6 * Copyright (C) 1999 Alpha Processor, Inc.,
7 * (David Daniel, Stig Telfer, Soohoon Lee)
9 * Code supporting NAUTILUS systems.
12 * NAUTILUS has the following I/O features:
14 * a) Driven by AMD 751 aka IRONGATE (northbridge):
18 * b) Driven by ALI M1543C (southbridge)
21 * 1 dual drive capable FDD controller
23 * 1 ECP/EPP/SP parallel port
27 #include <linux/kernel.h>
28 #include <linux/types.h>
30 #include <linux/sched.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/reboot.h>
34 #include <linux/bootmem.h>
35 #include <linux/bitops.h>
37 #include <asm/ptrace.h>
40 #include <asm/mmu_context.h>
43 #include <asm/pgtable.h>
44 #include <asm/core_irongate.h>
45 #include <asm/hwrpb.h>
46 #include <asm/tlbflush.h>
52 #include "machvec_impl.h"
56 nautilus_init_irq(void)
58 if (alpha_using_srm) {
59 alpha_mv.device_interrupt = srm_device_interrupt;
63 common_init_isa_dma();
67 nautilus_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
69 /* Preserve the IRQ set up by the console. */
72 /* UP1500: AGP INTA is actually routed to IRQ 5, not IRQ 10 as
73 console reports. Check the device id of AGP bridge to distinguish
74 UP1500 from UP1000/1100. Note: 'pin' is 2 due to bridge swizzle. */
75 if (slot == 1 && pin == 2 &&
76 dev->bus->self && dev->bus->self->device == 0x700f)
78 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
83 nautilus_kill_arch(int mode)
85 struct pci_bus *bus = pci_isa_hose->bus;
90 case LINUX_REBOOT_CMD_RESTART:
91 if (! alpha_using_srm) {
93 pci_bus_read_config_byte(bus, 0x38, 0x43, &t8);
94 pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80);
101 case LINUX_REBOOT_CMD_POWER_OFF:
103 off = 0x2000; /* SLP_TYPE = 0, SLP_EN = 1 */
104 pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport);
107 off = 0x3400; /* SLP_TYPE = 5, SLP_EN = 1 */
108 pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport);
111 outw(0xffff, pmuport); /* Clear pending events. */
112 outw(off, pmuport + 4);
118 /* Perform analysis of a machine check that arrived from the system (NMI) */
121 naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
122 struct pt_regs *regs)
124 printk("PC %lx RA %lx\n", regs->pc, regs->r26);
125 irongate_pci_clr_err();
128 /* Machine checks can come from two sources - those on the CPU and those
129 in the system. They are analysed separately but all starts here. */
132 nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
136 /* Now for some analysis. Machine checks fall into two classes --
137 those picked up by the system, and those picked up by the CPU.
138 Add to that the two levels of severity - correctable or not. */
140 if (vector == SCB_Q_SYSMCHK
141 && ((IRONGATE0->dramms & 0x300) == 0x300)) {
142 unsigned long nmi_ctl;
151 /* Write again clears error bits. */
152 IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
156 /* Write again clears error bits. */
157 IRONGATE0->dramms = IRONGATE0->dramms;
167 if (vector == SCB_Q_SYSERR)
168 mchk_class = "Correctable";
169 else if (vector == SCB_Q_SYSMCHK)
170 mchk_class = "Fatal";
172 ev6_machine_check(vector, la_ptr);
176 printk(KERN_CRIT "NAUTILUS Machine check 0x%lx "
177 "[%s System Machine Check (NMI)]\n",
180 naut_sys_machine_check(vector, la_ptr, get_irq_regs());
182 /* Tell the PALcode to clear the machine check */
188 extern void pcibios_claim_one_bus(struct pci_bus *);
190 static struct resource irongate_io = {
191 .name = "Irongate PCI IO",
192 .flags = IORESOURCE_IO,
194 static struct resource irongate_mem = {
195 .name = "Irongate PCI MEM",
196 .flags = IORESOURCE_MEM,
200 nautilus_init_pci(void)
202 struct pci_controller *hose = hose_head;
204 struct pci_dev *irongate;
205 unsigned long bus_align, bus_size, pci_mem;
206 unsigned long memtop = max_low_pfn << PAGE_SHIFT;
208 /* Scan our single hose. */
209 bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
211 pcibios_claim_one_bus(bus);
213 irongate = pci_get_bus_and_slot(0, 0);
214 bus->self = irongate;
215 bus->resource[0] = &irongate_io;
216 bus->resource[1] = &irongate_mem;
218 pci_bus_size_bridges(bus);
221 bus->resource[0]->start = 0;
222 bus->resource[0]->end = 0xffff;
224 /* Set up PCI memory range - limit is hardwired to 0xffffffff,
225 base must be at aligned to 16Mb. */
226 bus_align = bus->resource[1]->start;
227 bus_size = bus->resource[1]->end + 1 - bus_align;
228 if (bus_align < 0x1000000UL)
229 bus_align = 0x1000000UL;
231 pci_mem = (0x100000000UL - bus_size) & -bus_align;
233 bus->resource[1]->start = pci_mem;
234 bus->resource[1]->end = 0xffffffffUL;
235 if (request_resource(&iomem_resource, bus->resource[1]) < 0)
236 printk(KERN_ERR "Failed to request MEM on hose 0\n");
238 if (pci_mem < memtop)
240 if (memtop > alpha_mv.min_mem_address) {
241 free_reserved_area((unsigned long)__va(alpha_mv.min_mem_address),
242 (unsigned long)__va(memtop), 0, NULL);
243 printk("nautilus_init_pci: %ldk freed\n",
244 (memtop - alpha_mv.min_mem_address) >> 10);
247 if ((IRONGATE0->dev_vendor >> 16) > 0x7006) /* Albacore? */
248 IRONGATE0->pci_mem = pci_mem;
250 pci_bus_assign_resources(bus);
252 /* pci_common_swizzle() relies on bus->self being NULL
253 for the root bus, so just clear it. */
255 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
262 struct alpha_machine_vector nautilus_mv __initmv = {
263 .vector_name = "Nautilus",
267 .machine_check = nautilus_machine_check,
268 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
269 .min_io_address = DEFAULT_IO_BASE,
270 .min_mem_address = IRONGATE_DEFAULT_MEM_BASE,
273 .device_interrupt = isa_device_interrupt,
275 .init_arch = irongate_init_arch,
276 .init_irq = nautilus_init_irq,
277 .init_rtc = common_init_rtc,
278 .init_pci = nautilus_init_pci,
279 .kill_arch = nautilus_kill_arch,
280 .pci_map_irq = nautilus_map_irq,
281 .pci_swizzle = common_swizzle,