2 * linux/arch/alpha/kernel/sys_titan.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 * Copyright (C) 1999, 2000 Jeff Wiedemeier
9 * Code supporting TITAN systems (EV6+TITAN), currently:
15 #include <linux/kernel.h>
16 #include <linux/types.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/bitops.h>
23 #include <asm/ptrace.h>
24 #include <asm/system.h>
27 #include <asm/mmu_context.h>
29 #include <asm/pgtable.h>
30 #include <asm/core_titan.h>
31 #include <asm/hwrpb.h>
32 #include <asm/tlbflush.h>
37 #include "machvec_impl.h"
46 * Titan supports up to 4 CPUs
48 static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };
51 * Mask is set (1) if enabled
53 static unsigned long titan_cached_irq_mask;
56 * Need SMP-safe access to interrupt CSRs
58 DEFINE_SPINLOCK(titan_irq_lock);
61 titan_update_irq_hw(unsigned long mask)
63 register titan_cchip *cchip = TITAN_cchip;
64 unsigned long isa_enable = 1UL << 55;
65 register int bcpu = boot_cpuid;
68 cpumask_t cpm = cpu_present_map;
69 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
70 unsigned long mask0, mask1, mask2, mask3, dummy;
73 mask0 = mask & titan_cpu_irq_affinity[0];
74 mask1 = mask & titan_cpu_irq_affinity[1];
75 mask2 = mask & titan_cpu_irq_affinity[2];
76 mask3 = mask & titan_cpu_irq_affinity[3];
78 if (bcpu == 0) mask0 |= isa_enable;
79 else if (bcpu == 1) mask1 |= isa_enable;
80 else if (bcpu == 2) mask2 |= isa_enable;
81 else mask3 |= isa_enable;
83 dim0 = &cchip->dim0.csr;
84 dim1 = &cchip->dim1.csr;
85 dim2 = &cchip->dim2.csr;
86 dim3 = &cchip->dim3.csr;
87 if (!cpu_isset(0, cpm)) dim0 = &dummy;
88 if (!cpu_isset(1, cpm)) dim1 = &dummy;
89 if (!cpu_isset(2, cpm)) dim2 = &dummy;
90 if (!cpu_isset(3, cpm)) dim3 = &dummy;
102 volatile unsigned long *dimB;
103 dimB = &cchip->dim0.csr;
104 if (bcpu == 1) dimB = &cchip->dim1.csr;
105 else if (bcpu == 2) dimB = &cchip->dim2.csr;
106 else if (bcpu == 3) dimB = &cchip->dim3.csr;
108 *dimB = mask | isa_enable;
115 titan_enable_irq(unsigned int irq)
117 spin_lock(&titan_irq_lock);
118 titan_cached_irq_mask |= 1UL << (irq - 16);
119 titan_update_irq_hw(titan_cached_irq_mask);
120 spin_unlock(&titan_irq_lock);
124 titan_disable_irq(unsigned int irq)
126 spin_lock(&titan_irq_lock);
127 titan_cached_irq_mask &= ~(1UL << (irq - 16));
128 titan_update_irq_hw(titan_cached_irq_mask);
129 spin_unlock(&titan_irq_lock);
133 titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
137 for (cpu = 0; cpu < 4; cpu++) {
138 if (cpu_isset(cpu, affinity))
139 titan_cpu_irq_affinity[cpu] |= 1UL << irq;
141 titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
147 titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
149 spin_lock(&titan_irq_lock);
150 titan_cpu_set_irq_affinity(irq - 16, *affinity);
151 titan_update_irq_hw(titan_cached_irq_mask);
152 spin_unlock(&titan_irq_lock);
158 titan_device_interrupt(unsigned long vector)
160 printk("titan_device_interrupt: NOT IMPLEMENTED YET!!\n");
164 titan_srm_device_interrupt(unsigned long vector)
168 irq = (vector - 0x800) >> 4;
174 init_titan_irqs(struct irq_chip * ops, int imin, int imax)
177 for (i = imin; i <= imax; ++i) {
178 irq_to_desc(i)->status |= IRQ_LEVEL;
179 set_irq_chip_and_handler(i, ops, handle_level_irq);
183 static struct irq_chip titan_irq_type = {
185 .unmask = titan_enable_irq,
186 .mask = titan_disable_irq,
187 .mask_ack = titan_disable_irq,
188 .set_affinity = titan_set_irq_affinity,
192 titan_intr_nop(int irq, void *dev_id)
195 * This is a NOP interrupt handler for the purposes of
196 * event counting -- just return.
204 if (alpha_using_srm && !alpha_mv.device_interrupt)
205 alpha_mv.device_interrupt = titan_srm_device_interrupt;
206 if (!alpha_mv.device_interrupt)
207 alpha_mv.device_interrupt = titan_device_interrupt;
209 titan_update_irq_hw(0);
211 init_titan_irqs(&titan_irq_type, 16, 63 + 16);
215 titan_legacy_init_irq(void)
217 /* init the legacy dma controller */
218 outb(0, DMA1_RESET_REG);
219 outb(0, DMA2_RESET_REG);
220 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
221 outb(0, DMA2_MASK_REG);
223 /* init the legacy irq controller */
226 /* init the titan irqs */
231 titan_dispatch_irqs(u64 mask)
233 unsigned long vector;
236 * Mask down to those interrupts which are enable on this processor
238 mask &= titan_cpu_irq_affinity[smp_processor_id()];
241 * Dispatch all requested interrupts
244 /* convert to SRM vector... priority is <63> -> <0> */
245 vector = 63 - __kernel_ctlz(mask);
246 mask &= ~(1UL << vector); /* clear it out */
247 vector = 0x900 + (vector << 4); /* convert to SRM vector */
250 alpha_mv.device_interrupt(vector);
259 titan_request_irq(unsigned int irq, irq_handler_t handler,
260 unsigned long irqflags, const char *devname,
264 err = request_irq(irq, handler, irqflags, devname, dev_id);
266 printk("titan_request_irq for IRQ %d returned %d; ignoring\n",
272 titan_late_init(void)
275 * Enable the system error interrupts. These interrupts are
276 * all reported to the kernel as machine checks, so the handler
277 * is a nop so it can be called to count the individual events.
279 titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED,
280 "CChip Error", NULL);
281 titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED,
282 "PChip 0 H_Error", NULL);
283 titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED,
284 "PChip 1 H_Error", NULL);
285 titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED,
286 "PChip 0 C_Error", NULL);
287 titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED,
288 "PChip 1 C_Error", NULL);
291 * Register our error handlers.
293 titan_register_error_handlers();
296 * Check if the console left us any error logs.
298 cdl_check_console_data_log();
303 titan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
308 /* Get the current intline. */
309 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
312 /* Is it explicitly routed through ISA? */
313 if ((irq & 0xF0) == 0xE0)
316 /* Offset by 16 to make room for ISA interrupts 0 - 15. */
324 * This isn't really the right place, but there's some init
325 * that needs to be done after everything is basically up.
332 locate_and_init_vga(NULL);
340 privateer_init_pci(void)
343 * Hook a couple of extra err interrupts that the
344 * common titan code won't.
346 titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED,
348 titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED,
349 "Temperature Warning", NULL);
352 * Finish with the common version.
354 return titan_init_pci();
359 * The System Vectors.
361 struct alpha_machine_vector titan_mv __initmv = {
362 .vector_name = "TITAN",
366 .machine_check = titan_machine_check,
367 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
368 .min_io_address = DEFAULT_IO_BASE,
369 .min_mem_address = DEFAULT_MEM_BASE,
370 .pci_dac_offset = TITAN_DAC_OFFSET,
372 .nr_irqs = 80, /* 64 + 16 */
373 /* device_interrupt will be filled in by titan_init_irq */
375 .agp_info = titan_agp_info,
377 .init_arch = titan_init_arch,
378 .init_irq = titan_legacy_init_irq,
379 .init_rtc = common_init_rtc,
380 .init_pci = titan_init_pci,
382 .kill_arch = titan_kill_arch,
383 .pci_map_irq = titan_map_irq,
384 .pci_swizzle = common_swizzle,
388 struct alpha_machine_vector privateer_mv __initmv = {
389 .vector_name = "PRIVATEER",
393 .machine_check = privateer_machine_check,
394 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
395 .min_io_address = DEFAULT_IO_BASE,
396 .min_mem_address = DEFAULT_MEM_BASE,
397 .pci_dac_offset = TITAN_DAC_OFFSET,
399 .nr_irqs = 80, /* 64 + 16 */
400 /* device_interrupt will be filled in by titan_init_irq */
402 .agp_info = titan_agp_info,
404 .init_arch = titan_init_arch,
405 .init_irq = titan_legacy_init_irq,
406 .init_rtc = common_init_rtc,
407 .init_pci = privateer_init_pci,
409 .kill_arch = titan_kill_arch,
410 .pci_map_irq = titan_map_irq,
411 .pci_swizzle = common_swizzle,
413 /* No alpha_mv alias for privateer since we compile it
414 in unconditionally with titan; setup_arch knows how to cope. */