2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
12 select BUILDTIME_EXTABLE_SORT
14 select CLONE_BACKWARDS
15 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
16 select DEVTMPFS if !INITRAMFS_SOURCE=""
17 select GENERIC_ATOMIC64
18 select GENERIC_CLOCKEVENTS
19 select GENERIC_FIND_FIRST_BIT
20 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PENDING_IRQ if SMP
23 select GENERIC_SMP_IDLE_THREAD
25 select HAVE_ARCH_TRACEHOOK
26 select HAVE_FUTEX_CMPXCHG
27 select HAVE_IOREMAP_PROT
29 select HAVE_KRETPROBES
31 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
33 select HAVE_PERF_EVENTS
35 select MODULES_USE_ELF_RELA
38 select OF_EARLY_FLATTREE
39 select PERF_USE_VMALLOC
40 select HAVE_DEBUG_STACKOVERFLOW
42 config TRACE_IRQFLAGS_SUPPORT
45 config LOCKDEP_SUPPORT
48 config SCHED_OMIT_FRAME_POINTER
54 config RWSEM_GENERIC_SPINLOCK
57 config ARCH_FLATMEM_ENABLE
66 config GENERIC_CALIBRATE_DELAY
69 config GENERIC_HWEIGHT
72 config STACKTRACE_SUPPORT
76 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
81 source "kernel/Kconfig.freezer"
83 menu "ARC Architecture Configuration"
85 menu "ARC Platform/SoC/Board"
87 source "arch/arc/plat-sim/Kconfig"
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 #New platform adds here
95 prompt "ARC Instruction Set"
101 The original ARC ISA of ARC600/700 cores
106 ISA for the Next Generation ARC-HS cores
110 menu "ARC CPU Configuration"
114 default ARC_CPU_770 if ISA_ARCOMPACT
115 default ARC_CPU_HS if ISA_ARCV2
123 Support for ARC750 core
129 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
130 This core has a bunch of cool new features:
131 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
132 Shared Address Spaces (for sharing TLB entires in MMU)
133 -Caches: New Prog Model, Region Flush
134 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
142 Support for ARC HS38x Cores based on ARCv2 ISA
143 The notable features are:
144 - SMP configurations of upto 4 core with coherency
145 - Optional L2 Cache and IO-Coherency
146 - Revised Interrupt Architecture (multiple priorites, reg banks,
147 auto stack switch, auto regfile save/restore)
148 - MMUv4 (PIPT dcache, Huge Pages)
150 * 64bit load/store: LDD, STD
151 * Hardware assisted divide/remainder: DIV, REM
152 * Function prologue/epilogue: ENTER_S, LEAVE_S
153 * IRQ enable/disable: CLRI, SETI
154 * pop count: FFS, FLS
155 * SETcc, BMSKN, XBFU...
159 config CPU_BIG_ENDIAN
160 bool "Enable Big Endian Mode"
163 Build kernel for Big Endian Mode of ARC CPU
166 bool "Symmetric Multi-Processing"
168 select ARC_HAS_COH_CACHES if ISA_ARCV2
169 select ARC_MCIP if ISA_ARCV2
171 This enables support for systems with more than one CPU.
175 config ARC_HAS_COH_CACHES
178 config ARC_HAS_REENTRANT_IRQ_LV2
182 bool "ARConnect Multicore IP (MCIP) Support "
185 This IP block enables SMP in ARC-HS38 cores.
186 It provides for cross-core interrupts, multi-core debug
187 hardware semaphores, shared memory,....
190 int "Maximum number of CPUs (2-4096)"
194 config ARC_SMP_HALT_ON_RESET
195 bool "Enable Halt-on-reset boot mode"
196 default y if ARC_UBOOT_SUPPORT
198 In SMP configuration cores can be configured as Halt-on-reset
199 or they could all start at same time. For Halt-on-reset, non
200 masters are parked until Master kicks them so they can start of
201 at designated entry point. For other case, all jump to common
202 entry point and spin wait for Master's signal.
207 bool "Enable Cache Support"
209 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
210 depends on !SMP || ARC_HAS_COH_CACHES
214 config ARC_CACHE_LINE_SHIFT
215 int "Cache Line Length (as power of 2)"
219 Starting with ARC700 4.9, Cache line length is configurable,
220 This option specifies "N", with Line-len = 2 power N
221 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
222 Linux only supports same line lengths for I and D caches.
224 config ARC_HAS_ICACHE
225 bool "Use Instruction Cache"
228 config ARC_HAS_DCACHE
229 bool "Use Data Cache"
232 config ARC_CACHE_PAGES
233 bool "Per Page Cache Control"
235 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
237 This can be used to over-ride the global I/D Cache Enable on a
238 per-page basis (but only for pages accessed via MMU such as
239 Kernel Virtual address or User Virtual Address)
240 TLB entries have a per-page Cache Enable Bit.
241 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
242 Global DISABLE + Per Page ENABLE won't work
244 config ARC_CACHE_VIPT_ALIASING
245 bool "Support VIPT Aliasing D$"
246 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
254 Single Cycle RAMS to store Fast Path Code
258 int "ICCM Size in KB"
260 depends on ARC_HAS_ICCM
265 Single Cycle RAMS to store Fast Path Data
269 int "DCCM Size in KB"
271 depends on ARC_HAS_DCCM
274 hex "DCCM map address"
276 depends on ARC_HAS_DCCM
278 config ARC_HAS_HW_MPY
279 bool "Use Hardware Multiplier (Normal or Faster XMAC)"
282 Influences how gcc generates code for MPY operations.
283 If enabled, MPYxx insns are generated, provided by Standard/XMAC
284 Multipler. Otherwise software multipy lib is used
288 default ARC_MMU_V3 if ARC_CPU_770
289 default ARC_MMU_V2 if ARC_CPU_750D
290 default ARC_MMU_V4 if ARC_CPU_HS
302 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
303 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
307 depends on ARC_CPU_770
309 Introduced with ARC700 4.10: New Features
310 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
311 Shared Address Spaces (SASID)
323 prompt "MMU Page Size"
324 default ARC_PAGE_SIZE_8K
326 config ARC_PAGE_SIZE_8K
329 Choose between 8k vs 16k
331 config ARC_PAGE_SIZE_16K
333 depends on ARC_MMU_V3 || ARC_MMU_V4
335 config ARC_PAGE_SIZE_4K
337 depends on ARC_MMU_V3 || ARC_MMU_V4
343 config ARC_COMPACT_IRQ_LEVELS
344 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
346 # Timer HAS to be high priority, for any other high priority config
348 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
349 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
351 if ARC_COMPACT_IRQ_LEVELS
362 endif #ARC_COMPACT_IRQ_LEVELS
364 config ARC_FPU_SAVE_RESTORE
365 bool "Enable FPU state persistence across context switch"
368 Double Precision Floating Point unit had dedictaed regs which
369 need to be saved/restored across context-switch.
370 Note that ARC FPU is overly simplistic, unlike say x86, which has
371 hardware pieces to allow software to conditionally save/restore,
372 based on actual usage of FPU by a task. Thus our implemn does
373 this for all tasks in system.
381 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
383 depends on !ARC_CANT_LLSC
385 config ARC_STAR_9000923308
386 bool "Workaround for llock/scond livelock"
388 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
391 bool "Insn: SWAPE (endian-swap)"
397 bool "Insn: 64bit LDD/STD"
399 Enable gcc to generate 64-bit load/store instructions
400 ISA mandates even/odd registers to allow encoding of two
401 dest operands with 2 possible source operands.
404 config ARC_HAS_DIV_REM
405 bool "Insn: div, divu, rem, remu"
409 bool "Local 64-bit r/o cycle counter"
414 bool "SMP synchronized 64-bit cycle counter"
418 config ARC_NUMBER_OF_INTERRUPTS
419 int "Number of interrupts"
423 This defines the number of interrupts on the ARCv2HS core.
424 It affects the size of vector table.
425 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
426 in hardware, it keep things simple for Linux to assume they are always
431 endmenu # "ARC CPU Configuration"
433 config LINUX_LINK_BASE
434 hex "Linux Link Address"
437 ARC700 divides the 32 bit phy address space into two equal halves
438 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
439 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
440 Typically Linux kernel is linked at the start of untransalted addr,
441 hence the default value of 0x8zs.
442 However some customers have peripherals mapped at this addr, so
443 Linux needs to be scooted a bit.
444 If you don't know what the above means, leave this setting alone.
445 This needs to match memory start address specified in Device Tree
448 bool "High Memory Support"
450 With ARC 2G:2G address split, only upper 2G is directly addressable by
451 kernel. Enable this to potentially allow access to rest of 2G and PAE
455 bool "Support for the 40-bit Physical Address Extension"
460 Enable access to physical memory beyond 4G, only supported on
461 ARC cores with 40 bit Physical Addressing support
463 config ARCH_PHYS_ADDR_T_64BIT
464 def_bool ARC_HAS_PAE40
466 config ARCH_DMA_ADDR_T_64BIT
469 config ARC_CURR_IN_REG
470 bool "Dedicate Register r25 for current_task pointer"
473 This reserved Register R25 to point to Current Task in
474 kernel mode. This saves memory access for each such access
477 config ARC_EMUL_UNALIGNED
478 bool "Emulate unaligned memory access (userspace only)"
480 select SYSCTL_ARCH_UNALIGN_NO_WARN
481 select SYSCTL_ARCH_UNALIGN_ALLOW
482 depends on ISA_ARCOMPACT
484 This enables misaligned 16 & 32 bit memory access from user space.
485 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
486 potential bugs in code
489 int "Timer Frequency"
492 config ARC_METAWARE_HLINK
493 bool "Support for Metaware debugger assisted Host access"
496 This options allows a Linux userland apps to directly access
497 host file system (open/creat/read/write etc) with help from
498 Metaware Debugger. This can come in handy for Linux-host communication
499 when there is no real usable peripheral such as EMAC.
507 config ARC_DW2_UNWIND
508 bool "Enable DWARF specific kernel stack unwind"
512 Compiles the kernel with DWARF unwind information and can be used
513 to get stack backtraces.
515 If you say Y here the resulting kernel image will be slightly larger
516 but not slower, and it will give very useful debugging information.
517 If you don't debug the kernel, you can say N, but we may not be able
518 to solve problems without frame unwind information
520 config ARC_DBG_TLB_PARANOIA
521 bool "Paranoia Checks in Low Level TLB Handlers"
524 config ARC_DBG_TLB_MISS_COUNT
525 bool "Profile TLB Misses"
529 Counts number of I and D TLB Misses and exports them via Debugfs
530 The counters can be cleared via Debugfs as well
535 bool "Debug Inter Core interrupts"
542 config ARC_UBOOT_SUPPORT
543 bool "Support uboot arg Handling"
546 ARC Linux by default checks for uboot provided args as pointers to
547 external cmdline or DTB. This however breaks in absence of uboot,
548 when booting from Metaware debugger directly, as the registers are
549 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
550 registers look like uboot args to kernel which then chokes.
551 So only enable the uboot arg checking/processing if users are sure
552 of uboot being in play.
554 config ARC_BUILTIN_DTB_NAME
555 string "Built in DTB"
557 Set the name of the DTB to embed in the vmlinux binary
558 Leaving it blank selects the minimal "skeleton" dtb
560 source "kernel/Kconfig.preempt"
562 menu "Executable file formats"
563 source "fs/Kconfig.binfmt"
566 endmenu # "ARC Architecture Configuration"
570 source "drivers/Kconfig"
572 source "arch/arc/Kconfig.debug"
573 source "security/Kconfig"
574 source "crypto/Kconfig"
576 source "kernel/power/Kconfig"