2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef _ASM_ARC_ARCREGS_H
10 #define _ASM_ARC_ARCREGS_H
14 /* Build Configuration Registers */
15 #define ARC_REG_VECBASE_BCR 0x68
17 /* status32 Bits Positions */
18 #define STATUS_H_BIT 0 /* CPU Halted */
19 #define STATUS_E1_BIT 1 /* Int 1 enable */
20 #define STATUS_E2_BIT 2 /* Int 2 enable */
21 #define STATUS_A1_BIT 3 /* Int 1 active */
22 #define STATUS_A2_BIT 4 /* Int 2 active */
23 #define STATUS_AE_BIT 5 /* Exception active */
24 #define STATUS_DE_BIT 6 /* PC is in delay slot */
25 #define STATUS_U_BIT 7 /* User/Kernel mode */
26 #define STATUS_L_BIT 12 /* Loop inhibit */
28 /* These masks correspond to the status word(STATUS_32) bits */
29 #define STATUS_H_MASK (1<<STATUS_H_BIT)
30 #define STATUS_E1_MASK (1<<STATUS_E1_BIT)
31 #define STATUS_E2_MASK (1<<STATUS_E2_BIT)
32 #define STATUS_A1_MASK (1<<STATUS_A1_BIT)
33 #define STATUS_A2_MASK (1<<STATUS_A2_BIT)
34 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
35 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
36 #define STATUS_U_MASK (1<<STATUS_U_BIT)
37 #define STATUS_L_MASK (1<<STATUS_L_BIT)
39 /* Auxiliary registers */
40 #define AUX_IDENTITY 4
41 #define AUX_INTR_VEC_BASE 0x25
42 #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
43 #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
44 #define AUX_IRQ_LV12 0x43 /* interrupt level register */
46 #define AUX_IENABLE 0x40c
47 #define AUX_ITRIGGER 0x40d
48 #define AUX_IPULSE 0x415
53 ******************************************************************
54 * Inline ASM macros to read/write AUX Regs
55 * Essentially invocation of lr/sr insns from "C"
60 #define read_aux_reg(reg) __builtin_arc_lr(reg)
62 /* gcc builtin sr needs reg param to be long immediate */
63 #define write_aux_reg(reg_immed, val) \
64 __builtin_arc_sr((unsigned int)val, reg_immed)
68 #define read_aux_reg(reg) \
71 __asm__ __volatile__( \
79 * Aux Reg address is specified as long immediate by caller
81 * write_aux_reg(0x69, some_val);
82 * This generates tightest code.
84 #define write_aux_reg(reg_imm, val) \
86 __asm__ __volatile__( \
89 : "ir"(val), "i"(reg_imm)); \
93 * Aux Reg address is specified in a variable
96 * write_aux_reg2(reg_num, some_val);
97 * This has to generate glue code to load the reg num from
98 * memory to a reg hence not recommended.
100 #define write_aux_reg2(reg_in_var, val) \
104 __asm__ __volatile__( \
105 " ld %0, [%2] \n\t" \
106 " sr %1, [%0] \n\t" \
108 : "r"(val), "memory"(®_in_var)); \
113 #endif /* __ASEMBLY__ */
115 #endif /* __KERNEL__ */
117 #endif /* _ASM_ARC_ARCREGS_H */