2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef _ASM_ARC_ARCREGS_H
10 #define _ASM_ARC_ARCREGS_H
14 /* Build Configuration Registers */
15 #define ARC_REG_VECBASE_BCR 0x68
17 /* status32 Bits Positions */
18 #define STATUS_H_BIT 0 /* CPU Halted */
19 #define STATUS_E1_BIT 1 /* Int 1 enable */
20 #define STATUS_E2_BIT 2 /* Int 2 enable */
21 #define STATUS_A1_BIT 3 /* Int 1 active */
22 #define STATUS_A2_BIT 4 /* Int 2 active */
23 #define STATUS_AE_BIT 5 /* Exception active */
24 #define STATUS_DE_BIT 6 /* PC is in delay slot */
25 #define STATUS_U_BIT 7 /* User/Kernel mode */
26 #define STATUS_L_BIT 12 /* Loop inhibit */
28 /* These masks correspond to the status word(STATUS_32) bits */
29 #define STATUS_H_MASK (1<<STATUS_H_BIT)
30 #define STATUS_E1_MASK (1<<STATUS_E1_BIT)
31 #define STATUS_E2_MASK (1<<STATUS_E2_BIT)
32 #define STATUS_A1_MASK (1<<STATUS_A1_BIT)
33 #define STATUS_A2_MASK (1<<STATUS_A2_BIT)
34 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
35 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
36 #define STATUS_U_MASK (1<<STATUS_U_BIT)
37 #define STATUS_L_MASK (1<<STATUS_L_BIT)
39 /* Auxiliary registers */
40 #define AUX_IDENTITY 4
41 #define AUX_INTR_VEC_BASE 0x25
42 #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
43 #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
44 #define AUX_IRQ_LV12 0x43 /* interrupt level register */
46 #define AUX_IENABLE 0x40c
47 #define AUX_ITRIGGER 0x40d
48 #define AUX_IPULSE 0x415
50 /* Timer related Aux registers */
51 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
52 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
53 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
54 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
55 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
56 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
58 #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
59 #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
61 /* Instruction cache related Auxiliary registers */
62 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
63 #define ARC_REG_IC_IVIC 0x10
64 #define ARC_REG_IC_CTRL 0x11
65 #define ARC_REG_IC_IVIL 0x19
66 #if (CONFIG_ARC_MMU_VER > 2)
67 #define ARC_REG_IC_PTAG 0x1E
70 /* Bit val in IC_CTRL */
71 #define IC_CTRL_CACHE_DISABLE 0x1
73 /* Data cache related Auxiliary registers */
74 #define ARC_REG_DC_BCR 0x72
75 #define ARC_REG_DC_IVDC 0x47
76 #define ARC_REG_DC_CTRL 0x48
77 #define ARC_REG_DC_IVDL 0x4A
78 #define ARC_REG_DC_FLSH 0x4B
79 #define ARC_REG_DC_FLDL 0x4C
80 #if (CONFIG_ARC_MMU_VER > 2)
81 #define ARC_REG_DC_PTAG 0x5C
84 /* Bit val in DC_CTRL */
85 #define DC_CTRL_INV_MODE_FLUSH 0x40
86 #define DC_CTRL_FLUSH_STATUS 0x100
88 /* MMU Management regs */
89 #define ARC_REG_PID 0x409
90 #define ARC_REG_SCRATCH_DATA0 0x418
92 /* Bits in MMU PID register */
93 #define MMU_ENABLE (1 << 31) /* Enable MMU for process */
96 * Floating Pt Registers
97 * Status regs are read-only (build-time) so need not be saved/restored
99 #define ARC_AUX_FP_STAT 0x300
100 #define ARC_AUX_DPFP_1L 0x301
101 #define ARC_AUX_DPFP_1H 0x302
102 #define ARC_AUX_DPFP_2L 0x303
103 #define ARC_AUX_DPFP_2H 0x304
104 #define ARC_AUX_DPFP_STAT 0x305
109 ******************************************************************
110 * Inline ASM macros to read/write AUX Regs
111 * Essentially invocation of lr/sr insns from "C"
116 #define read_aux_reg(reg) __builtin_arc_lr(reg)
118 /* gcc builtin sr needs reg param to be long immediate */
119 #define write_aux_reg(reg_immed, val) \
120 __builtin_arc_sr((unsigned int)val, reg_immed)
124 #define read_aux_reg(reg) \
126 unsigned int __ret; \
127 __asm__ __volatile__( \
135 * Aux Reg address is specified as long immediate by caller
137 * write_aux_reg(0x69, some_val);
138 * This generates tightest code.
140 #define write_aux_reg(reg_imm, val) \
142 __asm__ __volatile__( \
145 : "ir"(val), "i"(reg_imm)); \
149 * Aux Reg address is specified in a variable
152 * write_aux_reg2(reg_num, some_val);
153 * This has to generate glue code to load the reg num from
154 * memory to a reg hence not recommended.
156 #define write_aux_reg2(reg_in_var, val) \
160 __asm__ __volatile__( \
161 " ld %0, [%2] \n\t" \
162 " sr %1, [%0] \n\t" \
164 : "r"(val), "memory"(®_in_var)); \
169 #define READ_BCR(reg, into) \
172 tmp = read_aux_reg(reg); \
173 if (sizeof(tmp) == sizeof(into)) { \
174 into = *((typeof(into) *)&tmp); \
176 extern void bogus_undefined(void); \
181 #define WRITE_BCR(reg, into) \
184 if (sizeof(tmp) == sizeof(into)) { \
185 tmp = (*(unsigned int *)(into)); \
186 write_aux_reg(reg, tmp); \
188 extern void bogus_undefined(void); \
194 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
195 /* These DPFP regs need to be saved/restored across ctx-sw */
204 ***************************************************************
205 * Build Configuration Registers, with encoded hardware config
209 #ifdef CONFIG_CPU_BIG_ENDIAN
210 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
212 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
217 *******************************************************************
218 * Generic structures to hold build configuration used at runtime
221 struct cpuinfo_arc_cache {
222 unsigned int has_aliasing, sz, line_len, assoc, ver;
226 struct cpuinfo_arc_cache icache, dcache;
229 extern struct cpuinfo_arc cpuinfo_arc700[];
231 #endif /* __ASEMBLY__ */
233 #endif /* __KERNEL__ */
235 #endif /* _ASM_ARC_ARCREGS_H */