2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef _ASM_ARC_ATOMIC_H
10 #define _ASM_ARC_ATOMIC_H
14 #include <linux/types.h>
15 #include <linux/compiler.h>
16 #include <asm/cmpxchg.h>
17 #include <asm/barrier.h>
20 #define ATOMIC_INIT(i) { (i) }
22 #ifndef CONFIG_ARC_PLAT_EZNPS
24 #define atomic_read(v) READ_ONCE((v)->counter)
26 #ifdef CONFIG_ARC_HAS_LLSC
28 #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
30 #define ATOMIC_OP(op, c_op, asm_op) \
31 static inline void atomic_##op(int i, atomic_t *v) \
35 __asm__ __volatile__( \
36 "1: llock %[val], [%[ctr]] \n" \
37 " " #asm_op " %[val], %[val], %[i] \n" \
38 " scond %[val], [%[ctr]] \n" \
40 : [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
41 : [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
46 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
47 static inline int atomic_##op##_return(int i, atomic_t *v) \
52 * Explicit full memory barrier needed before/after as \
53 * LLOCK/SCOND thmeselves don't provide any such semantics \
57 __asm__ __volatile__( \
58 "1: llock %[val], [%[ctr]] \n" \
59 " " #asm_op " %[val], %[val], %[i] \n" \
60 " scond %[val], [%[ctr]] \n" \
63 : [ctr] "r" (&v->counter), \
72 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
73 static inline int atomic_fetch_##op(int i, atomic_t *v) \
75 unsigned int val, orig; \
78 * Explicit full memory barrier needed before/after as \
79 * LLOCK/SCOND thmeselves don't provide any such semantics \
83 __asm__ __volatile__( \
84 "1: llock %[orig], [%[ctr]] \n" \
85 " " #asm_op " %[val], %[orig], %[i] \n" \
86 " scond %[val], [%[ctr]] \n" \
88 : [val] "=&r" (val), \
90 : [ctr] "r" (&v->counter), \
99 #else /* !CONFIG_ARC_HAS_LLSC */
103 /* violating atomic_xxx API locking protocol in UP for optimization sake */
104 #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
108 static inline void atomic_set(atomic_t *v, int i)
111 * Independent of hardware support, all of the atomic_xxx() APIs need
112 * to follow the same locking rules to make sure that a "hardware"
113 * atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
116 * Thus atomic_set() despite being 1 insn (and seemingly atomic)
117 * requires the locking.
121 atomic_ops_lock(flags);
122 WRITE_ONCE(v->counter, i);
123 atomic_ops_unlock(flags);
129 * Non hardware assisted Atomic-R-M-W
130 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
133 #define ATOMIC_OP(op, c_op, asm_op) \
134 static inline void atomic_##op(int i, atomic_t *v) \
136 unsigned long flags; \
138 atomic_ops_lock(flags); \
140 atomic_ops_unlock(flags); \
143 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
144 static inline int atomic_##op##_return(int i, atomic_t *v) \
146 unsigned long flags; \
147 unsigned long temp; \
150 * spin lock/unlock provides the needed smp_mb() before/after \
152 atomic_ops_lock(flags); \
156 atomic_ops_unlock(flags); \
161 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
162 static inline int atomic_fetch_##op(int i, atomic_t *v) \
164 unsigned long flags; \
165 unsigned long orig; \
168 * spin lock/unlock provides the needed smp_mb() before/after \
170 atomic_ops_lock(flags); \
173 atomic_ops_unlock(flags); \
178 #endif /* !CONFIG_ARC_HAS_LLSC */
180 #define ATOMIC_OPS(op, c_op, asm_op) \
181 ATOMIC_OP(op, c_op, asm_op) \
182 ATOMIC_OP_RETURN(op, c_op, asm_op) \
183 ATOMIC_FETCH_OP(op, c_op, asm_op)
185 ATOMIC_OPS(add, +=, add)
186 ATOMIC_OPS(sub, -=, sub)
188 #define atomic_andnot atomic_andnot
191 #define ATOMIC_OPS(op, c_op, asm_op) \
192 ATOMIC_OP(op, c_op, asm_op) \
193 ATOMIC_FETCH_OP(op, c_op, asm_op)
195 ATOMIC_OPS(and, &=, and)
196 ATOMIC_OPS(andnot, &= ~, bic)
197 ATOMIC_OPS(or, |=, or)
198 ATOMIC_OPS(xor, ^=, xor)
200 #else /* CONFIG_ARC_PLAT_EZNPS */
202 static inline int atomic_read(const atomic_t *v)
206 __asm__ __volatile__(
214 static inline void atomic_set(atomic_t *v, int i)
216 __asm__ __volatile__(
219 : "r"(i), "r"(&v->counter)
223 #define ATOMIC_OP(op, c_op, asm_op) \
224 static inline void atomic_##op(int i, atomic_t *v) \
226 __asm__ __volatile__( \
231 : "r"(i), "r"(&v->counter), "i"(asm_op) \
232 : "r2", "r3", "memory"); \
235 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
236 static inline int atomic_##op##_return(int i, atomic_t *v) \
238 unsigned int temp = i; \
240 /* Explicit full memory barrier needed before/after */ \
243 __asm__ __volatile__( \
249 : "r"(&v->counter), "i"(asm_op) \
250 : "r2", "r3", "memory"); \
259 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
260 static inline int atomic_fetch_##op(int i, atomic_t *v) \
262 unsigned int temp = i; \
264 /* Explicit full memory barrier needed before/after */ \
267 __asm__ __volatile__( \
273 : "r"(&v->counter), "i"(asm_op) \
274 : "r2", "r3", "memory"); \
281 #define ATOMIC_OPS(op, c_op, asm_op) \
282 ATOMIC_OP(op, c_op, asm_op) \
283 ATOMIC_OP_RETURN(op, c_op, asm_op) \
284 ATOMIC_FETCH_OP(op, c_op, asm_op)
286 ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
287 #define atomic_sub(i, v) atomic_add(-(i), (v))
288 #define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
289 #define atomic_fetch_sub(i, v) atomic_fetch_add(-(i), (v))
292 #define ATOMIC_OPS(op, c_op, asm_op) \
293 ATOMIC_OP(op, c_op, asm_op) \
294 ATOMIC_FETCH_OP(op, c_op, asm_op)
296 ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
297 #define atomic_andnot(mask, v) atomic_and(~(mask), (v))
298 #define atomic_fetch_andnot(mask, v) atomic_fetch_and(~(mask), (v))
299 ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
300 ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
302 #endif /* CONFIG_ARC_PLAT_EZNPS */
305 #undef ATOMIC_FETCH_OP
306 #undef ATOMIC_OP_RETURN
310 * __atomic_add_unless - add unless the number is a given value
311 * @v: pointer of type atomic_t
312 * @a: the amount to add to v...
313 * @u: ...unless v is equal to u.
315 * Atomically adds @a to @v, so long as it was not @u.
316 * Returns the old value of @v
318 #define __atomic_add_unless(v, a, u) \
323 * Explicit full memory barrier needed before/after as \
324 * LLOCK/SCOND thmeselves don't provide any such semantics \
328 c = atomic_read(v); \
329 while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c)\
337 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
339 #define atomic_inc(v) atomic_add(1, v)
340 #define atomic_dec(v) atomic_sub(1, v)
342 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
343 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
344 #define atomic_inc_return(v) atomic_add_return(1, (v))
345 #define atomic_dec_return(v) atomic_sub_return(1, (v))
346 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
348 #define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0)
351 #ifdef CONFIG_GENERIC_ATOMIC64
353 #include <asm-generic/atomic64.h>
355 #else /* Kconfig ensures this is only enabled with needed h/w assist */
358 * ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
359 * - The address HAS to be 64-bit aligned
360 * - There are 2 semantics involved here:
361 * = exclusive implies no interim update between load/store to same addr
362 * = both words are observed/updated together: this is guaranteed even
363 * for regular 64-bit load (LDD) / store (STD). Thus atomic64_set()
364 * is NOT required to use LLOCKD+SCONDD, STD suffices
371 #define ATOMIC64_INIT(a) { (a) }
373 static inline long long atomic64_read(const atomic64_t *v)
375 unsigned long long val;
377 __asm__ __volatile__(
385 static inline void atomic64_set(atomic64_t *v, long long a)
388 * This could have been a simple assignment in "C" but would need
389 * explicit volatile. Otherwise gcc optimizers could elide the store
390 * which borked atomic64 self-test
391 * In the inline asm version, memory clobber needed for exact same
392 * reason, to tell gcc about the store.
394 * This however is not needed for sibling atomic64_add() etc since both
395 * load/store are explicitly done in inline asm. As long as API is used
396 * for each access, gcc has no way to optimize away any load/store
398 __asm__ __volatile__(
401 : "r"(a), "r"(&v->counter)
405 #define ATOMIC64_OP(op, op1, op2) \
406 static inline void atomic64_##op(long long a, atomic64_t *v) \
408 unsigned long long val; \
410 __asm__ __volatile__( \
412 " llockd %0, [%1] \n" \
413 " " #op1 " %L0, %L0, %L2 \n" \
414 " " #op2 " %H0, %H0, %H2 \n" \
415 " scondd %0, [%1] \n" \
418 : "r"(&v->counter), "ir"(a) \
422 #define ATOMIC64_OP_RETURN(op, op1, op2) \
423 static inline long long atomic64_##op##_return(long long a, atomic64_t *v) \
425 unsigned long long val; \
429 __asm__ __volatile__( \
431 " llockd %0, [%1] \n" \
432 " " #op1 " %L0, %L0, %L2 \n" \
433 " " #op2 " %H0, %H0, %H2 \n" \
434 " scondd %0, [%1] \n" \
437 : "r"(&v->counter), "ir"(a) \
438 : "cc"); /* memory clobber comes from smp_mb() */ \
445 #define ATOMIC64_FETCH_OP(op, op1, op2) \
446 static inline long long atomic64_fetch_##op(long long a, atomic64_t *v) \
448 unsigned long long val, orig; \
452 __asm__ __volatile__( \
454 " llockd %0, [%2] \n" \
455 " " #op1 " %L1, %L0, %L3 \n" \
456 " " #op2 " %H1, %H0, %H3 \n" \
457 " scondd %1, [%2] \n" \
459 : "=&r"(orig), "=&r"(val) \
460 : "r"(&v->counter), "ir"(a) \
461 : "cc"); /* memory clobber comes from smp_mb() */ \
468 #define ATOMIC64_OPS(op, op1, op2) \
469 ATOMIC64_OP(op, op1, op2) \
470 ATOMIC64_OP_RETURN(op, op1, op2) \
471 ATOMIC64_FETCH_OP(op, op1, op2)
473 #define atomic64_andnot atomic64_andnot
475 ATOMIC64_OPS(add, add.f, adc)
476 ATOMIC64_OPS(sub, sub.f, sbc)
477 ATOMIC64_OPS(and, and, and)
478 ATOMIC64_OPS(andnot, bic, bic)
479 ATOMIC64_OPS(or, or, or)
480 ATOMIC64_OPS(xor, xor, xor)
483 #undef ATOMIC64_FETCH_OP
484 #undef ATOMIC64_OP_RETURN
487 static inline long long
488 atomic64_cmpxchg(atomic64_t *ptr, long long expected, long long new)
494 __asm__ __volatile__(
495 "1: llockd %0, [%1] \n"
496 " brne %L0, %L2, 2f \n"
497 " brne %H0, %H2, 2f \n"
498 " scondd %3, [%1] \n"
502 : "r"(ptr), "ir"(expected), "r"(new)
503 : "cc"); /* memory clobber comes from smp_mb() */
510 static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
516 __asm__ __volatile__(
517 "1: llockd %0, [%1] \n"
518 " scondd %2, [%1] \n"
523 : "cc"); /* memory clobber comes from smp_mb() */
531 * atomic64_dec_if_positive - decrement by 1 if old value positive
532 * @v: pointer of type atomic64_t
534 * The function returns the old value of *v minus 1, even if
535 * the atomic variable, v, was not decremented.
538 static inline long long atomic64_dec_if_positive(atomic64_t *v)
544 __asm__ __volatile__(
545 "1: llockd %0, [%1] \n"
546 " sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n"
547 " sub.c %H0, %H0, 1 # if C set, w1 - 1\n"
548 " brlt %H0, 0, 2f \n"
549 " scondd %0, [%1] \n"
554 : "cc"); /* memory clobber comes from smp_mb() */
562 * atomic64_add_unless - add unless the number is a given value
563 * @v: pointer of type atomic64_t
564 * @a: the amount to add to v...
565 * @u: ...unless v is equal to u.
567 * if (v != u) { v += a; ret = 1} else {ret = 0}
568 * Returns 1 iff @v was not @u (i.e. if add actually happened)
570 static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
577 __asm__ __volatile__(
578 "1: llockd %0, [%2] \n"
580 " brne %L0, %L4, 2f # continue to add since v != u \n"
581 " breq.d %H0, %H4, 3f # return since v == u \n"
584 " add.f %L0, %L0, %L3 \n"
585 " adc %H0, %H0, %H3 \n"
586 " scondd %0, [%2] \n"
589 : "=&r"(val), "=&r" (op_done)
590 : "r"(&v->counter), "r"(a), "r"(u)
591 : "cc"); /* memory clobber comes from smp_mb() */
598 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
599 #define atomic64_inc(v) atomic64_add(1LL, (v))
600 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
601 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
602 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
603 #define atomic64_dec(v) atomic64_sub(1LL, (v))
604 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
605 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
606 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
608 #endif /* !CONFIG_GENERIC_ATOMIC64 */
610 #endif /* !__ASSEMBLY__ */