2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #ifndef _LINUX_BITOPS_H
13 #error only <linux/bitops.h> can be included directly
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <asm/barrier.h>
21 #ifndef CONFIG_ARC_HAS_LLSC
25 #if defined(CONFIG_ARC_HAS_LLSC)
28 * Hardware assisted Atomic-R-M-W
31 #define BIT_OP(op, c_op, asm_op) \
32 static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
39 * ARC ISA micro-optimization: \
41 * Instructions dealing with bitpos only consider lower 5 bits \
42 * e.g (x << 33) is handled like (x << 1) by ASL instruction \
43 * (mem pointer still needs adjustment to point to next word) \
45 * Hence the masking to clamp @nr arg can be elided in general. \
47 * However if @nr is a constant (above assumed in a register), \
48 * and greater than 31, gcc can optimize away (x << 33) to 0, \
49 * as overflow, given the 32-bit ISA. Thus masking needs to be \
50 * done for const @nr, but no code is generated due to gcc \
53 if (__builtin_constant_p(nr)) \
56 __asm__ __volatile__( \
57 "1: llock %0, [%1] \n" \
58 " " #asm_op " %0, %0, %2 \n" \
59 " scond %0, [%1] \n" \
61 : "=&r"(temp) /* Early clobber, to prevent reg reuse */ \
62 : "r"(m), /* Not "m": llock only supports reg direct addr mode */ \
71 * set it and return 0 (old value)
73 * return 1 (old value).
75 * Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
76 * and the old value of bit is returned
78 #define TEST_N_BIT_OP(op, c_op, asm_op) \
79 static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
81 unsigned long old, temp; \
85 if (__builtin_constant_p(nr)) \
89 * Explicit full memory barrier needed before/after as \
90 * LLOCK/SCOND themselves don't provide any such smenatic \
94 __asm__ __volatile__( \
95 "1: llock %0, [%2] \n" \
96 " " #asm_op " %1, %0, %3 \n" \
97 " scond %1, [%2] \n" \
99 : "=&r"(old), "=&r"(temp) \
105 return (old & (1 << nr)) != 0; \
108 #else /* !CONFIG_ARC_HAS_LLSC */
111 * Non hardware assisted Atomic-R-M-W
112 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
114 * There's "significant" micro-optimization in writing our own variants of
115 * bitops (over generic variants)
117 * (1) The generic APIs have "signed" @nr while we have it "unsigned"
118 * This avoids extra code to be generated for pointer arithmatic, since
119 * is "not sure" that index is NOT -ve
120 * (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc
121 * only consider bottom 5 bits of @nr, so NO need to mask them off.
122 * (GCC Quirk: however for constant @nr we still need to do the masking
126 #define BIT_OP(op, c_op, asm_op) \
127 static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
129 unsigned long temp, flags; \
132 if (__builtin_constant_p(nr)) \
136 * spin lock/unlock provide the needed smp_mb() before/after \
138 bitops_lock(flags); \
141 *m = temp c_op (1UL << nr); \
143 bitops_unlock(flags); \
146 #define TEST_N_BIT_OP(op, c_op, asm_op) \
147 static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
149 unsigned long old, flags; \
152 if (__builtin_constant_p(nr)) \
155 bitops_lock(flags); \
158 *m = old c_op (1 << nr); \
160 bitops_unlock(flags); \
162 return (old & (1 << nr)) != 0; \
165 #endif /* CONFIG_ARC_HAS_LLSC */
167 /***************************************
168 * Non atomic variants
169 **************************************/
171 #define __BIT_OP(op, c_op, asm_op) \
172 static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \
174 unsigned long temp; \
177 if (__builtin_constant_p(nr)) \
181 *m = temp c_op (1UL << nr); \
184 #define __TEST_N_BIT_OP(op, c_op, asm_op) \
185 static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
190 if (__builtin_constant_p(nr)) \
194 *m = old c_op (1 << nr); \
196 return (old & (1 << nr)) != 0; \
199 #define BIT_OPS(op, c_op, asm_op) \
201 /* set_bit(), clear_bit(), change_bit() */ \
202 BIT_OP(op, c_op, asm_op) \
204 /* test_and_set_bit(), test_and_clear_bit(), test_and_change_bit() */\
205 TEST_N_BIT_OP(op, c_op, asm_op) \
207 /* __set_bit(), __clear_bit(), __change_bit() */ \
208 __BIT_OP(op, c_op, asm_op) \
210 /* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
211 __TEST_N_BIT_OP(op, c_op, asm_op)
213 BIT_OPS(set, |, bset)
214 BIT_OPS(clear, & ~, bclr)
215 BIT_OPS(change, ^, bxor)
218 * This routine doesn't need to be atomic.
221 test_bit(unsigned int nr, const volatile unsigned long *addr)
227 if (__builtin_constant_p(nr))
232 return ((mask & *addr) != 0);
235 #ifdef CONFIG_ISA_ARCOMPACT
238 * Count the number of zeros, starting from MSB
239 * Helper for fls( ) friends
240 * This is a pure count, so (1-32) or (0-31) doesn't apply
241 * It could be 0 to 32, based on num of 0's in there
242 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
244 static inline __attribute__ ((const)) int clz(unsigned int x)
248 __asm__ __volatile__(
251 " add.p %0, %0, 1 \n"
259 static inline int constant_fls(int x)
265 if (!(x & 0xffff0000u)) {
269 if (!(x & 0xff000000u)) {
273 if (!(x & 0xf0000000u)) {
277 if (!(x & 0xc0000000u)) {
281 if (!(x & 0x80000000u)) {
289 * fls = Find Last Set in word
291 * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
293 static inline __attribute__ ((const)) int fls(unsigned long x)
295 if (__builtin_constant_p(x))
296 return constant_fls(x);
302 * __fls: Similar to fls, but zero based (0-31)
304 static inline __attribute__ ((const)) int __fls(unsigned long x)
313 * ffs = Find First Set in word (LSB to MSB)
314 * @result: [1-32], 0 if all 0's
316 #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
319 * __ffs: Similar to ffs, but zero based (0-31)
321 static inline __attribute__ ((const)) int __ffs(unsigned long word)
326 return ffs(word) - 1;
329 #else /* CONFIG_ISA_ARCV2 */
332 * fls = Find Last Set in word
334 * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
336 static inline __attribute__ ((const)) int fls(unsigned long x)
341 " fls.f %0, %1 \n" /* 0:31; 0(Z) if src 0 */
342 " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */
343 : "=r"(n) /* Early clobber not needed */
351 * __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set
353 static inline __attribute__ ((const)) int __fls(unsigned long x)
355 /* FLS insn has exactly same semantics as the API */
356 return __builtin_arc_fls(x);
360 * ffs = Find First Set in word (LSB to MSB)
361 * @result: [1-32], 0 if all 0's
363 static inline __attribute__ ((const)) int ffs(unsigned long x)
368 " ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */
369 " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */
370 " mov.z %0, 0 \n" /* 31(Z)-> 0 */
371 : "=r"(n) /* Early clobber not needed */
379 * __ffs: Similar to ffs, but zero based (0-31)
381 static inline __attribute__ ((const)) int __ffs(unsigned long x)
386 " ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */
387 " mov.z %0, 0 \n" /* 31(Z)-> 0 */
396 #endif /* CONFIG_ISA_ARCOMPACT */
399 * ffz = Find First Zero in word.
400 * @return:[0-31], 32 if all 1's
402 #define ffz(x) __ffs(~(x))
404 #include <asm-generic/bitops/hweight.h>
405 #include <asm-generic/bitops/fls64.h>
406 #include <asm-generic/bitops/sched.h>
407 #include <asm-generic/bitops/lock.h>
409 #include <asm-generic/bitops/find.h>
410 #include <asm-generic/bitops/le.h>
411 #include <asm-generic/bitops/ext2-atomic-setbit.h>
413 #endif /* !__ASSEMBLY__ */