2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef __ARC_ASM_CACHE_H
10 #define __ARC_ASM_CACHE_H
12 /* In case $$ not config, setup a dummy number for rest of kernel */
13 #ifndef CONFIG_ARC_CACHE_LINE_SHIFT
14 #define L1_CACHE_SHIFT 6
16 #define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT
19 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
20 #define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))
23 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
24 * Ideal for wiring memory mapped peripherals as we don't need to do
25 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
27 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
31 /* Uncached access macros */
32 #define arc_read_uncached_32(ptr) \
35 __asm__ __volatile__( \
36 " ld.di %0, [%1] \n" \
42 #define arc_write_uncached_32(ptr, data)\
44 __asm__ __volatile__( \
45 " st.di %0, [%1] \n" \
47 : "r"(data), "r"(ptr)); \
50 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
52 extern void arc_cache_init(void);
53 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
54 extern void read_decode_cache_bcr(void);
56 extern int ioc_exists;
58 #endif /* !__ASSEMBLY__ */
60 /* Instruction cache related Auxiliary registers */
61 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
62 #define ARC_REG_IC_IVIC 0x10
63 #define ARC_REG_IC_CTRL 0x11
64 #define ARC_REG_IC_IVIL 0x19
65 #if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)
66 #define ARC_REG_IC_PTAG 0x1E
68 #define ARC_REG_IC_PTAG_HI 0x1F
70 /* Bit val in IC_CTRL */
71 #define IC_CTRL_CACHE_DISABLE 0x1
73 /* Data cache related Auxiliary registers */
74 #define ARC_REG_DC_BCR 0x72 /* Build Config reg */
75 #define ARC_REG_DC_IVDC 0x47
76 #define ARC_REG_DC_CTRL 0x48
77 #define ARC_REG_DC_IVDL 0x4A
78 #define ARC_REG_DC_FLSH 0x4B
79 #define ARC_REG_DC_FLDL 0x4C
80 #define ARC_REG_DC_PTAG 0x5C
81 #define ARC_REG_DC_PTAG_HI 0x5F
83 /* Bit val in DC_CTRL */
84 #define DC_CTRL_INV_MODE_FLUSH 0x40
85 #define DC_CTRL_FLUSH_STATUS 0x100
87 /*System-level cache (L2 cache) related Auxiliary registers */
88 #define ARC_REG_SLC_CFG 0x901
89 #define ARC_REG_SLC_CTRL 0x903
90 #define ARC_REG_SLC_FLUSH 0x904
91 #define ARC_REG_SLC_INVALIDATE 0x905
92 #define ARC_REG_SLC_RGN_START 0x914
93 #define ARC_REG_SLC_RGN_END 0x916
95 /* Bit val in SLC_CONTROL */
96 #define SLC_CTRL_IM 0x040
97 #define SLC_CTRL_DISABLE 0x001
98 #define SLC_CTRL_BUSY 0x100
99 #define SLC_CTRL_RGN_OP_INV 0x200
101 /* IO coherency related Auxiliary registers */
102 #define ARC_REG_IO_COH_ENABLE 0x500
103 #define ARC_REG_IO_COH_PARTIAL 0x501
104 #define ARC_REG_IO_COH_AP0_BASE 0x508
105 #define ARC_REG_IO_COH_AP0_SIZE 0x509
107 #endif /* _ASM_CACHE_H */