4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CLONE_BACKWARDS
11 select CPU_PM if (SUSPEND || CPU_IDLE)
12 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
13 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
14 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
15 select GENERIC_IDLE_POLL_SETUP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SCHED_CLOCK
20 select GENERIC_SMP_IDLE_THREAD
21 select GENERIC_STRNCPY_FROM_USER
22 select GENERIC_STRNLEN_USER
23 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
29 select HAVE_CONTEXT_TRACKING
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_DEBUG_KMEMLEAK
32 select HAVE_DMA_API_DEBUG
34 select HAVE_DMA_CONTIGUOUS if MMU
35 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
36 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
37 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
38 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
39 select HAVE_GENERIC_DMA_COHERENT
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZ4
45 select HAVE_KERNEL_LZMA
46 select HAVE_KERNEL_LZO
48 select HAVE_KPROBES if !XIP_KERNEL
49 select HAVE_KRETPROBES if (HAVE_KPROBES)
51 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
52 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
53 select HAVE_PERF_EVENTS
54 select HAVE_REGS_AND_STACK_ACCESS_API
55 select HAVE_SYSCALL_TRACEPOINTS
57 select IRQ_FORCED_THREADING
59 select MODULES_USE_ELF_REL
61 select OLD_SIGSUSPEND3
62 select PERF_USE_VMALLOC
64 select SYS_SUPPORTS_APM_EMULATION
65 # Above selects are sorted alphabetically; please add new ones
66 # according to that. Thanks.
68 The ARM series is a line of low-power-consumption RISC chip designs
69 licensed by ARM Ltd and targeted at embedded applications and
70 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
71 manufactured, but legacy ARM-based PC hardware remains popular in
72 Europe. There is an ARM Linux project with a web page at
73 <http://www.arm.linux.org.uk/>.
75 config ARM_HAS_SG_CHAIN
78 config NEED_SG_DMA_LENGTH
81 config ARM_DMA_USE_IOMMU
83 select ARM_HAS_SG_CHAIN
84 select NEED_SG_DMA_LENGTH
88 config ARM_DMA_IOMMU_ALIGNMENT
89 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
93 DMA mapping framework by default aligns all buffers to the smallest
94 PAGE_SIZE order which is greater than or equal to the requested buffer
95 size. This works well for buffers up to a few hundreds kilobytes, but
96 for larger buffers it just a waste of address space. Drivers which has
97 relatively small addressing window (like 64Mib) might run out of
98 virtual space with just a few allocations.
100 With this parameter you can specify the maximum PAGE_SIZE order for
101 DMA IOMMU buffers. Larger buffers will be aligned only to this
102 specified order. The order is expressed as a power of two multiplied
110 config MIGHT_HAVE_PCI
113 config SYS_SUPPORTS_APM_EMULATION
118 select GENERIC_ALLOCATOR
129 The Extended Industry Standard Architecture (EISA) bus was
130 developed as an open alternative to the IBM MicroChannel bus.
132 The EISA bus provided some of the features of the IBM MicroChannel
133 bus while maintaining backward compatibility with cards made for
134 the older ISA bus. The EISA bus saw limited use between 1988 and
135 1995 when it was made obsolete by the PCI bus.
137 Say Y here if you are building a kernel for an EISA-based machine.
144 config STACKTRACE_SUPPORT
148 config HAVE_LATENCYTOP_SUPPORT
153 config LOCKDEP_SUPPORT
157 config TRACE_IRQFLAGS_SUPPORT
161 config RWSEM_GENERIC_SPINLOCK
165 config RWSEM_XCHGADD_ALGORITHM
168 config ARCH_HAS_ILOG2_U32
171 config ARCH_HAS_ILOG2_U64
174 config ARCH_HAS_CPUFREQ
177 Internal node to signify that the ARCH has CPUFREQ support
178 and that the relevant menu configurations are displayed for
181 config ARCH_HAS_BANDGAP
184 config GENERIC_HWEIGHT
188 config GENERIC_CALIBRATE_DELAY
192 config ARCH_MAY_HAVE_PC_FDC
198 config NEED_DMA_MAP_STATE
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
266 default DRAM_BASE if !MMU
268 Please provide the physical address corresponding to the
269 location of main memory in your system.
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
282 bool "MMU-based Paged Memory Management Support"
285 Select if you want MMU-based virtualised addressing space
286 support by paged memory management. If unsure, say 'Y'.
289 # The "ARM system type" choice list is ordered alphabetically by option
290 # text. Please add new entries in the option alphabetic order.
293 prompt "ARM system type"
294 default ARCH_VERSATILE if !MMU
295 default ARCH_MULTIPLATFORM if MMU
297 config ARCH_MULTIPLATFORM
298 bool "Allow multiple platforms to be selected"
300 select ARM_PATCH_PHYS_VIRT
303 select MULTI_IRQ_HANDLER
307 config ARCH_INTEGRATOR
308 bool "ARM Ltd. Integrator family"
309 select ARCH_HAS_CPUFREQ
312 select COMMON_CLK_VERSATILE
313 select GENERIC_CLOCKEVENTS
316 select MULTI_IRQ_HANDLER
317 select NEED_MACH_MEMORY_H
318 select PLAT_VERSATILE
321 select VERSATILE_FPGA_IRQ
323 Support for ARM's Integrator platform.
326 bool "ARM Ltd. RealView family"
327 select ARCH_WANT_OPTIONAL_GPIOLIB
329 select ARM_TIMER_SP804
331 select COMMON_CLK_VERSATILE
332 select GENERIC_CLOCKEVENTS
333 select GPIO_PL061 if GPIOLIB
335 select NEED_MACH_MEMORY_H
336 select PLAT_VERSATILE
337 select PLAT_VERSATILE_CLCD
339 This enables support for ARM Ltd RealView boards.
341 config ARCH_VERSATILE
342 bool "ARM Ltd. Versatile family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
348 select GENERIC_CLOCKEVENTS
349 select HAVE_MACH_CLKDEV
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_CLCD
353 select PLAT_VERSATILE_CLOCK
354 select VERSATILE_FPGA_IRQ
356 This enables support for ARM Ltd Versatile board.
360 select ARCH_REQUIRE_GPIOLIB
363 select NEED_MACH_GPIO_H
364 select NEED_MACH_IO_H if PCCARD
366 select PINCTRL_AT91 if USE_OF
368 This enables support for systems based on Atmel
369 AT91RM9200 and AT91SAM9* processors.
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
380 select MULTI_IRQ_HANDLER
383 Support for Cirrus Logic 711x/721x/731x based boards.
386 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
390 select GENERIC_CLOCKEVENTS
391 select NEED_MACH_GPIO_H
393 Support for the Cortina Systems Gemini family SoCs
397 select ARCH_USES_GETTIMEOFFSET
400 select NEED_MACH_IO_H
401 select NEED_MACH_MEMORY_H
404 This is an evaluation board for the StrongARM processor available
405 from Digital. It has limited hardware on-board, including an
406 Ethernet interface, two PCMCIA sockets, two serial ports and a
411 select ARCH_HAS_HOLES_MEMORYMODEL
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
418 select NEED_MACH_MEMORY_H
420 This enables support for the Cirrus EP93xx series of CPUs.
422 config ARCH_FOOTBRIDGE
426 select GENERIC_CLOCKEVENTS
428 select NEED_MACH_IO_H if !MMU
429 select NEED_MACH_MEMORY_H
431 Support for systems based on the DC21285 companion chip
432 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
435 bool "Hilscher NetX based"
439 select GENERIC_CLOCKEVENTS
441 This enables support for systems based on the Hilscher NetX Soc
447 select NEED_MACH_MEMORY_H
448 select NEED_RET_TO_USER
453 Support for Intel's IOP13XX (XScale) family of processors.
458 select ARCH_REQUIRE_GPIOLIB
460 select NEED_MACH_GPIO_H
461 select NEED_RET_TO_USER
465 Support for Intel's 80219 and IOP32X (XScale) family of
471 select ARCH_REQUIRE_GPIOLIB
473 select NEED_MACH_GPIO_H
474 select NEED_RET_TO_USER
478 Support for Intel's IOP33X (XScale) family of processors.
483 select ARCH_HAS_DMA_SET_COHERENT_MASK
484 select ARCH_REQUIRE_GPIOLIB
487 select DMABOUNCE if PCI
488 select GENERIC_CLOCKEVENTS
489 select MIGHT_HAVE_PCI
490 select NEED_MACH_IO_H
491 select USB_EHCI_BIG_ENDIAN_DESC
492 select USB_EHCI_BIG_ENDIAN_MMIO
494 Support for Intel's IXP4XX (XScale) family of processors.
498 select ARCH_REQUIRE_GPIOLIB
500 select GENERIC_CLOCKEVENTS
501 select MIGHT_HAVE_PCI
505 select PLAT_ORION_LEGACY
506 select USB_ARCH_HAS_EHCI
508 Support for the Marvell Dove SoC 88AP510
511 bool "Marvell Kirkwood"
512 select ARCH_HAS_CPUFREQ
513 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
520 select PINCTRL_KIRKWOOD
521 select PLAT_ORION_LEGACY
523 Support for the following Marvell Kirkwood series SoCs:
524 88F6180, 88F6192 and 88F6281.
527 bool "Marvell MV78xx0"
528 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 select PLAT_ORION_LEGACY
535 Support for the following Marvell MV78xx0 series SoCs:
541 select ARCH_REQUIRE_GPIOLIB
543 select GENERIC_CLOCKEVENTS
546 select PLAT_ORION_LEGACY
548 Support for the following Marvell Orion 5x series SoCs:
549 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
550 Orion-2 (5281), Orion-1-90 (6183).
553 bool "Marvell PXA168/910/MMP2"
555 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_ALLOCATOR
558 select GENERIC_CLOCKEVENTS
561 select MULTI_IRQ_HANDLER
562 select NEED_MACH_GPIO_H
567 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
570 bool "Micrel/Kendin KS8695"
571 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_MEMORY_H
577 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
578 System-on-Chip devices.
581 bool "Nuvoton W90X900 CPU"
582 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_CLOCKEVENTS
588 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
589 At present, the w90x900 has been renamed nuc900, regarding
590 the ARM series product line, you can login the following
591 link address to know more.
593 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
594 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
598 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
606 select USB_ARCH_HAS_OHCI
609 Support for the NXP LPC32XX family of processors
612 bool "PXA2xx/PXA3xx-based"
614 select ARCH_HAS_CPUFREQ
616 select ARCH_REQUIRE_GPIOLIB
617 select ARM_CPU_SUSPEND if PM
621 select GENERIC_CLOCKEVENTS
624 select MULTI_IRQ_HANDLER
625 select NEED_MACH_GPIO_H
629 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
633 select ARCH_REQUIRE_GPIOLIB
634 select CLKSRC_OF if OF
636 select GENERIC_CLOCKEVENTS
638 Support for Qualcomm MSM/QSD based systems. This runs on the
639 apps processor of the MSM/QSD and depends on a shared memory
640 interface to the modem processor which runs the baseband
641 stack and controls some vital subsystems
642 (clock and power control, etc).
645 bool "Renesas SH-Mobile / R-Mobile"
646 select ARM_PATCH_PHYS_VIRT
648 select GENERIC_CLOCKEVENTS
649 select HAVE_ARM_SCU if SMP
650 select HAVE_ARM_TWD if SMP
651 select HAVE_MACH_CLKDEV
653 select MIGHT_HAVE_CACHE_L2X0
654 select MULTI_IRQ_HANDLER
657 select PM_GENERIC_DOMAINS if PM
660 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
665 select ARCH_MAY_HAVE_PC_FDC
666 select ARCH_SPARSEMEM_ENABLE
667 select ARCH_USES_GETTIMEOFFSET
670 select HAVE_PATA_PLATFORM
672 select NEED_MACH_IO_H
673 select NEED_MACH_MEMORY_H
677 On the Acorn Risc-PC, Linux can support the internal IDE disk and
678 CD-ROM interface, serial and parallel port, and the floppy drive.
682 select ARCH_HAS_CPUFREQ
684 select ARCH_REQUIRE_GPIOLIB
685 select ARCH_SPARSEMEM_ENABLE
690 select GENERIC_CLOCKEVENTS
693 select NEED_MACH_GPIO_H
694 select NEED_MACH_MEMORY_H
697 Support for StrongARM 11x0 based boards.
700 bool "Samsung S3C24XX SoCs"
701 select ARCH_HAS_CPUFREQ
702 select ARCH_REQUIRE_GPIOLIB
704 select CLKSRC_SAMSUNG_PWM
705 select GENERIC_CLOCKEVENTS
707 select HAVE_S3C2410_I2C if I2C
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
709 select HAVE_S3C_RTC if RTC_CLASS
710 select MULTI_IRQ_HANDLER
711 select NEED_MACH_GPIO_H
712 select NEED_MACH_IO_H
715 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
716 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
717 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
718 Samsung SMDK2410 development board (and derivatives).
721 bool "Samsung S3C64XX"
722 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
726 select CLKSRC_SAMSUNG_PWM
729 select GENERIC_CLOCKEVENTS
731 select HAVE_S3C2410_I2C if I2C
732 select HAVE_S3C2410_WATCHDOG if WATCHDOG
734 select NEED_MACH_GPIO_H
737 select PM_GENERIC_DOMAINS
739 select S3C_GPIO_TRACK
741 select SAMSUNG_GPIOLIB_4BIT
742 select SAMSUNG_WAKEMASK
743 select SAMSUNG_WDT_RESET
744 select USB_ARCH_HAS_OHCI
746 Samsung S3C64XX series based systems
749 bool "Samsung S5P6440 S5P6450"
751 select CLKSRC_SAMSUNG_PWM
753 select GENERIC_CLOCKEVENTS
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
757 select HAVE_S3C_RTC if RTC_CLASS
758 select NEED_MACH_GPIO_H
760 select SAMSUNG_WDT_RESET
762 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
766 bool "Samsung S5PC100"
767 select ARCH_REQUIRE_GPIOLIB
769 select CLKSRC_SAMSUNG_PWM
771 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 select HAVE_S3C_RTC if RTC_CLASS
776 select NEED_MACH_GPIO_H
778 select SAMSUNG_WDT_RESET
780 Samsung S5PC100 series based systems
783 bool "Samsung S5PV210/S5PC110"
784 select ARCH_HAS_CPUFREQ
785 select ARCH_HAS_HOLES_MEMORYMODEL
786 select ARCH_SPARSEMEM_ENABLE
788 select CLKSRC_SAMSUNG_PWM
790 select GENERIC_CLOCKEVENTS
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select HAVE_S3C_RTC if RTC_CLASS
795 select NEED_MACH_GPIO_H
796 select NEED_MACH_MEMORY_H
799 Samsung S5PV210/S5PC110 series based systems
802 bool "Samsung EXYNOS"
803 select ARCH_HAS_CPUFREQ
804 select ARCH_HAS_HOLES_MEMORYMODEL
805 select ARCH_REQUIRE_GPIOLIB
806 select ARCH_SPARSEMEM_ENABLE
810 select GENERIC_CLOCKEVENTS
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select HAVE_S3C_RTC if RTC_CLASS
814 select NEED_MACH_MEMORY_H
818 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
822 select ARCH_HAS_HOLES_MEMORYMODEL
823 select ARCH_REQUIRE_GPIOLIB
825 select GENERIC_ALLOCATOR
826 select GENERIC_CLOCKEVENTS
827 select GENERIC_IRQ_CHIP
833 Support for TI's DaVinci platform.
838 select ARCH_HAS_CPUFREQ
839 select ARCH_HAS_HOLES_MEMORYMODEL
841 select ARCH_REQUIRE_GPIOLIB
844 select GENERIC_CLOCKEVENTS
845 select GENERIC_IRQ_CHIP
848 select NEED_MACH_IO_H if PCCARD
849 select NEED_MACH_MEMORY_H
851 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
855 menu "Multiple platform selection"
856 depends on ARCH_MULTIPLATFORM
858 comment "CPU Core family selection"
860 config ARCH_MULTI_V4T
861 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
862 depends on !ARCH_MULTI_V6_V7
863 select ARCH_MULTI_V4_V5
864 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
865 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
866 CPU_ARM925T || CPU_ARM940T)
869 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
870 depends on !ARCH_MULTI_V6_V7
871 select ARCH_MULTI_V4_V5
872 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
873 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
874 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
876 config ARCH_MULTI_V4_V5
880 bool "ARMv6 based platforms (ARM11)"
881 select ARCH_MULTI_V6_V7
885 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
887 select ARCH_MULTI_V6_V7
890 config ARCH_MULTI_V6_V7
893 config ARCH_MULTI_CPU_AUTO
894 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
900 # This is sorted alphabetically by mach-* pathname. However, plat-*
901 # Kconfigs may be included either alphabetically (according to the
902 # plat- suffix) or along side the corresponding mach-* source.
904 source "arch/arm/mach-mvebu/Kconfig"
906 source "arch/arm/mach-at91/Kconfig"
908 source "arch/arm/mach-bcm/Kconfig"
910 source "arch/arm/mach-bcm2835/Kconfig"
912 source "arch/arm/mach-clps711x/Kconfig"
914 source "arch/arm/mach-cns3xxx/Kconfig"
916 source "arch/arm/mach-davinci/Kconfig"
918 source "arch/arm/mach-dove/Kconfig"
920 source "arch/arm/mach-ep93xx/Kconfig"
922 source "arch/arm/mach-footbridge/Kconfig"
924 source "arch/arm/mach-gemini/Kconfig"
926 source "arch/arm/mach-highbank/Kconfig"
928 source "arch/arm/mach-integrator/Kconfig"
930 source "arch/arm/mach-iop32x/Kconfig"
932 source "arch/arm/mach-iop33x/Kconfig"
934 source "arch/arm/mach-iop13xx/Kconfig"
936 source "arch/arm/mach-ixp4xx/Kconfig"
938 source "arch/arm/mach-keystone/Kconfig"
940 source "arch/arm/mach-kirkwood/Kconfig"
942 source "arch/arm/mach-ks8695/Kconfig"
944 source "arch/arm/mach-msm/Kconfig"
946 source "arch/arm/mach-mv78xx0/Kconfig"
948 source "arch/arm/mach-imx/Kconfig"
950 source "arch/arm/mach-mxs/Kconfig"
952 source "arch/arm/mach-netx/Kconfig"
954 source "arch/arm/mach-nomadik/Kconfig"
956 source "arch/arm/mach-nspire/Kconfig"
958 source "arch/arm/plat-omap/Kconfig"
960 source "arch/arm/mach-omap1/Kconfig"
962 source "arch/arm/mach-omap2/Kconfig"
964 source "arch/arm/mach-orion5x/Kconfig"
966 source "arch/arm/mach-picoxcell/Kconfig"
968 source "arch/arm/mach-pxa/Kconfig"
969 source "arch/arm/plat-pxa/Kconfig"
971 source "arch/arm/mach-mmp/Kconfig"
973 source "arch/arm/mach-realview/Kconfig"
975 source "arch/arm/mach-rockchip/Kconfig"
977 source "arch/arm/mach-sa1100/Kconfig"
979 source "arch/arm/plat-samsung/Kconfig"
981 source "arch/arm/mach-socfpga/Kconfig"
983 source "arch/arm/mach-spear/Kconfig"
985 source "arch/arm/mach-sti/Kconfig"
987 source "arch/arm/mach-s3c24xx/Kconfig"
989 source "arch/arm/mach-s3c64xx/Kconfig"
991 source "arch/arm/mach-s5p64x0/Kconfig"
993 source "arch/arm/mach-s5pc100/Kconfig"
995 source "arch/arm/mach-s5pv210/Kconfig"
997 source "arch/arm/mach-exynos/Kconfig"
999 source "arch/arm/mach-shmobile/Kconfig"
1001 source "arch/arm/mach-sunxi/Kconfig"
1003 source "arch/arm/mach-prima2/Kconfig"
1005 source "arch/arm/mach-tegra/Kconfig"
1007 source "arch/arm/mach-u300/Kconfig"
1009 source "arch/arm/mach-ux500/Kconfig"
1011 source "arch/arm/mach-versatile/Kconfig"
1013 source "arch/arm/mach-vexpress/Kconfig"
1014 source "arch/arm/plat-versatile/Kconfig"
1016 source "arch/arm/mach-virt/Kconfig"
1018 source "arch/arm/mach-vt8500/Kconfig"
1020 source "arch/arm/mach-w90x900/Kconfig"
1022 source "arch/arm/mach-zynq/Kconfig"
1024 # Definitions to make life easier
1030 select GENERIC_CLOCKEVENTS
1036 select GENERIC_IRQ_CHIP
1039 config PLAT_ORION_LEGACY
1046 config PLAT_VERSATILE
1049 config ARM_TIMER_SP804
1052 select CLKSRC_OF if OF
1054 source arch/arm/mm/Kconfig
1058 default 16 if ARCH_EP93XX
1062 bool "Enable iWMMXt support" if !CPU_PJ4
1063 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1064 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1066 Enable support for iWMMXt context switching at run time if
1067 running on a CPU that supports it.
1071 depends on CPU_XSCALE
1074 config MULTI_IRQ_HANDLER
1077 Allow each machine to specify it's own IRQ handler at run time.
1080 source "arch/arm/Kconfig-nommu"
1083 config PJ4B_ERRATA_4742
1084 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1085 depends on CPU_PJ4B && MACH_ARMADA_370
1088 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1089 Event (WFE) IDLE states, a specific timing sensitivity exists between
1090 the retiring WFI/WFE instructions and the newly issued subsequent
1091 instructions. This sensitivity can result in a CPU hang scenario.
1093 The software must insert either a Data Synchronization Barrier (DSB)
1094 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1097 config ARM_ERRATA_326103
1098 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1101 Executing a SWP instruction to read-only memory does not set bit 11
1102 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1103 treat the access as a read, preventing a COW from occurring and
1104 causing the faulting task to livelock.
1106 config ARM_ERRATA_411920
1107 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1108 depends on CPU_V6 || CPU_V6K
1110 Invalidation of the Instruction Cache operation can
1111 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1112 It does not affect the MPCore. This option enables the ARM Ltd.
1113 recommended workaround.
1115 config ARM_ERRATA_430973
1116 bool "ARM errata: Stale prediction on replaced interworking branch"
1119 This option enables the workaround for the 430973 Cortex-A8
1120 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1121 interworking branch is replaced with another code sequence at the
1122 same virtual address, whether due to self-modifying code or virtual
1123 to physical address re-mapping, Cortex-A8 does not recover from the
1124 stale interworking branch prediction. This results in Cortex-A8
1125 executing the new code sequence in the incorrect ARM or Thumb state.
1126 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1127 and also flushes the branch target cache at every context switch.
1128 Note that setting specific bits in the ACTLR register may not be
1129 available in non-secure mode.
1131 config ARM_ERRATA_458693
1132 bool "ARM errata: Processor deadlock when a false hazard is created"
1134 depends on !ARCH_MULTIPLATFORM
1136 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1137 erratum. For very specific sequences of memory operations, it is
1138 possible for a hazard condition intended for a cache line to instead
1139 be incorrectly associated with a different cache line. This false
1140 hazard might then cause a processor deadlock. The workaround enables
1141 the L1 caching of the NEON accesses and disables the PLD instruction
1142 in the ACTLR register. Note that setting specific bits in the ACTLR
1143 register may not be available in non-secure mode.
1145 config ARM_ERRATA_460075
1146 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1148 depends on !ARCH_MULTIPLATFORM
1150 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1151 erratum. Any asynchronous access to the L2 cache may encounter a
1152 situation in which recent store transactions to the L2 cache are lost
1153 and overwritten with stale memory contents from external memory. The
1154 workaround disables the write-allocate mode for the L2 cache via the
1155 ACTLR register. Note that setting specific bits in the ACTLR register
1156 may not be available in non-secure mode.
1158 config ARM_ERRATA_742230
1159 bool "ARM errata: DMB operation may be faulty"
1160 depends on CPU_V7 && SMP
1161 depends on !ARCH_MULTIPLATFORM
1163 This option enables the workaround for the 742230 Cortex-A9
1164 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1165 between two write operations may not ensure the correct visibility
1166 ordering of the two writes. This workaround sets a specific bit in
1167 the diagnostic register of the Cortex-A9 which causes the DMB
1168 instruction to behave as a DSB, ensuring the correct behaviour of
1171 config ARM_ERRATA_742231
1172 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1173 depends on CPU_V7 && SMP
1174 depends on !ARCH_MULTIPLATFORM
1176 This option enables the workaround for the 742231 Cortex-A9
1177 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1178 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1179 accessing some data located in the same cache line, may get corrupted
1180 data due to bad handling of the address hazard when the line gets
1181 replaced from one of the CPUs at the same time as another CPU is
1182 accessing it. This workaround sets specific bits in the diagnostic
1183 register of the Cortex-A9 which reduces the linefill issuing
1184 capabilities of the processor.
1186 config PL310_ERRATA_588369
1187 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1188 depends on CACHE_L2X0
1190 The PL310 L2 cache controller implements three types of Clean &
1191 Invalidate maintenance operations: by Physical Address
1192 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1193 They are architecturally defined to behave as the execution of a
1194 clean operation followed immediately by an invalidate operation,
1195 both performing to the same memory location. This functionality
1196 is not correctly implemented in PL310 as clean lines are not
1197 invalidated as a result of these operations.
1199 config ARM_ERRATA_643719
1200 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1201 depends on CPU_V7 && SMP
1203 This option enables the workaround for the 643719 Cortex-A9 (prior to
1204 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1205 register returns zero when it should return one. The workaround
1206 corrects this value, ensuring cache maintenance operations which use
1207 it behave as intended and avoiding data corruption.
1209 config ARM_ERRATA_720789
1210 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1213 This option enables the workaround for the 720789 Cortex-A9 (prior to
1214 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1215 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1216 As a consequence of this erratum, some TLB entries which should be
1217 invalidated are not, resulting in an incoherency in the system page
1218 tables. The workaround changes the TLB flushing routines to invalidate
1219 entries regardless of the ASID.
1221 config PL310_ERRATA_727915
1222 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1223 depends on CACHE_L2X0
1225 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1226 operation (offset 0x7FC). This operation runs in background so that
1227 PL310 can handle normal accesses while it is in progress. Under very
1228 rare circumstances, due to this erratum, write data can be lost when
1229 PL310 treats a cacheable write transaction during a Clean &
1230 Invalidate by Way operation.
1232 config ARM_ERRATA_743622
1233 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1235 depends on !ARCH_MULTIPLATFORM
1237 This option enables the workaround for the 743622 Cortex-A9
1238 (r2p*) erratum. Under very rare conditions, a faulty
1239 optimisation in the Cortex-A9 Store Buffer may lead to data
1240 corruption. This workaround sets a specific bit in the diagnostic
1241 register of the Cortex-A9 which disables the Store Buffer
1242 optimisation, preventing the defect from occurring. This has no
1243 visible impact on the overall performance or power consumption of the
1246 config ARM_ERRATA_751472
1247 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1249 depends on !ARCH_MULTIPLATFORM
1251 This option enables the workaround for the 751472 Cortex-A9 (prior
1252 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1253 completion of a following broadcasted operation if the second
1254 operation is received by a CPU before the ICIALLUIS has completed,
1255 potentially leading to corrupted entries in the cache or TLB.
1257 config PL310_ERRATA_753970
1258 bool "PL310 errata: cache sync operation may be faulty"
1259 depends on CACHE_PL310
1261 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1263 Under some condition the effect of cache sync operation on
1264 the store buffer still remains when the operation completes.
1265 This means that the store buffer is always asked to drain and
1266 this prevents it from merging any further writes. The workaround
1267 is to replace the normal offset of cache sync operation (0x730)
1268 by another offset targeting an unmapped PL310 register 0x740.
1269 This has the same effect as the cache sync operation: store buffer
1270 drain and waiting for all buffers empty.
1272 config ARM_ERRATA_754322
1273 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1276 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1277 r3p*) erratum. A speculative memory access may cause a page table walk
1278 which starts prior to an ASID switch but completes afterwards. This
1279 can populate the micro-TLB with a stale entry which may be hit with
1280 the new ASID. This workaround places two dsb instructions in the mm
1281 switching code so that no page table walks can cross the ASID switch.
1283 config ARM_ERRATA_754327
1284 bool "ARM errata: no automatic Store Buffer drain"
1285 depends on CPU_V7 && SMP
1287 This option enables the workaround for the 754327 Cortex-A9 (prior to
1288 r2p0) erratum. The Store Buffer does not have any automatic draining
1289 mechanism and therefore a livelock may occur if an external agent
1290 continuously polls a memory location waiting to observe an update.
1291 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1292 written polling loops from denying visibility of updates to memory.
1294 config ARM_ERRATA_364296
1295 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1298 This options enables the workaround for the 364296 ARM1136
1299 r0p2 erratum (possible cache data corruption with
1300 hit-under-miss enabled). It sets the undocumented bit 31 in
1301 the auxiliary control register and the FI bit in the control
1302 register, thus disabling hit-under-miss without putting the
1303 processor into full low interrupt latency mode. ARM11MPCore
1306 config ARM_ERRATA_764369
1307 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1308 depends on CPU_V7 && SMP
1310 This option enables the workaround for erratum 764369
1311 affecting Cortex-A9 MPCore with two or more processors (all
1312 current revisions). Under certain timing circumstances, a data
1313 cache line maintenance operation by MVA targeting an Inner
1314 Shareable memory region may fail to proceed up to either the
1315 Point of Coherency or to the Point of Unification of the
1316 system. This workaround adds a DSB instruction before the
1317 relevant cache maintenance functions and sets a specific bit
1318 in the diagnostic control register of the SCU.
1320 config PL310_ERRATA_769419
1321 bool "PL310 errata: no automatic Store Buffer drain"
1322 depends on CACHE_L2X0
1324 On revisions of the PL310 prior to r3p2, the Store Buffer does
1325 not automatically drain. This can cause normal, non-cacheable
1326 writes to be retained when the memory system is idle, leading
1327 to suboptimal I/O performance for drivers using coherent DMA.
1328 This option adds a write barrier to the cpu_idle loop so that,
1329 on systems with an outer cache, the store buffer is drained
1332 config ARM_ERRATA_775420
1333 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1336 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1337 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1338 operation aborts with MMU exception, it might cause the processor
1339 to deadlock. This workaround puts DSB before executing ISB if
1340 an abort may occur on cache maintenance.
1342 config ARM_ERRATA_798181
1343 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1344 depends on CPU_V7 && SMP
1346 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1347 adequately shooting down all use of the old entries. This
1348 option enables the Linux kernel workaround for this erratum
1349 which sends an IPI to the CPUs that are running the same ASID
1350 as the one being invalidated.
1352 config ARM_ERRATA_773022
1353 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1356 This option enables the workaround for the 773022 Cortex-A15
1357 (up to r0p4) erratum. In certain rare sequences of code, the
1358 loop buffer may deliver incorrect instructions. This
1359 workaround disables the loop buffer to avoid the erratum.
1363 source "arch/arm/common/Kconfig"
1373 Find out whether you have ISA slots on your motherboard. ISA is the
1374 name of a bus system, i.e. the way the CPU talks to the other stuff
1375 inside your box. Other bus systems are PCI, EISA, MicroChannel
1376 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1377 newer boards don't support it. If you have ISA, say Y, otherwise N.
1379 # Select ISA DMA controller support
1384 # Select ISA DMA interface
1389 bool "PCI support" if MIGHT_HAVE_PCI
1391 Find out whether you have a PCI motherboard. PCI is the name of a
1392 bus system, i.e. the way the CPU talks to the other stuff inside
1393 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1394 VESA. If you have PCI, say Y, otherwise N.
1400 config PCI_NANOENGINE
1401 bool "BSE nanoEngine PCI support"
1402 depends on SA1100_NANOENGINE
1404 Enable PCI on the BSE nanoEngine board.
1409 config PCI_HOST_ITE8152
1411 depends on PCI && MACH_ARMCORE
1415 source "drivers/pci/Kconfig"
1416 source "drivers/pci/pcie/Kconfig"
1418 source "drivers/pcmcia/Kconfig"
1422 menu "Kernel Features"
1427 This option should be selected by machines which have an SMP-
1430 The only effect of this option is to make the SMP-related
1431 options available to the user for configuration.
1434 bool "Symmetric Multi-Processing"
1435 depends on CPU_V6K || CPU_V7
1436 depends on GENERIC_CLOCKEVENTS
1438 depends on MMU || ARM_MPU
1439 select USE_GENERIC_SMP_HELPERS
1441 This enables support for systems with more than one CPU. If you have
1442 a system with only one CPU, like most personal computers, say N. If
1443 you have a system with more than one CPU, say Y.
1445 If you say N here, the kernel will run on single and multiprocessor
1446 machines, but will use only one CPU of a multiprocessor machine. If
1447 you say Y here, the kernel will run on many, but not all, single
1448 processor machines. On a single processor machine, the kernel will
1449 run faster if you say N here.
1451 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1452 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1453 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1455 If you don't know what to do here, say N.
1458 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1459 depends on SMP && !XIP_KERNEL && MMU
1462 SMP kernels contain instructions which fail on non-SMP processors.
1463 Enabling this option allows the kernel to modify itself to make
1464 these instructions safe. Disabling it allows about 1K of space
1467 If you don't know what to do here, say Y.
1469 config ARM_CPU_TOPOLOGY
1470 bool "Support cpu topology definition"
1471 depends on SMP && CPU_V7
1474 Support ARM cpu topology definition. The MPIDR register defines
1475 affinity between processors which is then used to describe the cpu
1476 topology of an ARM System.
1479 bool "Multi-core scheduler support"
1480 depends on ARM_CPU_TOPOLOGY
1482 Multi-core scheduler support improves the CPU scheduler's decision
1483 making when dealing with multi-core CPU chips at a cost of slightly
1484 increased overhead in some places. If unsure say N here.
1487 bool "SMT scheduler support"
1488 depends on ARM_CPU_TOPOLOGY
1490 Improves the CPU scheduler's decision making when dealing with
1491 MultiThreading at a cost of slightly increased overhead in some
1492 places. If unsure say N here.
1497 This option enables support for the ARM system coherency unit
1499 config HAVE_ARM_ARCH_TIMER
1500 bool "Architected timer support"
1502 select ARM_ARCH_TIMER
1504 This option enables support for the ARM architected timer
1509 select CLKSRC_OF if OF
1511 This options enables support for the ARM timer and watchdog unit
1514 bool "Multi-Cluster Power Management"
1515 depends on CPU_V7 && SMP
1517 This option provides the common power management infrastructure
1518 for (multi-)cluster based systems, such as big.LITTLE based
1522 prompt "Memory split"
1525 Select the desired split between kernel and user memory.
1527 If you are not absolutely sure what you are doing, leave this
1531 bool "3G/1G user/kernel split"
1533 bool "2G/2G user/kernel split"
1535 bool "1G/3G user/kernel split"
1540 default 0x40000000 if VMSPLIT_1G
1541 default 0x80000000 if VMSPLIT_2G
1545 int "Maximum number of CPUs (2-32)"
1551 bool "Support for hot-pluggable CPUs"
1554 Say Y here to experiment with turning CPUs off and on. CPUs
1555 can be controlled through /sys/devices/system/cpu.
1558 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1561 Say Y here if you want Linux to communicate with system firmware
1562 implementing the PSCI specification for CPU-centric power
1563 management operations described in ARM document number ARM DEN
1564 0022A ("Power State Coordination Interface System Software on
1567 # The GPIO number here must be sorted by descending number. In case of
1568 # a multiplatform kernel, we just want the highest value required by the
1569 # selected platforms.
1572 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1573 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1574 default 392 if ARCH_U8500
1575 default 352 if ARCH_VT8500
1576 default 288 if ARCH_SUNXI
1577 default 264 if MACH_H4700
1580 Maximum number of GPIOs in the system.
1582 If unsure, leave the default value.
1584 source kernel/Kconfig.preempt
1588 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1589 ARCH_S5PV210 || ARCH_EXYNOS4
1590 default AT91_TIMER_HZ if ARCH_AT91
1591 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1595 depends on HZ_FIXED = 0
1596 prompt "Timer frequency"
1620 default HZ_FIXED if HZ_FIXED != 0
1621 default 100 if HZ_100
1622 default 200 if HZ_200
1623 default 250 if HZ_250
1624 default 300 if HZ_300
1625 default 500 if HZ_500
1629 def_bool HIGH_RES_TIMERS
1632 def_bool HIGH_RES_TIMERS
1634 config THUMB2_KERNEL
1635 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1636 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1637 default y if CPU_THUMBONLY
1639 select ARM_ASM_UNIFIED
1642 By enabling this option, the kernel will be compiled in
1643 Thumb-2 mode. A compiler/assembler that understand the unified
1644 ARM-Thumb syntax is needed.
1648 config THUMB2_AVOID_R_ARM_THM_JUMP11
1649 bool "Work around buggy Thumb-2 short branch relocations in gas"
1650 depends on THUMB2_KERNEL && MODULES
1653 Various binutils versions can resolve Thumb-2 branches to
1654 locally-defined, preemptible global symbols as short-range "b.n"
1655 branch instructions.
1657 This is a problem, because there's no guarantee the final
1658 destination of the symbol, or any candidate locations for a
1659 trampoline, are within range of the branch. For this reason, the
1660 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1661 relocation in modules at all, and it makes little sense to add
1664 The symptom is that the kernel fails with an "unsupported
1665 relocation" error when loading some modules.
1667 Until fixed tools are available, passing
1668 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1669 code which hits this problem, at the cost of a bit of extra runtime
1670 stack usage in some cases.
1672 The problem is described in more detail at:
1673 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1675 Only Thumb-2 kernels are affected.
1677 Unless you are sure your tools don't have this problem, say Y.
1679 config ARM_ASM_UNIFIED
1683 bool "Use the ARM EABI to compile the kernel"
1685 This option allows for the kernel to be compiled using the latest
1686 ARM ABI (aka EABI). This is only useful if you are using a user
1687 space environment that is also compiled with EABI.
1689 Since there are major incompatibilities between the legacy ABI and
1690 EABI, especially with regard to structure member alignment, this
1691 option also changes the kernel syscall calling convention to
1692 disambiguate both ABIs and allow for backward compatibility support
1693 (selected with CONFIG_OABI_COMPAT).
1695 To use this you need GCC version 4.0.0 or later.
1698 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1699 depends on AEABI && !THUMB2_KERNEL
1702 This option preserves the old syscall interface along with the
1703 new (ARM EABI) one. It also provides a compatibility layer to
1704 intercept syscalls that have structure arguments which layout
1705 in memory differs between the legacy ABI and the new ARM EABI
1706 (only for non "thumb" binaries). This option adds a tiny
1707 overhead to all syscalls and produces a slightly larger kernel.
1708 If you know you'll be using only pure EABI user space then you
1709 can say N here. If this option is not selected and you attempt
1710 to execute a legacy ABI binary then the result will be
1711 UNPREDICTABLE (in fact it can be predicted that it won't work
1712 at all). If in doubt say Y.
1714 config ARCH_HAS_HOLES_MEMORYMODEL
1717 config ARCH_SPARSEMEM_ENABLE
1720 config ARCH_SPARSEMEM_DEFAULT
1721 def_bool ARCH_SPARSEMEM_ENABLE
1723 config ARCH_SELECT_MEMORY_MODEL
1724 def_bool ARCH_SPARSEMEM_ENABLE
1726 config HAVE_ARCH_PFN_VALID
1727 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1730 bool "High Memory Support"
1733 The address space of ARM processors is only 4 Gigabytes large
1734 and it has to accommodate user address space, kernel address
1735 space as well as some memory mapped IO. That means that, if you
1736 have a large amount of physical memory and/or IO, not all of the
1737 memory can be "permanently mapped" by the kernel. The physical
1738 memory that is not permanently mapped is called "high memory".
1740 Depending on the selected kernel/user memory split, minimum
1741 vmalloc space and actual amount of RAM, you may not need this
1742 option which should result in a slightly faster kernel.
1747 bool "Allocate 2nd-level pagetables from highmem"
1750 config HW_PERF_EVENTS
1751 bool "Enable hardware performance counter support for perf events"
1752 depends on PERF_EVENTS
1755 Enable hardware performance counter support for perf events. If
1756 disabled, perf events will use software events only.
1758 config SYS_SUPPORTS_HUGETLBFS
1762 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1766 config ARCH_WANT_GENERAL_HUGETLB
1771 config FORCE_MAX_ZONEORDER
1772 int "Maximum zone order" if ARCH_SHMOBILE
1773 range 11 64 if ARCH_SHMOBILE
1774 default "12" if SOC_AM33XX
1775 default "9" if SA1111
1778 The kernel memory allocator divides physically contiguous memory
1779 blocks into "zones", where each zone is a power of two number of
1780 pages. This option selects the largest power of two that the kernel
1781 keeps in the memory allocator. If you need to allocate very large
1782 blocks of physically contiguous memory, then you may need to
1783 increase this value.
1785 This config option is actually maximum order plus one. For example,
1786 a value of 11 means that the largest free memory block is 2^10 pages.
1788 config ALIGNMENT_TRAP
1790 depends on CPU_CP15_MMU
1791 default y if !ARCH_EBSA110
1792 select HAVE_PROC_CPU if PROC_FS
1794 ARM processors cannot fetch/store information which is not
1795 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1796 address divisible by 4. On 32-bit ARM processors, these non-aligned
1797 fetch/store instructions will be emulated in software if you say
1798 here, which has a severe performance impact. This is necessary for
1799 correct operation of some network protocols. With an IP-only
1800 configuration it is safe to say N, otherwise say Y.
1802 config UACCESS_WITH_MEMCPY
1803 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1805 default y if CPU_FEROCEON
1807 Implement faster copy_to_user and clear_user methods for CPU
1808 cores where a 8-word STM instruction give significantly higher
1809 memory write throughput than a sequence of individual 32bit stores.
1811 A possible side effect is a slight increase in scheduling latency
1812 between threads sharing the same address space if they invoke
1813 such copy operations with large buffers.
1815 However, if the CPU data cache is using a write-allocate mode,
1816 this option is unlikely to provide any performance gain.
1820 prompt "Enable seccomp to safely compute untrusted bytecode"
1822 This kernel feature is useful for number crunching applications
1823 that may need to compute untrusted bytecode during their
1824 execution. By using pipes or other transports made available to
1825 the process as file descriptors supporting the read/write
1826 syscalls, it's possible to isolate those applications in
1827 their own address space using seccomp. Once seccomp is
1828 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1829 and the task is only allowed to execute a few safe syscalls
1830 defined by each seccomp mode.
1832 config CC_STACKPROTECTOR
1833 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1835 This option turns on the -fstack-protector GCC feature. This
1836 feature puts, at the beginning of functions, a canary value on
1837 the stack just before the return address, and validates
1838 the value just before actually returning. Stack based buffer
1839 overflows (that need to overwrite this return address) now also
1840 overwrite the canary, which gets detected and the attack is then
1841 neutralized via a kernel panic.
1842 This feature requires gcc version 4.2 or above.
1849 bool "Xen guest support on ARM (EXPERIMENTAL)"
1850 depends on ARM && AEABI && OF
1851 depends on CPU_V7 && !CPU_V6
1852 depends on !GENERIC_ATOMIC64
1855 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1862 bool "Flattened Device Tree support"
1865 select OF_EARLY_FLATTREE
1867 Include support for flattened device tree machine descriptions.
1870 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1873 This is the traditional way of passing data to the kernel at boot
1874 time. If you are solely relying on the flattened device tree (or
1875 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1876 to remove ATAGS support from your kernel binary. If unsure,
1879 config DEPRECATED_PARAM_STRUCT
1880 bool "Provide old way to pass kernel parameters"
1883 This was deprecated in 2001 and announced to live on for 5 years.
1884 Some old boot loaders still use this way.
1886 # Compressed boot loader in ROM. Yes, we really want to ask about
1887 # TEXT and BSS so we preserve their values in the config files.
1888 config ZBOOT_ROM_TEXT
1889 hex "Compressed ROM boot loader base address"
1892 The physical address at which the ROM-able zImage is to be
1893 placed in the target. Platforms which normally make use of
1894 ROM-able zImage formats normally set this to a suitable
1895 value in their defconfig file.
1897 If ZBOOT_ROM is not enabled, this has no effect.
1899 config ZBOOT_ROM_BSS
1900 hex "Compressed ROM boot loader BSS address"
1903 The base address of an area of read/write memory in the target
1904 for the ROM-able zImage which must be available while the
1905 decompressor is running. It must be large enough to hold the
1906 entire decompressed kernel plus an additional 128 KiB.
1907 Platforms which normally make use of ROM-able zImage formats
1908 normally set this to a suitable value in their defconfig file.
1910 If ZBOOT_ROM is not enabled, this has no effect.
1913 bool "Compressed boot loader in ROM/flash"
1914 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1916 Say Y here if you intend to execute your compressed kernel image
1917 (zImage) directly from ROM or flash. If unsure, say N.
1920 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1921 depends on ZBOOT_ROM && ARCH_SH7372
1922 default ZBOOT_ROM_NONE
1924 Include experimental SD/MMC loading code in the ROM-able zImage.
1925 With this enabled it is possible to write the ROM-able zImage
1926 kernel image to an MMC or SD card and boot the kernel straight
1927 from the reset vector. At reset the processor Mask ROM will load
1928 the first part of the ROM-able zImage which in turn loads the
1929 rest the kernel image to RAM.
1931 config ZBOOT_ROM_NONE
1932 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1934 Do not load image from SD or MMC
1936 config ZBOOT_ROM_MMCIF
1937 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1939 Load image from MMCIF hardware block.
1941 config ZBOOT_ROM_SH_MOBILE_SDHI
1942 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1944 Load image from SDHI hardware block
1948 config ARM_APPENDED_DTB
1949 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1950 depends on OF && !ZBOOT_ROM
1952 With this option, the boot code will look for a device tree binary
1953 (DTB) appended to zImage
1954 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1956 This is meant as a backward compatibility convenience for those
1957 systems with a bootloader that can't be upgraded to accommodate
1958 the documented boot protocol using a device tree.
1960 Beware that there is very little in terms of protection against
1961 this option being confused by leftover garbage in memory that might
1962 look like a DTB header after a reboot if no actual DTB is appended
1963 to zImage. Do not leave this option active in a production kernel
1964 if you don't intend to always append a DTB. Proper passing of the
1965 location into r2 of a bootloader provided DTB is always preferable
1968 config ARM_ATAG_DTB_COMPAT
1969 bool "Supplement the appended DTB with traditional ATAG information"
1970 depends on ARM_APPENDED_DTB
1972 Some old bootloaders can't be updated to a DTB capable one, yet
1973 they provide ATAGs with memory configuration, the ramdisk address,
1974 the kernel cmdline string, etc. Such information is dynamically
1975 provided by the bootloader and can't always be stored in a static
1976 DTB. To allow a device tree enabled kernel to be used with such
1977 bootloaders, this option allows zImage to extract the information
1978 from the ATAG list and store it at run time into the appended DTB.
1981 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1982 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1985 bool "Use bootloader kernel arguments if available"
1987 Uses the command-line options passed by the boot loader instead of
1988 the device tree bootargs property. If the boot loader doesn't provide
1989 any, the device tree bootargs property will be used.
1991 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1992 bool "Extend with bootloader kernel arguments"
1994 The command-line arguments provided by the boot loader will be
1995 appended to the the device tree bootargs property.
2000 string "Default kernel command string"
2003 On some architectures (EBSA110 and CATS), there is currently no way
2004 for the boot loader to pass arguments to the kernel. For these
2005 architectures, you should supply some command-line options at build
2006 time by entering them here. As a minimum, you should specify the
2007 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2010 prompt "Kernel command line type" if CMDLINE != ""
2011 default CMDLINE_FROM_BOOTLOADER
2014 config CMDLINE_FROM_BOOTLOADER
2015 bool "Use bootloader kernel arguments if available"
2017 Uses the command-line options passed by the boot loader. If
2018 the boot loader doesn't provide any, the default kernel command
2019 string provided in CMDLINE will be used.
2021 config CMDLINE_EXTEND
2022 bool "Extend bootloader kernel arguments"
2024 The command-line arguments provided by the boot loader will be
2025 appended to the default kernel command string.
2027 config CMDLINE_FORCE
2028 bool "Always use the default kernel command string"
2030 Always use the default kernel command string, even if the boot
2031 loader passes other arguments to the kernel.
2032 This is useful if you cannot or don't want to change the
2033 command-line options your boot loader passes to the kernel.
2037 bool "Kernel Execute-In-Place from ROM"
2038 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2040 Execute-In-Place allows the kernel to run from non-volatile storage
2041 directly addressable by the CPU, such as NOR flash. This saves RAM
2042 space since the text section of the kernel is not loaded from flash
2043 to RAM. Read-write sections, such as the data section and stack,
2044 are still copied to RAM. The XIP kernel is not compressed since
2045 it has to run directly from flash, so it will take more space to
2046 store it. The flash address used to link the kernel object files,
2047 and for storing it, is configuration dependent. Therefore, if you
2048 say Y here, you must know the proper physical address where to
2049 store the kernel image depending on your own flash memory usage.
2051 Also note that the make target becomes "make xipImage" rather than
2052 "make zImage" or "make Image". The final kernel binary to put in
2053 ROM memory will be arch/arm/boot/xipImage.
2057 config XIP_PHYS_ADDR
2058 hex "XIP Kernel Physical Location"
2059 depends on XIP_KERNEL
2060 default "0x00080000"
2062 This is the physical address in your flash memory the kernel will
2063 be linked for and stored to. This address is dependent on your
2067 bool "Kexec system call (EXPERIMENTAL)"
2068 depends on (!SMP || PM_SLEEP_SMP)
2070 kexec is a system call that implements the ability to shutdown your
2071 current kernel, and to start another kernel. It is like a reboot
2072 but it is independent of the system firmware. And like a reboot
2073 you can start any kernel with it, not just Linux.
2075 It is an ongoing process to be certain the hardware in a machine
2076 is properly shutdown, so do not be surprised if this code does not
2077 initially work for you.
2080 bool "Export atags in procfs"
2081 depends on ATAGS && KEXEC
2084 Should the atags used to boot the kernel be exported in an "atags"
2085 file in procfs. Useful with kexec.
2088 bool "Build kdump crash kernel (EXPERIMENTAL)"
2090 Generate crash dump after being started by kexec. This should
2091 be normally only set in special crash dump kernels which are
2092 loaded in the main kernel with kexec-tools into a specially
2093 reserved region and then later executed after a crash by
2094 kdump/kexec. The crash dump kernel must be compiled to a
2095 memory address not used by the main kernel
2097 For more details see Documentation/kdump/kdump.txt
2099 config AUTO_ZRELADDR
2100 bool "Auto calculation of the decompressed kernel image address"
2101 depends on !ZBOOT_ROM
2103 ZRELADDR is the physical address where the decompressed kernel
2104 image will be placed. If AUTO_ZRELADDR is selected, the address
2105 will be determined at run-time by masking the current IP with
2106 0xf8000000. This assumes the zImage being placed in the first 128MB
2107 from start of memory.
2111 menu "CPU Power Management"
2114 source "drivers/cpufreq/Kconfig"
2117 source "drivers/cpuidle/Kconfig"
2121 menu "Floating point emulation"
2123 comment "At least one emulation must be selected"
2126 bool "NWFPE math emulation"
2127 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2129 Say Y to include the NWFPE floating point emulator in the kernel.
2130 This is necessary to run most binaries. Linux does not currently
2131 support floating point hardware so you need to say Y here even if
2132 your machine has an FPA or floating point co-processor podule.
2134 You may say N here if you are going to load the Acorn FPEmulator
2135 early in the bootup.
2138 bool "Support extended precision"
2139 depends on FPE_NWFPE
2141 Say Y to include 80-bit support in the kernel floating-point
2142 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2143 Note that gcc does not generate 80-bit operations by default,
2144 so in most cases this option only enlarges the size of the
2145 floating point emulator without any good reason.
2147 You almost surely want to say N here.
2150 bool "FastFPE math emulation (EXPERIMENTAL)"
2151 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2153 Say Y here to include the FAST floating point emulator in the kernel.
2154 This is an experimental much faster emulator which now also has full
2155 precision for the mantissa. It does not support any exceptions.
2156 It is very simple, and approximately 3-6 times faster than NWFPE.
2158 It should be sufficient for most programs. It may be not suitable
2159 for scientific calculations, but you have to check this for yourself.
2160 If you do not feel you need a faster FP emulation you should better
2164 bool "VFP-format floating point maths"
2165 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2167 Say Y to include VFP support code in the kernel. This is needed
2168 if your hardware includes a VFP unit.
2170 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2171 release notes and additional status information.
2173 Say N if your target does not have VFP hardware.
2181 bool "Advanced SIMD (NEON) Extension support"
2182 depends on VFPv3 && CPU_V7
2184 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2187 config KERNEL_MODE_NEON
2188 bool "Support for NEON in kernel mode"
2189 depends on NEON && AEABI
2191 Say Y to include support for NEON in kernel mode.
2195 menu "Userspace binary formats"
2197 source "fs/Kconfig.binfmt"
2200 tristate "RISC OS personality"
2203 Say Y here to include the kernel code necessary if you want to run
2204 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2205 experimental; if this sounds frightening, say N and sleep in peace.
2206 You can also say M here to compile this support as a module (which
2207 will be called arthur).
2211 menu "Power management options"
2213 source "kernel/power/Kconfig"
2215 config ARCH_SUSPEND_POSSIBLE
2216 depends on !ARCH_S5PC100
2217 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2218 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2221 config ARM_CPU_SUSPEND
2226 source "net/Kconfig"
2228 source "drivers/Kconfig"
2232 source "arch/arm/Kconfig.debug"
2234 source "security/Kconfig"
2236 source "crypto/Kconfig"
2238 source "lib/Kconfig"
2240 source "arch/arm/kvm/Kconfig"