5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt translation functions at runtime according to
201 the position of the kernel in system memory.
203 This can only be used with non-XIP with MMU kernels where
204 the base of physical memory is at a 16MB boundary.
206 config ARM_PATCH_PHYS_VIRT_16BIT
208 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
210 source "init/Kconfig"
212 source "kernel/Kconfig.freezer"
217 bool "MMU-based Paged Memory Management Support"
220 Select if you want MMU-based virtualised addressing space
221 support by paged memory management. If unsure, say 'Y'.
224 # The "ARM system type" choice list is ordered alphabetically by option
225 # text. Please add new entries in the option alphabetic order.
228 prompt "ARM system type"
229 default ARCH_VERSATILE
231 config ARCH_INTEGRATOR
232 bool "ARM Ltd. Integrator family"
234 select ARCH_HAS_CPUFREQ
237 select GENERIC_CLOCKEVENTS
238 select PLAT_VERSATILE
239 select PLAT_VERSATILE_FPGA_IRQ
241 Support for ARM's Integrator platform.
244 bool "ARM Ltd. RealView family"
248 select GENERIC_CLOCKEVENTS
249 select ARCH_WANT_OPTIONAL_GPIOLIB
250 select PLAT_VERSATILE
251 select PLAT_VERSATILE_CLCD
252 select ARM_TIMER_SP804
253 select GPIO_PL061 if GPIOLIB
255 This enables support for ARM Ltd RealView boards.
257 config ARCH_VERSATILE
258 bool "ARM Ltd. Versatile family"
263 select GENERIC_CLOCKEVENTS
264 select ARCH_WANT_OPTIONAL_GPIOLIB
265 select PLAT_VERSATILE
266 select PLAT_VERSATILE_CLCD
267 select PLAT_VERSATILE_FPGA_IRQ
268 select ARM_TIMER_SP804
270 This enables support for ARM Ltd Versatile board.
273 bool "ARM Ltd. Versatile Express family"
274 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select ARM_TIMER_SP804
278 select GENERIC_CLOCKEVENTS
280 select HAVE_PATA_PLATFORM
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_CLCD
285 This enables support for the ARM Ltd Versatile Express boards.
289 select ARCH_REQUIRE_GPIOLIB
292 This enables support for systems based on the Atmel AT91RM9200,
293 AT91SAM9 and AT91CAP9 processors.
296 bool "Broadcom BCMRING"
301 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 Support for Broadcom's BCMRing platform.
307 bool "Cirrus Logic CLPS711x/EP721x-based"
309 select ARCH_USES_GETTIMEOFFSET
311 Support for Cirrus Logic 711x/721x based boards.
314 bool "Cavium Networks CNS3XXX family"
316 select GENERIC_CLOCKEVENTS
318 select MIGHT_HAVE_PCI
319 select PCI_DOMAINS if PCI
321 Support for Cavium Networks CNS3XXX platform.
324 bool "Cortina Systems Gemini"
326 select ARCH_REQUIRE_GPIOLIB
327 select ARCH_USES_GETTIMEOFFSET
329 Support for the Cortina Systems Gemini family SoCs
336 select ARCH_USES_GETTIMEOFFSET
338 This is an evaluation board for the StrongARM processor available
339 from Digital. It has limited hardware on-board, including an
340 Ethernet interface, two PCMCIA sockets, two serial ports and a
349 select ARCH_REQUIRE_GPIOLIB
350 select ARCH_HAS_HOLES_MEMORYMODEL
351 select ARCH_USES_GETTIMEOFFSET
353 This enables support for the Cirrus EP93xx series of CPUs.
355 config ARCH_FOOTBRIDGE
359 select GENERIC_CLOCKEVENTS
361 Support for systems based on the DC21285 companion chip
362 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
365 bool "Freescale MXC/iMX-based"
366 select GENERIC_CLOCKEVENTS
367 select ARCH_REQUIRE_GPIOLIB
369 select HAVE_SCHED_CLOCK
371 Support for Freescale MXC/iMX-based family of processors
374 bool "Freescale MXS-based"
375 select GENERIC_CLOCKEVENTS
376 select ARCH_REQUIRE_GPIOLIB
379 Support for Freescale MXS-based family of processors
382 bool "Freescale STMP3xxx"
385 select ARCH_REQUIRE_GPIOLIB
386 select GENERIC_CLOCKEVENTS
387 select USB_ARCH_HAS_EHCI
389 Support for systems based on the Freescale 3xxx CPUs.
392 bool "Hilscher NetX based"
395 select GENERIC_CLOCKEVENTS
397 This enables support for systems based on the Hilscher NetX Soc
400 bool "Hynix HMS720x-based"
403 select ARCH_USES_GETTIMEOFFSET
405 This enables support for systems based on the Hynix HMS720x
413 select ARCH_SUPPORTS_MSI
416 Support for Intel's IOP13XX (XScale) family of processors.
424 select ARCH_REQUIRE_GPIOLIB
426 Support for Intel's 80219 and IOP32X (XScale) family of
435 select ARCH_REQUIRE_GPIOLIB
437 Support for Intel's IOP33X (XScale) family of processors.
444 select ARCH_USES_GETTIMEOFFSET
446 Support for Intel's IXP23xx (XScale) family of processors.
449 bool "IXP2400/2800-based"
453 select ARCH_USES_GETTIMEOFFSET
455 Support for Intel's IXP2400/2800 (XScale) family of processors.
462 select GENERIC_CLOCKEVENTS
463 select HAVE_SCHED_CLOCK
464 select MIGHT_HAVE_PCI
465 select DMABOUNCE if PCI
467 Support for Intel's IXP4XX (XScale) family of processors.
473 select ARCH_REQUIRE_GPIOLIB
474 select GENERIC_CLOCKEVENTS
477 Support for the Marvell Dove SoC 88AP510
480 bool "Marvell Kirkwood"
483 select ARCH_REQUIRE_GPIOLIB
484 select GENERIC_CLOCKEVENTS
487 Support for the following Marvell Kirkwood series SoCs:
488 88F6180, 88F6192 and 88F6281.
491 bool "Marvell Loki (88RC8480)"
493 select GENERIC_CLOCKEVENTS
496 Support for the Marvell Loki (88RC8480) SoC.
501 select ARCH_REQUIRE_GPIOLIB
504 select USB_ARCH_HAS_OHCI
507 select GENERIC_CLOCKEVENTS
509 Support for the NXP LPC32XX family of processors
512 bool "Marvell MV78xx0"
515 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
519 Support for the following Marvell MV78xx0 series SoCs:
527 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 Support for the following Marvell Orion 5x series SoCs:
532 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
533 Orion-2 (5281), Orion-1-90 (6183).
536 bool "Marvell PXA168/910/MMP2"
538 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
541 select HAVE_SCHED_CLOCK
546 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
549 bool "Micrel/Kendin KS8695"
551 select ARCH_REQUIRE_GPIOLIB
552 select ARCH_USES_GETTIMEOFFSET
554 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
555 System-on-Chip devices.
558 bool "Nuvoton W90X900 CPU"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
565 At present, the w90x900 has been renamed nuc900, regarding
566 the ARM series product line, you can login the following
567 link address to know more.
569 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
570 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
573 bool "Nuvoton NUC93X CPU"
577 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
578 low-power and high performance MPEG-4/JPEG multimedia controller chip.
584 select GENERIC_CLOCKEVENTS
587 select HAVE_SCHED_CLOCK
588 select ARCH_HAS_BARRIERS if CACHE_L2X0
589 select ARCH_HAS_CPUFREQ
591 This enables support for NVIDIA Tegra based systems (Tegra APX,
592 Tegra 6xx and Tegra 2 series).
595 bool "Philips Nexperia PNX4008 Mobile"
598 select ARCH_USES_GETTIMEOFFSET
600 This enables support for Philips PNX4008 mobile platform.
603 bool "PXA2xx/PXA3xx-based"
606 select ARCH_HAS_CPUFREQ
608 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
610 select HAVE_SCHED_CLOCK
615 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
620 select GENERIC_CLOCKEVENTS
621 select ARCH_REQUIRE_GPIOLIB
624 Support for Qualcomm MSM/QSD based systems. This runs on the
625 apps processor of the MSM/QSD and depends on a shared memory
626 interface to the modem processor which runs the baseband
627 stack and controls some vital subsystems
628 (clock and power control, etc).
631 bool "Renesas SH-Mobile / R-Mobile"
634 select GENERIC_CLOCKEVENTS
637 select MULTI_IRQ_HANDLER
639 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
646 select ARCH_MAY_HAVE_PC_FDC
647 select HAVE_PATA_PLATFORM
650 select ARCH_SPARSEMEM_ENABLE
651 select ARCH_USES_GETTIMEOFFSET
653 On the Acorn Risc-PC, Linux can support the internal IDE disk and
654 CD-ROM interface, serial and parallel port, and the floppy drive.
660 select ARCH_SPARSEMEM_ENABLE
662 select ARCH_HAS_CPUFREQ
664 select GENERIC_CLOCKEVENTS
666 select HAVE_SCHED_CLOCK
668 select ARCH_REQUIRE_GPIOLIB
670 Support for StrongARM 11x0 based boards.
673 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
675 select ARCH_HAS_CPUFREQ
677 select ARCH_USES_GETTIMEOFFSET
678 select HAVE_S3C2410_I2C if I2C
680 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
681 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
682 the Samsung SMDK2410 development board (and derivatives).
684 Note, the S3C2416 and the S3C2450 are so close that they even share
685 the same SoC ID code. This means that there is no separate machine
686 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
689 bool "Samsung S3C64XX"
695 select ARCH_USES_GETTIMEOFFSET
696 select ARCH_HAS_CPUFREQ
697 select ARCH_REQUIRE_GPIOLIB
698 select SAMSUNG_CLKSRC
699 select SAMSUNG_IRQ_VIC_TIMER
700 select SAMSUNG_IRQ_UART
701 select S3C_GPIO_TRACK
702 select S3C_GPIO_PULL_UPDOWN
703 select S3C_GPIO_CFG_S3C24XX
704 select S3C_GPIO_CFG_S3C64XX
706 select USB_ARCH_HAS_OHCI
707 select SAMSUNG_GPIOLIB_4BIT
708 select HAVE_S3C2410_I2C if I2C
709 select HAVE_S3C2410_WATCHDOG if WATCHDOG
711 Samsung S3C64XX series based systems
714 bool "Samsung S5P6440 S5P6450"
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
719 select GENERIC_CLOCKEVENTS
720 select HAVE_SCHED_CLOCK
721 select HAVE_S3C2410_I2C if I2C
722 select HAVE_S3C_RTC if RTC_CLASS
724 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
728 bool "Samsung S5P6442"
732 select ARCH_USES_GETTIMEOFFSET
733 select HAVE_S3C2410_WATCHDOG if WATCHDOG
735 Samsung S5P6442 CPU based systems
738 bool "Samsung S5PC100"
742 select ARM_L1_CACHE_SHIFT_6
743 select ARCH_USES_GETTIMEOFFSET
744 select HAVE_S3C2410_I2C if I2C
745 select HAVE_S3C_RTC if RTC_CLASS
746 select HAVE_S3C2410_WATCHDOG if WATCHDOG
748 Samsung S5PC100 series based systems
751 bool "Samsung S5PV210/S5PC110"
753 select ARCH_SPARSEMEM_ENABLE
756 select ARM_L1_CACHE_SHIFT_6
757 select ARCH_HAS_CPUFREQ
758 select GENERIC_CLOCKEVENTS
759 select HAVE_SCHED_CLOCK
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C_RTC if RTC_CLASS
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 Samsung S5PV210/S5PC110 series based systems
767 bool "Samsung EXYNOS4"
769 select ARCH_SPARSEMEM_ENABLE
772 select ARCH_HAS_CPUFREQ
773 select GENERIC_CLOCKEVENTS
774 select HAVE_S3C_RTC if RTC_CLASS
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
778 Samsung EXYNOS4 series based systems
787 select ARCH_USES_GETTIMEOFFSET
789 Support for the StrongARM based Digital DNARD machine, also known
790 as "Shark" (<http://www.shark-linux.de/shark.html>).
793 bool "Telechips TCC ARM926-based systems"
797 select GENERIC_CLOCKEVENTS
799 Support for Telechips TCC ARM926-based systems.
802 bool "ST-Ericsson U300 Series"
805 select HAVE_SCHED_CLOCK
809 select GENERIC_CLOCKEVENTS
813 Support for ST-Ericsson U300 series mobile platforms.
816 bool "ST-Ericsson U8500 Series"
819 select GENERIC_CLOCKEVENTS
821 select ARCH_REQUIRE_GPIOLIB
822 select ARCH_HAS_CPUFREQ
824 Support for ST-Ericsson's Ux500 architecture
827 bool "STMicroelectronics Nomadik"
832 select GENERIC_CLOCKEVENTS
833 select ARCH_REQUIRE_GPIOLIB
835 Support for the Nomadik platform by ST-Ericsson
839 select GENERIC_CLOCKEVENTS
840 select ARCH_REQUIRE_GPIOLIB
844 select GENERIC_ALLOCATOR
845 select ARCH_HAS_HOLES_MEMORYMODEL
847 Support for TI's DaVinci platform.
852 select ARCH_REQUIRE_GPIOLIB
853 select ARCH_HAS_CPUFREQ
854 select GENERIC_CLOCKEVENTS
855 select HAVE_SCHED_CLOCK
856 select ARCH_HAS_HOLES_MEMORYMODEL
858 Support for TI's OMAP platform (OMAP1/2/3/4).
863 select ARCH_REQUIRE_GPIOLIB
865 select GENERIC_CLOCKEVENTS
868 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
871 bool "VIA/WonderMedia 85xx"
874 select ARCH_HAS_CPUFREQ
875 select GENERIC_CLOCKEVENTS
876 select ARCH_REQUIRE_GPIOLIB
879 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
883 # This is sorted alphabetically by mach-* pathname. However, plat-*
884 # Kconfigs may be included either alphabetically (according to the
885 # plat- suffix) or along side the corresponding mach-* source.
887 source "arch/arm/mach-at91/Kconfig"
889 source "arch/arm/mach-bcmring/Kconfig"
891 source "arch/arm/mach-clps711x/Kconfig"
893 source "arch/arm/mach-cns3xxx/Kconfig"
895 source "arch/arm/mach-davinci/Kconfig"
897 source "arch/arm/mach-dove/Kconfig"
899 source "arch/arm/mach-ep93xx/Kconfig"
901 source "arch/arm/mach-footbridge/Kconfig"
903 source "arch/arm/mach-gemini/Kconfig"
905 source "arch/arm/mach-h720x/Kconfig"
907 source "arch/arm/mach-integrator/Kconfig"
909 source "arch/arm/mach-iop32x/Kconfig"
911 source "arch/arm/mach-iop33x/Kconfig"
913 source "arch/arm/mach-iop13xx/Kconfig"
915 source "arch/arm/mach-ixp4xx/Kconfig"
917 source "arch/arm/mach-ixp2000/Kconfig"
919 source "arch/arm/mach-ixp23xx/Kconfig"
921 source "arch/arm/mach-kirkwood/Kconfig"
923 source "arch/arm/mach-ks8695/Kconfig"
925 source "arch/arm/mach-loki/Kconfig"
927 source "arch/arm/mach-lpc32xx/Kconfig"
929 source "arch/arm/mach-msm/Kconfig"
931 source "arch/arm/mach-mv78xx0/Kconfig"
933 source "arch/arm/plat-mxc/Kconfig"
935 source "arch/arm/mach-mxs/Kconfig"
937 source "arch/arm/mach-netx/Kconfig"
939 source "arch/arm/mach-nomadik/Kconfig"
940 source "arch/arm/plat-nomadik/Kconfig"
942 source "arch/arm/mach-nuc93x/Kconfig"
944 source "arch/arm/plat-omap/Kconfig"
946 source "arch/arm/mach-omap1/Kconfig"
948 source "arch/arm/mach-omap2/Kconfig"
950 source "arch/arm/mach-orion5x/Kconfig"
952 source "arch/arm/mach-pxa/Kconfig"
953 source "arch/arm/plat-pxa/Kconfig"
955 source "arch/arm/mach-mmp/Kconfig"
957 source "arch/arm/mach-realview/Kconfig"
959 source "arch/arm/mach-sa1100/Kconfig"
961 source "arch/arm/plat-samsung/Kconfig"
962 source "arch/arm/plat-s3c24xx/Kconfig"
963 source "arch/arm/plat-s5p/Kconfig"
965 source "arch/arm/plat-spear/Kconfig"
967 source "arch/arm/plat-tcc/Kconfig"
970 source "arch/arm/mach-s3c2400/Kconfig"
971 source "arch/arm/mach-s3c2410/Kconfig"
972 source "arch/arm/mach-s3c2412/Kconfig"
973 source "arch/arm/mach-s3c2416/Kconfig"
974 source "arch/arm/mach-s3c2440/Kconfig"
975 source "arch/arm/mach-s3c2443/Kconfig"
979 source "arch/arm/mach-s3c64xx/Kconfig"
982 source "arch/arm/mach-s5p64x0/Kconfig"
984 source "arch/arm/mach-s5p6442/Kconfig"
986 source "arch/arm/mach-s5pc100/Kconfig"
988 source "arch/arm/mach-s5pv210/Kconfig"
990 source "arch/arm/mach-exynos4/Kconfig"
992 source "arch/arm/mach-shmobile/Kconfig"
994 source "arch/arm/plat-stmp3xxx/Kconfig"
996 source "arch/arm/mach-tegra/Kconfig"
998 source "arch/arm/mach-u300/Kconfig"
1000 source "arch/arm/mach-ux500/Kconfig"
1002 source "arch/arm/mach-versatile/Kconfig"
1004 source "arch/arm/mach-vexpress/Kconfig"
1005 source "arch/arm/plat-versatile/Kconfig"
1007 source "arch/arm/mach-vt8500/Kconfig"
1009 source "arch/arm/mach-w90x900/Kconfig"
1011 # Definitions to make life easier
1017 select GENERIC_CLOCKEVENTS
1018 select HAVE_SCHED_CLOCK
1022 select HAVE_SCHED_CLOCK
1027 config PLAT_VERSATILE
1030 config ARM_TIMER_SP804
1033 source arch/arm/mm/Kconfig
1036 bool "Enable iWMMXt support"
1037 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1038 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1040 Enable support for iWMMXt context switching at run time if
1041 running on a CPU that supports it.
1043 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1046 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1050 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1051 (!ARCH_OMAP3 || OMAP3_EMU)
1055 config MULTI_IRQ_HANDLER
1058 Allow each machine to specify it's own IRQ handler at run time.
1061 source "arch/arm/Kconfig-nommu"
1064 config ARM_ERRATA_411920
1065 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1066 depends on CPU_V6 || CPU_V6K
1068 Invalidation of the Instruction Cache operation can
1069 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1070 It does not affect the MPCore. This option enables the ARM Ltd.
1071 recommended workaround.
1073 config ARM_ERRATA_430973
1074 bool "ARM errata: Stale prediction on replaced interworking branch"
1077 This option enables the workaround for the 430973 Cortex-A8
1078 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1079 interworking branch is replaced with another code sequence at the
1080 same virtual address, whether due to self-modifying code or virtual
1081 to physical address re-mapping, Cortex-A8 does not recover from the
1082 stale interworking branch prediction. This results in Cortex-A8
1083 executing the new code sequence in the incorrect ARM or Thumb state.
1084 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1085 and also flushes the branch target cache at every context switch.
1086 Note that setting specific bits in the ACTLR register may not be
1087 available in non-secure mode.
1089 config ARM_ERRATA_458693
1090 bool "ARM errata: Processor deadlock when a false hazard is created"
1093 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1094 erratum. For very specific sequences of memory operations, it is
1095 possible for a hazard condition intended for a cache line to instead
1096 be incorrectly associated with a different cache line. This false
1097 hazard might then cause a processor deadlock. The workaround enables
1098 the L1 caching of the NEON accesses and disables the PLD instruction
1099 in the ACTLR register. Note that setting specific bits in the ACTLR
1100 register may not be available in non-secure mode.
1102 config ARM_ERRATA_460075
1103 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1106 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1107 erratum. Any asynchronous access to the L2 cache may encounter a
1108 situation in which recent store transactions to the L2 cache are lost
1109 and overwritten with stale memory contents from external memory. The
1110 workaround disables the write-allocate mode for the L2 cache via the
1111 ACTLR register. Note that setting specific bits in the ACTLR register
1112 may not be available in non-secure mode.
1114 config ARM_ERRATA_742230
1115 bool "ARM errata: DMB operation may be faulty"
1116 depends on CPU_V7 && SMP
1118 This option enables the workaround for the 742230 Cortex-A9
1119 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1120 between two write operations may not ensure the correct visibility
1121 ordering of the two writes. This workaround sets a specific bit in
1122 the diagnostic register of the Cortex-A9 which causes the DMB
1123 instruction to behave as a DSB, ensuring the correct behaviour of
1126 config ARM_ERRATA_742231
1127 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1128 depends on CPU_V7 && SMP
1130 This option enables the workaround for the 742231 Cortex-A9
1131 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1132 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1133 accessing some data located in the same cache line, may get corrupted
1134 data due to bad handling of the address hazard when the line gets
1135 replaced from one of the CPUs at the same time as another CPU is
1136 accessing it. This workaround sets specific bits in the diagnostic
1137 register of the Cortex-A9 which reduces the linefill issuing
1138 capabilities of the processor.
1140 config PL310_ERRATA_588369
1141 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1142 depends on CACHE_L2X0
1144 The PL310 L2 cache controller implements three types of Clean &
1145 Invalidate maintenance operations: by Physical Address
1146 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1147 They are architecturally defined to behave as the execution of a
1148 clean operation followed immediately by an invalidate operation,
1149 both performing to the same memory location. This functionality
1150 is not correctly implemented in PL310 as clean lines are not
1151 invalidated as a result of these operations.
1153 config ARM_ERRATA_720789
1154 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1155 depends on CPU_V7 && SMP
1157 This option enables the workaround for the 720789 Cortex-A9 (prior to
1158 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1159 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1160 As a consequence of this erratum, some TLB entries which should be
1161 invalidated are not, resulting in an incoherency in the system page
1162 tables. The workaround changes the TLB flushing routines to invalidate
1163 entries regardless of the ASID.
1165 config PL310_ERRATA_727915
1166 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1167 depends on CACHE_L2X0
1169 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1170 operation (offset 0x7FC). This operation runs in background so that
1171 PL310 can handle normal accesses while it is in progress. Under very
1172 rare circumstances, due to this erratum, write data can be lost when
1173 PL310 treats a cacheable write transaction during a Clean &
1174 Invalidate by Way operation.
1176 config ARM_ERRATA_743622
1177 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1180 This option enables the workaround for the 743622 Cortex-A9
1181 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1182 optimisation in the Cortex-A9 Store Buffer may lead to data
1183 corruption. This workaround sets a specific bit in the diagnostic
1184 register of the Cortex-A9 which disables the Store Buffer
1185 optimisation, preventing the defect from occurring. This has no
1186 visible impact on the overall performance or power consumption of the
1189 config ARM_ERRATA_751472
1190 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1191 depends on CPU_V7 && SMP
1193 This option enables the workaround for the 751472 Cortex-A9 (prior
1194 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1195 completion of a following broadcasted operation if the second
1196 operation is received by a CPU before the ICIALLUIS has completed,
1197 potentially leading to corrupted entries in the cache or TLB.
1199 config ARM_ERRATA_753970
1200 bool "ARM errata: cache sync operation may be faulty"
1201 depends on CACHE_PL310
1203 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1205 Under some condition the effect of cache sync operation on
1206 the store buffer still remains when the operation completes.
1207 This means that the store buffer is always asked to drain and
1208 this prevents it from merging any further writes. The workaround
1209 is to replace the normal offset of cache sync operation (0x730)
1210 by another offset targeting an unmapped PL310 register 0x740.
1211 This has the same effect as the cache sync operation: store buffer
1212 drain and waiting for all buffers empty.
1214 config ARM_ERRATA_754322
1215 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1218 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1219 r3p*) erratum. A speculative memory access may cause a page table walk
1220 which starts prior to an ASID switch but completes afterwards. This
1221 can populate the micro-TLB with a stale entry which may be hit with
1222 the new ASID. This workaround places two dsb instructions in the mm
1223 switching code so that no page table walks can cross the ASID switch.
1225 config ARM_ERRATA_754327
1226 bool "ARM errata: no automatic Store Buffer drain"
1227 depends on CPU_V7 && SMP
1229 This option enables the workaround for the 754327 Cortex-A9 (prior to
1230 r2p0) erratum. The Store Buffer does not have any automatic draining
1231 mechanism and therefore a livelock may occur if an external agent
1232 continuously polls a memory location waiting to observe an update.
1233 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1234 written polling loops from denying visibility of updates to memory.
1238 source "arch/arm/common/Kconfig"
1248 Find out whether you have ISA slots on your motherboard. ISA is the
1249 name of a bus system, i.e. the way the CPU talks to the other stuff
1250 inside your box. Other bus systems are PCI, EISA, MicroChannel
1251 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1252 newer boards don't support it. If you have ISA, say Y, otherwise N.
1254 # Select ISA DMA controller support
1259 # Select ISA DMA interface
1264 bool "PCI support" if MIGHT_HAVE_PCI
1266 Find out whether you have a PCI motherboard. PCI is the name of a
1267 bus system, i.e. the way the CPU talks to the other stuff inside
1268 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1269 VESA. If you have PCI, say Y, otherwise N.
1275 config PCI_NANOENGINE
1276 bool "BSE nanoEngine PCI support"
1277 depends on SA1100_NANOENGINE
1279 Enable PCI on the BSE nanoEngine board.
1284 # Select the host bridge type
1285 config PCI_HOST_VIA82C505
1287 depends on PCI && ARCH_SHARK
1290 config PCI_HOST_ITE8152
1292 depends on PCI && MACH_ARMCORE
1296 source "drivers/pci/Kconfig"
1298 source "drivers/pcmcia/Kconfig"
1302 menu "Kernel Features"
1304 source "kernel/time/Kconfig"
1307 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1308 depends on EXPERIMENTAL
1309 depends on CPU_V6K || CPU_V7
1310 depends on GENERIC_CLOCKEVENTS
1311 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1312 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1313 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1314 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1315 select USE_GENERIC_SMP_HELPERS
1316 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1318 This enables support for systems with more than one CPU. If you have
1319 a system with only one CPU, like most personal computers, say N. If
1320 you have a system with more than one CPU, say Y.
1322 If you say N here, the kernel will run on single and multiprocessor
1323 machines, but will use only one CPU of a multiprocessor machine. If
1324 you say Y here, the kernel will run on many, but not all, single
1325 processor machines. On a single processor machine, the kernel will
1326 run faster if you say N here.
1328 See also <file:Documentation/i386/IO-APIC.txt>,
1329 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1330 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1332 If you don't know what to do here, say N.
1335 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1336 depends on EXPERIMENTAL
1337 depends on SMP && !XIP_KERNEL
1340 SMP kernels contain instructions which fail on non-SMP processors.
1341 Enabling this option allows the kernel to modify itself to make
1342 these instructions safe. Disabling it allows about 1K of space
1345 If you don't know what to do here, say Y.
1351 This option enables support for the ARM system coherency unit
1358 This options enables support for the ARM timer and watchdog unit
1361 prompt "Memory split"
1364 Select the desired split between kernel and user memory.
1366 If you are not absolutely sure what you are doing, leave this
1370 bool "3G/1G user/kernel split"
1372 bool "2G/2G user/kernel split"
1374 bool "1G/3G user/kernel split"
1379 default 0x40000000 if VMSPLIT_1G
1380 default 0x80000000 if VMSPLIT_2G
1384 int "Maximum number of CPUs (2-32)"
1390 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1391 depends on SMP && HOTPLUG && EXPERIMENTAL
1392 depends on !ARCH_MSM
1394 Say Y here to experiment with turning CPUs off and on. CPUs
1395 can be controlled through /sys/devices/system/cpu.
1398 bool "Use local timer interrupts"
1401 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1403 Enable support for local timers on SMP platforms, rather then the
1404 legacy IPI broadcast method. Local timers allows the system
1405 accounting to be spread across the timer interval, preventing a
1406 "thundering herd" at every timer tick.
1408 source kernel/Kconfig.preempt
1412 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1413 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1414 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1415 default AT91_TIMER_HZ if ARCH_AT91
1416 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1419 config THUMB2_KERNEL
1420 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1421 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1423 select ARM_ASM_UNIFIED
1425 By enabling this option, the kernel will be compiled in
1426 Thumb-2 mode. A compiler/assembler that understand the unified
1427 ARM-Thumb syntax is needed.
1431 config THUMB2_AVOID_R_ARM_THM_JUMP11
1432 bool "Work around buggy Thumb-2 short branch relocations in gas"
1433 depends on THUMB2_KERNEL && MODULES
1436 Various binutils versions can resolve Thumb-2 branches to
1437 locally-defined, preemptible global symbols as short-range "b.n"
1438 branch instructions.
1440 This is a problem, because there's no guarantee the final
1441 destination of the symbol, or any candidate locations for a
1442 trampoline, are within range of the branch. For this reason, the
1443 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1444 relocation in modules at all, and it makes little sense to add
1447 The symptom is that the kernel fails with an "unsupported
1448 relocation" error when loading some modules.
1450 Until fixed tools are available, passing
1451 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1452 code which hits this problem, at the cost of a bit of extra runtime
1453 stack usage in some cases.
1455 The problem is described in more detail at:
1456 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1458 Only Thumb-2 kernels are affected.
1460 Unless you are sure your tools don't have this problem, say Y.
1462 config ARM_ASM_UNIFIED
1466 bool "Use the ARM EABI to compile the kernel"
1468 This option allows for the kernel to be compiled using the latest
1469 ARM ABI (aka EABI). This is only useful if you are using a user
1470 space environment that is also compiled with EABI.
1472 Since there are major incompatibilities between the legacy ABI and
1473 EABI, especially with regard to structure member alignment, this
1474 option also changes the kernel syscall calling convention to
1475 disambiguate both ABIs and allow for backward compatibility support
1476 (selected with CONFIG_OABI_COMPAT).
1478 To use this you need GCC version 4.0.0 or later.
1481 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1482 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1485 This option preserves the old syscall interface along with the
1486 new (ARM EABI) one. It also provides a compatibility layer to
1487 intercept syscalls that have structure arguments which layout
1488 in memory differs between the legacy ABI and the new ARM EABI
1489 (only for non "thumb" binaries). This option adds a tiny
1490 overhead to all syscalls and produces a slightly larger kernel.
1491 If you know you'll be using only pure EABI user space then you
1492 can say N here. If this option is not selected and you attempt
1493 to execute a legacy ABI binary then the result will be
1494 UNPREDICTABLE (in fact it can be predicted that it won't work
1495 at all). If in doubt say Y.
1497 config ARCH_HAS_HOLES_MEMORYMODEL
1500 config ARCH_SPARSEMEM_ENABLE
1503 config ARCH_SPARSEMEM_DEFAULT
1504 def_bool ARCH_SPARSEMEM_ENABLE
1506 config ARCH_SELECT_MEMORY_MODEL
1507 def_bool ARCH_SPARSEMEM_ENABLE
1510 bool "High Memory Support (EXPERIMENTAL)"
1511 depends on MMU && EXPERIMENTAL
1513 The address space of ARM processors is only 4 Gigabytes large
1514 and it has to accommodate user address space, kernel address
1515 space as well as some memory mapped IO. That means that, if you
1516 have a large amount of physical memory and/or IO, not all of the
1517 memory can be "permanently mapped" by the kernel. The physical
1518 memory that is not permanently mapped is called "high memory".
1520 Depending on the selected kernel/user memory split, minimum
1521 vmalloc space and actual amount of RAM, you may not need this
1522 option which should result in a slightly faster kernel.
1527 bool "Allocate 2nd-level pagetables from highmem"
1530 config HW_PERF_EVENTS
1531 bool "Enable hardware performance counter support for perf events"
1532 depends on PERF_EVENTS && CPU_HAS_PMU
1535 Enable hardware performance counter support for perf events. If
1536 disabled, perf events will use software events only.
1540 config FORCE_MAX_ZONEORDER
1541 int "Maximum zone order" if ARCH_SHMOBILE
1542 range 11 64 if ARCH_SHMOBILE
1543 default "9" if SA1111
1546 The kernel memory allocator divides physically contiguous memory
1547 blocks into "zones", where each zone is a power of two number of
1548 pages. This option selects the largest power of two that the kernel
1549 keeps in the memory allocator. If you need to allocate very large
1550 blocks of physically contiguous memory, then you may need to
1551 increase this value.
1553 This config option is actually maximum order plus one. For example,
1554 a value of 11 means that the largest free memory block is 2^10 pages.
1557 bool "Timer and CPU usage LEDs"
1558 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1559 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1560 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1561 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1562 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1563 ARCH_AT91 || ARCH_DAVINCI || \
1564 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1566 If you say Y here, the LEDs on your machine will be used
1567 to provide useful information about your current system status.
1569 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1570 be able to select which LEDs are active using the options below. If
1571 you are compiling a kernel for the EBSA-110 or the LART however, the
1572 red LED will simply flash regularly to indicate that the system is
1573 still functional. It is safe to say Y here if you have a CATS
1574 system, but the driver will do nothing.
1577 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1578 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1579 || MACH_OMAP_PERSEUS2
1581 depends on !GENERIC_CLOCKEVENTS
1582 default y if ARCH_EBSA110
1584 If you say Y here, one of the system LEDs (the green one on the
1585 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1586 will flash regularly to indicate that the system is still
1587 operational. This is mainly useful to kernel hackers who are
1588 debugging unstable kernels.
1590 The LART uses the same LED for both Timer LED and CPU usage LED
1591 functions. You may choose to use both, but the Timer LED function
1592 will overrule the CPU usage LED.
1595 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1597 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1598 || MACH_OMAP_PERSEUS2
1601 If you say Y here, the red LED will be used to give a good real
1602 time indication of CPU usage, by lighting whenever the idle task
1603 is not currently executing.
1605 The LART uses the same LED for both Timer LED and CPU usage LED
1606 functions. You may choose to use both, but the Timer LED function
1607 will overrule the CPU usage LED.
1609 config ALIGNMENT_TRAP
1611 depends on CPU_CP15_MMU
1612 default y if !ARCH_EBSA110
1613 select HAVE_PROC_CPU if PROC_FS
1615 ARM processors cannot fetch/store information which is not
1616 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1617 address divisible by 4. On 32-bit ARM processors, these non-aligned
1618 fetch/store instructions will be emulated in software if you say
1619 here, which has a severe performance impact. This is necessary for
1620 correct operation of some network protocols. With an IP-only
1621 configuration it is safe to say N, otherwise say Y.
1623 config UACCESS_WITH_MEMCPY
1624 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1625 depends on MMU && EXPERIMENTAL
1626 default y if CPU_FEROCEON
1628 Implement faster copy_to_user and clear_user methods for CPU
1629 cores where a 8-word STM instruction give significantly higher
1630 memory write throughput than a sequence of individual 32bit stores.
1632 A possible side effect is a slight increase in scheduling latency
1633 between threads sharing the same address space if they invoke
1634 such copy operations with large buffers.
1636 However, if the CPU data cache is using a write-allocate mode,
1637 this option is unlikely to provide any performance gain.
1641 prompt "Enable seccomp to safely compute untrusted bytecode"
1643 This kernel feature is useful for number crunching applications
1644 that may need to compute untrusted bytecode during their
1645 execution. By using pipes or other transports made available to
1646 the process as file descriptors supporting the read/write
1647 syscalls, it's possible to isolate those applications in
1648 their own address space using seccomp. Once seccomp is
1649 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1650 and the task is only allowed to execute a few safe syscalls
1651 defined by each seccomp mode.
1653 config CC_STACKPROTECTOR
1654 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1655 depends on EXPERIMENTAL
1657 This option turns on the -fstack-protector GCC feature. This
1658 feature puts, at the beginning of functions, a canary value on
1659 the stack just before the return address, and validates
1660 the value just before actually returning. Stack based buffer
1661 overflows (that need to overwrite this return address) now also
1662 overwrite the canary, which gets detected and the attack is then
1663 neutralized via a kernel panic.
1664 This feature requires gcc version 4.2 or above.
1666 config DEPRECATED_PARAM_STRUCT
1667 bool "Provide old way to pass kernel parameters"
1669 This was deprecated in 2001 and announced to live on for 5 years.
1670 Some old boot loaders still use this way.
1676 # Compressed boot loader in ROM. Yes, we really want to ask about
1677 # TEXT and BSS so we preserve their values in the config files.
1678 config ZBOOT_ROM_TEXT
1679 hex "Compressed ROM boot loader base address"
1682 The physical address at which the ROM-able zImage is to be
1683 placed in the target. Platforms which normally make use of
1684 ROM-able zImage formats normally set this to a suitable
1685 value in their defconfig file.
1687 If ZBOOT_ROM is not enabled, this has no effect.
1689 config ZBOOT_ROM_BSS
1690 hex "Compressed ROM boot loader BSS address"
1693 The base address of an area of read/write memory in the target
1694 for the ROM-able zImage which must be available while the
1695 decompressor is running. It must be large enough to hold the
1696 entire decompressed kernel plus an additional 128 KiB.
1697 Platforms which normally make use of ROM-able zImage formats
1698 normally set this to a suitable value in their defconfig file.
1700 If ZBOOT_ROM is not enabled, this has no effect.
1703 bool "Compressed boot loader in ROM/flash"
1704 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1706 Say Y here if you intend to execute your compressed kernel image
1707 (zImage) directly from ROM or flash. If unsure, say N.
1709 config ZBOOT_ROM_MMCIF
1710 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1711 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1713 Say Y here to include experimental MMCIF loading code in the
1714 ROM-able zImage. With this enabled it is possible to write the
1715 the ROM-able zImage kernel image to an MMC card and boot the
1716 kernel straight from the reset vector. At reset the processor
1717 Mask ROM will load the first part of the the ROM-able zImage
1718 which in turn loads the rest the kernel image to RAM using the
1719 MMCIF hardware block.
1722 string "Default kernel command string"
1725 On some architectures (EBSA110 and CATS), there is currently no way
1726 for the boot loader to pass arguments to the kernel. For these
1727 architectures, you should supply some command-line options at build
1728 time by entering them here. As a minimum, you should specify the
1729 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1731 config CMDLINE_FORCE
1732 bool "Always use the default kernel command string"
1733 depends on CMDLINE != ""
1735 Always use the default kernel command string, even if the boot
1736 loader passes other arguments to the kernel.
1737 This is useful if you cannot or don't want to change the
1738 command-line options your boot loader passes to the kernel.
1743 bool "Kernel Execute-In-Place from ROM"
1744 depends on !ZBOOT_ROM
1746 Execute-In-Place allows the kernel to run from non-volatile storage
1747 directly addressable by the CPU, such as NOR flash. This saves RAM
1748 space since the text section of the kernel is not loaded from flash
1749 to RAM. Read-write sections, such as the data section and stack,
1750 are still copied to RAM. The XIP kernel is not compressed since
1751 it has to run directly from flash, so it will take more space to
1752 store it. The flash address used to link the kernel object files,
1753 and for storing it, is configuration dependent. Therefore, if you
1754 say Y here, you must know the proper physical address where to
1755 store the kernel image depending on your own flash memory usage.
1757 Also note that the make target becomes "make xipImage" rather than
1758 "make zImage" or "make Image". The final kernel binary to put in
1759 ROM memory will be arch/arm/boot/xipImage.
1763 config XIP_PHYS_ADDR
1764 hex "XIP Kernel Physical Location"
1765 depends on XIP_KERNEL
1766 default "0x00080000"
1768 This is the physical address in your flash memory the kernel will
1769 be linked for and stored to. This address is dependent on your
1773 bool "Kexec system call (EXPERIMENTAL)"
1774 depends on EXPERIMENTAL
1776 kexec is a system call that implements the ability to shutdown your
1777 current kernel, and to start another kernel. It is like a reboot
1778 but it is independent of the system firmware. And like a reboot
1779 you can start any kernel with it, not just Linux.
1781 It is an ongoing process to be certain the hardware in a machine
1782 is properly shutdown, so do not be surprised if this code does not
1783 initially work for you. It may help to enable device hotplugging
1787 bool "Export atags in procfs"
1791 Should the atags used to boot the kernel be exported in an "atags"
1792 file in procfs. Useful with kexec.
1795 bool "Build kdump crash kernel (EXPERIMENTAL)"
1796 depends on EXPERIMENTAL
1798 Generate crash dump after being started by kexec. This should
1799 be normally only set in special crash dump kernels which are
1800 loaded in the main kernel with kexec-tools into a specially
1801 reserved region and then later executed after a crash by
1802 kdump/kexec. The crash dump kernel must be compiled to a
1803 memory address not used by the main kernel
1805 For more details see Documentation/kdump/kdump.txt
1807 config AUTO_ZRELADDR
1808 bool "Auto calculation of the decompressed kernel image address"
1809 depends on !ZBOOT_ROM && !ARCH_U300
1811 ZRELADDR is the physical address where the decompressed kernel
1812 image will be placed. If AUTO_ZRELADDR is selected, the address
1813 will be determined at run-time by masking the current IP with
1814 0xf8000000. This assumes the zImage being placed in the first 128MB
1815 from start of memory.
1819 menu "CPU Power Management"
1823 source "drivers/cpufreq/Kconfig"
1826 tristate "CPUfreq driver for i.MX CPUs"
1827 depends on ARCH_MXC && CPU_FREQ
1829 This enables the CPUfreq driver for i.MX CPUs.
1831 config CPU_FREQ_SA1100
1834 config CPU_FREQ_SA1110
1837 config CPU_FREQ_INTEGRATOR
1838 tristate "CPUfreq driver for ARM Integrator CPUs"
1839 depends on ARCH_INTEGRATOR && CPU_FREQ
1842 This enables the CPUfreq driver for ARM Integrator CPUs.
1844 For details, take a look at <file:Documentation/cpu-freq>.
1850 depends on CPU_FREQ && ARCH_PXA && PXA25x
1852 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1854 config CPU_FREQ_S3C64XX
1855 bool "CPUfreq support for Samsung S3C64XX CPUs"
1856 depends on CPU_FREQ && CPU_S3C6410
1861 Internal configuration node for common cpufreq on Samsung SoC
1863 config CPU_FREQ_S3C24XX
1864 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1865 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1868 This enables the CPUfreq driver for the Samsung S3C24XX family
1871 For details, take a look at <file:Documentation/cpu-freq>.
1875 config CPU_FREQ_S3C24XX_PLL
1876 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1877 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1879 Compile in support for changing the PLL frequency from the
1880 S3C24XX series CPUfreq driver. The PLL takes time to settle
1881 after a frequency change, so by default it is not enabled.
1883 This also means that the PLL tables for the selected CPU(s) will
1884 be built which may increase the size of the kernel image.
1886 config CPU_FREQ_S3C24XX_DEBUG
1887 bool "Debug CPUfreq Samsung driver core"
1888 depends on CPU_FREQ_S3C24XX
1890 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1892 config CPU_FREQ_S3C24XX_IODEBUG
1893 bool "Debug CPUfreq Samsung driver IO timing"
1894 depends on CPU_FREQ_S3C24XX
1896 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1898 config CPU_FREQ_S3C24XX_DEBUGFS
1899 bool "Export debugfs for CPUFreq"
1900 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1902 Export status information via debugfs.
1906 source "drivers/cpuidle/Kconfig"
1910 menu "Floating point emulation"
1912 comment "At least one emulation must be selected"
1915 bool "NWFPE math emulation"
1916 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1918 Say Y to include the NWFPE floating point emulator in the kernel.
1919 This is necessary to run most binaries. Linux does not currently
1920 support floating point hardware so you need to say Y here even if
1921 your machine has an FPA or floating point co-processor podule.
1923 You may say N here if you are going to load the Acorn FPEmulator
1924 early in the bootup.
1927 bool "Support extended precision"
1928 depends on FPE_NWFPE
1930 Say Y to include 80-bit support in the kernel floating-point
1931 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1932 Note that gcc does not generate 80-bit operations by default,
1933 so in most cases this option only enlarges the size of the
1934 floating point emulator without any good reason.
1936 You almost surely want to say N here.
1939 bool "FastFPE math emulation (EXPERIMENTAL)"
1940 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1942 Say Y here to include the FAST floating point emulator in the kernel.
1943 This is an experimental much faster emulator which now also has full
1944 precision for the mantissa. It does not support any exceptions.
1945 It is very simple, and approximately 3-6 times faster than NWFPE.
1947 It should be sufficient for most programs. It may be not suitable
1948 for scientific calculations, but you have to check this for yourself.
1949 If you do not feel you need a faster FP emulation you should better
1953 bool "VFP-format floating point maths"
1954 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1956 Say Y to include VFP support code in the kernel. This is needed
1957 if your hardware includes a VFP unit.
1959 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1960 release notes and additional status information.
1962 Say N if your target does not have VFP hardware.
1970 bool "Advanced SIMD (NEON) Extension support"
1971 depends on VFPv3 && CPU_V7
1973 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1978 menu "Userspace binary formats"
1980 source "fs/Kconfig.binfmt"
1983 tristate "RISC OS personality"
1986 Say Y here to include the kernel code necessary if you want to run
1987 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1988 experimental; if this sounds frightening, say N and sleep in peace.
1989 You can also say M here to compile this support as a module (which
1990 will be called arthur).
1994 menu "Power management options"
1996 source "kernel/power/Kconfig"
1998 config ARCH_SUSPEND_POSSIBLE
1999 depends on !ARCH_S5P64X0 && !ARCH_S5P6442
2000 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2001 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2006 source "net/Kconfig"
2008 source "drivers/Kconfig"
2012 source "arch/arm/Kconfig.debug"
2014 source "security/Kconfig"
2016 source "crypto/Kconfig"
2018 source "lib/Kconfig"