5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
72 select GENERIC_ALLOCATOR
83 The Extended Industry Standard Architecture (EISA) bus was
84 developed as an open alternative to the IBM MicroChannel bus.
86 The EISA bus provided some of the features of the IBM MicroChannel
87 bus while maintaining backward compatibility with cards made for
88 the older ISA bus. The EISA bus saw limited use between 1988 and
89 1995 when it was made obsolete by the PCI bus.
91 Say Y here if you are building a kernel for an EISA-based machine.
101 MicroChannel Architecture is found in some IBM PS/2 machines and
102 laptops. It is a bus system similar to PCI or ISA. See
103 <file:Documentation/mca.txt> (and especially the web page given
104 there) before attempting to build an MCA bus kernel.
106 config STACKTRACE_SUPPORT
110 config HAVE_LATENCYTOP_SUPPORT
115 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
123 config HARDIRQS_SW_RESEND
127 config GENERIC_IRQ_PROBE
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 The base address of exception vectors.
193 config ARM_PATCH_PHYS_VIRT
194 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
195 depends on EXPERIMENTAL
196 depends on !XIP_KERNEL && MMU
197 depends on !ARCH_REALVIEW || !SPARSEMEM
199 Patch phys-to-virt translation functions at runtime according to
200 the position of the kernel in system memory.
202 This can only be used with non-XIP with MMU kernels where
203 the base of physical memory is at a 16MB boundary.
205 config ARM_PATCH_PHYS_VIRT_16BIT
207 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
209 source "init/Kconfig"
211 source "kernel/Kconfig.freezer"
216 bool "MMU-based Paged Memory Management Support"
219 Select if you want MMU-based virtualised addressing space
220 support by paged memory management. If unsure, say 'Y'.
223 # The "ARM system type" choice list is ordered alphabetically by option
224 # text. Please add new entries in the option alphabetic order.
227 prompt "ARM system type"
228 default ARCH_VERSATILE
231 bool "Agilent AAEC-2000 based"
235 select ARCH_USES_GETTIMEOFFSET
237 This enables support for systems based on the Agilent AAEC-2000
239 config ARCH_INTEGRATOR
240 bool "ARM Ltd. Integrator family"
242 select ARCH_HAS_CPUFREQ
245 select GENERIC_CLOCKEVENTS
246 select PLAT_VERSATILE
248 Support for ARM's Integrator platform.
251 bool "ARM Ltd. RealView family"
254 select HAVE_SCHED_CLOCK
256 select GENERIC_CLOCKEVENTS
257 select ARCH_WANT_OPTIONAL_GPIOLIB
258 select PLAT_VERSATILE
259 select ARM_TIMER_SP804
260 select GPIO_PL061 if GPIOLIB
262 This enables support for ARM Ltd RealView boards.
264 config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
269 select HAVE_SCHED_CLOCK
271 select GENERIC_CLOCKEVENTS
272 select ARCH_WANT_OPTIONAL_GPIOLIB
273 select PLAT_VERSATILE
274 select ARM_TIMER_SP804
276 This enables support for ARM Ltd Versatile board.
279 bool "ARM Ltd. Versatile Express family"
280 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select ARM_TIMER_SP804
284 select GENERIC_CLOCKEVENTS
286 select HAVE_SCHED_CLOCK
288 select PLAT_VERSATILE
290 This enables support for the ARM Ltd Versatile Express boards.
294 select ARCH_REQUIRE_GPIOLIB
297 This enables support for systems based on the Atmel AT91RM9200,
298 AT91SAM9 and AT91CAP9 processors.
301 bool "Broadcom BCMRING"
306 select GENERIC_CLOCKEVENTS
307 select ARCH_WANT_OPTIONAL_GPIOLIB
309 Support for Broadcom's BCMRing platform.
312 bool "Cirrus Logic CLPS711x/EP721x-based"
314 select ARCH_USES_GETTIMEOFFSET
316 Support for Cirrus Logic 711x/721x based boards.
319 bool "Cavium Networks CNS3XXX family"
321 select GENERIC_CLOCKEVENTS
323 select MIGHT_HAVE_PCI
324 select PCI_DOMAINS if PCI
326 Support for Cavium Networks CNS3XXX platform.
329 bool "Cortina Systems Gemini"
331 select ARCH_REQUIRE_GPIOLIB
332 select ARCH_USES_GETTIMEOFFSET
334 Support for the Cortina Systems Gemini family SoCs
341 select ARCH_USES_GETTIMEOFFSET
343 This is an evaluation board for the StrongARM processor available
344 from Digital. It has limited hardware on-board, including an
345 Ethernet interface, two PCMCIA sockets, two serial ports and a
354 select ARCH_REQUIRE_GPIOLIB
355 select ARCH_HAS_HOLES_MEMORYMODEL
356 select ARCH_USES_GETTIMEOFFSET
358 This enables support for the Cirrus EP93xx series of CPUs.
360 config ARCH_FOOTBRIDGE
364 select GENERIC_CLOCKEVENTS
366 Support for systems based on the DC21285 companion chip
367 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
370 bool "Freescale MXC/iMX-based"
371 select GENERIC_CLOCKEVENTS
372 select ARCH_REQUIRE_GPIOLIB
375 Support for Freescale MXC/iMX-based family of processors
378 bool "Freescale MXS-based"
379 select GENERIC_CLOCKEVENTS
380 select ARCH_REQUIRE_GPIOLIB
383 Support for Freescale MXS-based family of processors
386 bool "Freescale STMP3xxx"
389 select ARCH_REQUIRE_GPIOLIB
390 select GENERIC_CLOCKEVENTS
391 select USB_ARCH_HAS_EHCI
393 Support for systems based on the Freescale 3xxx CPUs.
396 bool "Hilscher NetX based"
399 select GENERIC_CLOCKEVENTS
401 This enables support for systems based on the Hilscher NetX Soc
404 bool "Hynix HMS720x-based"
407 select ARCH_USES_GETTIMEOFFSET
409 This enables support for systems based on the Hynix HMS720x
417 select ARCH_SUPPORTS_MSI
420 Support for Intel's IOP13XX (XScale) family of processors.
428 select ARCH_REQUIRE_GPIOLIB
430 Support for Intel's 80219 and IOP32X (XScale) family of
439 select ARCH_REQUIRE_GPIOLIB
441 Support for Intel's IOP33X (XScale) family of processors.
448 select ARCH_USES_GETTIMEOFFSET
450 Support for Intel's IXP23xx (XScale) family of processors.
453 bool "IXP2400/2800-based"
457 select ARCH_USES_GETTIMEOFFSET
459 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
505 select ARCH_REQUIRE_GPIOLIB
508 select USB_ARCH_HAS_OHCI
511 select GENERIC_CLOCKEVENTS
513 Support for the NXP LPC32XX family of processors
516 bool "Marvell MV78xx0"
519 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
523 Support for the following Marvell MV78xx0 series SoCs:
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 Support for the following Marvell Orion 5x series SoCs:
536 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
537 Orion-2 (5281), Orion-1-90 (6183).
540 bool "Marvell PXA168/910/MMP2"
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
545 select HAVE_SCHED_CLOCK
550 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
553 bool "Micrel/Kendin KS8695"
555 select ARCH_REQUIRE_GPIOLIB
556 select ARCH_USES_GETTIMEOFFSET
558 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
559 System-on-Chip devices.
562 bool "NetSilicon NS9xxx"
565 select GENERIC_CLOCKEVENTS
568 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
571 <http://www.digi.com/products/microprocessors/index.jsp>
574 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
580 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
581 At present, the w90x900 has been renamed nuc900, regarding
582 the ARM series product line, you can login the following
583 link address to know more.
585 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
586 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
589 bool "Nuvoton NUC93X CPU"
593 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
594 low-power and high performance MPEG-4/JPEG multimedia controller chip.
600 select GENERIC_CLOCKEVENTS
603 select HAVE_SCHED_CLOCK
604 select ARCH_HAS_BARRIERS if CACHE_L2X0
605 select ARCH_HAS_CPUFREQ
607 This enables support for NVIDIA Tegra based systems (Tegra APX,
608 Tegra 6xx and Tegra 2 series).
611 bool "Philips Nexperia PNX4008 Mobile"
614 select ARCH_USES_GETTIMEOFFSET
616 This enables support for Philips PNX4008 mobile platform.
619 bool "PXA2xx/PXA3xx-based"
622 select ARCH_HAS_CPUFREQ
624 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
626 select HAVE_SCHED_CLOCK
631 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
636 select GENERIC_CLOCKEVENTS
637 select ARCH_REQUIRE_GPIOLIB
640 Support for Qualcomm MSM/QSD based systems. This runs on the
641 apps processor of the MSM/QSD and depends on a shared memory
642 interface to the modem processor which runs the baseband
643 stack and controls some vital subsystems
644 (clock and power control, etc).
647 bool "Renesas SH-Mobile / R-Mobile"
650 select GENERIC_CLOCKEVENTS
653 select MULTI_IRQ_HANDLER
655 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
662 select ARCH_MAY_HAVE_PC_FDC
663 select HAVE_PATA_PLATFORM
666 select ARCH_SPARSEMEM_ENABLE
667 select ARCH_USES_GETTIMEOFFSET
669 On the Acorn Risc-PC, Linux can support the internal IDE disk and
670 CD-ROM interface, serial and parallel port, and the floppy drive.
676 select ARCH_SPARSEMEM_ENABLE
678 select ARCH_HAS_CPUFREQ
680 select GENERIC_CLOCKEVENTS
682 select HAVE_SCHED_CLOCK
684 select ARCH_REQUIRE_GPIOLIB
686 Support for StrongARM 11x0 based boards.
689 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
691 select ARCH_HAS_CPUFREQ
693 select ARCH_USES_GETTIMEOFFSET
694 select HAVE_S3C2410_I2C if I2C
696 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
697 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
698 the Samsung SMDK2410 development board (and derivatives).
700 Note, the S3C2416 and the S3C2450 are so close that they even share
701 the same SoC ID code. This means that there is no seperate machine
702 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
705 bool "Samsung S3C64XX"
711 select ARCH_USES_GETTIMEOFFSET
712 select ARCH_HAS_CPUFREQ
713 select ARCH_REQUIRE_GPIOLIB
714 select SAMSUNG_CLKSRC
715 select SAMSUNG_IRQ_VIC_TIMER
716 select SAMSUNG_IRQ_UART
717 select S3C_GPIO_TRACK
718 select S3C_GPIO_PULL_UPDOWN
719 select S3C_GPIO_CFG_S3C24XX
720 select S3C_GPIO_CFG_S3C64XX
722 select USB_ARCH_HAS_OHCI
723 select SAMSUNG_GPIOLIB_4BIT
724 select HAVE_S3C2410_I2C if I2C
725 select HAVE_S3C2410_WATCHDOG if WATCHDOG
727 Samsung S3C64XX series based systems
730 bool "Samsung S5P6440 S5P6450"
734 select HAVE_S3C2410_WATCHDOG if WATCHDOG
735 select ARCH_USES_GETTIMEOFFSET
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C_RTC if RTC_CLASS
739 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
743 bool "Samsung S5P6442"
747 select ARCH_USES_GETTIMEOFFSET
748 select HAVE_S3C2410_WATCHDOG if WATCHDOG
750 Samsung S5P6442 CPU based systems
753 bool "Samsung S5PC100"
757 select ARM_L1_CACHE_SHIFT_6
758 select ARCH_USES_GETTIMEOFFSET
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C_RTC if RTC_CLASS
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 Samsung S5PC100 series based systems
766 bool "Samsung S5PV210/S5PC110"
768 select ARCH_SPARSEMEM_ENABLE
771 select ARM_L1_CACHE_SHIFT_6
772 select ARCH_HAS_CPUFREQ
773 select ARCH_USES_GETTIMEOFFSET
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C_RTC if RTC_CLASS
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
778 Samsung S5PV210/S5PC110 series based systems
781 bool "Samsung S5PV310/S5PC210"
783 select ARCH_SPARSEMEM_ENABLE
786 select ARCH_HAS_CPUFREQ
787 select GENERIC_CLOCKEVENTS
788 select HAVE_S3C_RTC if RTC_CLASS
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C2410_WATCHDOG if WATCHDOG
792 Samsung S5PV310 series based systems
801 select ARCH_USES_GETTIMEOFFSET
803 Support for the StrongARM based Digital DNARD machine, also known
804 as "Shark" (<http://www.shark-linux.de/shark.html>).
807 bool "Telechips TCC ARM926-based systems"
811 select GENERIC_CLOCKEVENTS
813 Support for Telechips TCC ARM926-based systems.
818 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
819 select ARCH_USES_GETTIMEOFFSET
821 Say Y here for systems based on one of the Sharp LH7A40X
822 System on a Chip processors. These CPUs include an ARM922T
823 core with a wide array of integrated devices for
824 hand-held and low-power applications.
827 bool "ST-Ericsson U300 Series"
830 select HAVE_SCHED_CLOCK
834 select GENERIC_CLOCKEVENTS
838 Support for ST-Ericsson U300 series mobile platforms.
841 bool "ST-Ericsson U8500 Series"
844 select GENERIC_CLOCKEVENTS
846 select ARCH_REQUIRE_GPIOLIB
847 select ARCH_HAS_CPUFREQ
849 Support for ST-Ericsson's Ux500 architecture
852 bool "STMicroelectronics Nomadik"
857 select GENERIC_CLOCKEVENTS
858 select ARCH_REQUIRE_GPIOLIB
860 Support for the Nomadik platform by ST-Ericsson
864 select GENERIC_CLOCKEVENTS
865 select ARCH_REQUIRE_GPIOLIB
869 select GENERIC_ALLOCATOR
870 select ARCH_HAS_HOLES_MEMORYMODEL
872 Support for TI's DaVinci platform.
877 select ARCH_REQUIRE_GPIOLIB
878 select ARCH_HAS_CPUFREQ
879 select GENERIC_CLOCKEVENTS
880 select HAVE_SCHED_CLOCK
881 select ARCH_HAS_HOLES_MEMORYMODEL
883 Support for TI's OMAP platform (OMAP1/2/3/4).
888 select ARCH_REQUIRE_GPIOLIB
890 select GENERIC_CLOCKEVENTS
893 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
896 bool "VIA/WonderMedia 85xx"
899 select ARCH_HAS_CPUFREQ
900 select GENERIC_CLOCKEVENTS
901 select ARCH_REQUIRE_GPIOLIB
904 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
908 # This is sorted alphabetically by mach-* pathname. However, plat-*
909 # Kconfigs may be included either alphabetically (according to the
910 # plat- suffix) or along side the corresponding mach-* source.
912 source "arch/arm/mach-aaec2000/Kconfig"
914 source "arch/arm/mach-at91/Kconfig"
916 source "arch/arm/mach-bcmring/Kconfig"
918 source "arch/arm/mach-clps711x/Kconfig"
920 source "arch/arm/mach-cns3xxx/Kconfig"
922 source "arch/arm/mach-davinci/Kconfig"
924 source "arch/arm/mach-dove/Kconfig"
926 source "arch/arm/mach-ep93xx/Kconfig"
928 source "arch/arm/mach-footbridge/Kconfig"
930 source "arch/arm/mach-gemini/Kconfig"
932 source "arch/arm/mach-h720x/Kconfig"
934 source "arch/arm/mach-integrator/Kconfig"
936 source "arch/arm/mach-iop32x/Kconfig"
938 source "arch/arm/mach-iop33x/Kconfig"
940 source "arch/arm/mach-iop13xx/Kconfig"
942 source "arch/arm/mach-ixp4xx/Kconfig"
944 source "arch/arm/mach-ixp2000/Kconfig"
946 source "arch/arm/mach-ixp23xx/Kconfig"
948 source "arch/arm/mach-kirkwood/Kconfig"
950 source "arch/arm/mach-ks8695/Kconfig"
952 source "arch/arm/mach-lh7a40x/Kconfig"
954 source "arch/arm/mach-loki/Kconfig"
956 source "arch/arm/mach-lpc32xx/Kconfig"
958 source "arch/arm/mach-msm/Kconfig"
960 source "arch/arm/mach-mv78xx0/Kconfig"
962 source "arch/arm/plat-mxc/Kconfig"
964 source "arch/arm/mach-mxs/Kconfig"
966 source "arch/arm/mach-netx/Kconfig"
968 source "arch/arm/mach-nomadik/Kconfig"
969 source "arch/arm/plat-nomadik/Kconfig"
971 source "arch/arm/mach-ns9xxx/Kconfig"
973 source "arch/arm/mach-nuc93x/Kconfig"
975 source "arch/arm/plat-omap/Kconfig"
977 source "arch/arm/mach-omap1/Kconfig"
979 source "arch/arm/mach-omap2/Kconfig"
981 source "arch/arm/mach-orion5x/Kconfig"
983 source "arch/arm/mach-pxa/Kconfig"
984 source "arch/arm/plat-pxa/Kconfig"
986 source "arch/arm/mach-mmp/Kconfig"
988 source "arch/arm/mach-realview/Kconfig"
990 source "arch/arm/mach-sa1100/Kconfig"
992 source "arch/arm/plat-samsung/Kconfig"
993 source "arch/arm/plat-s3c24xx/Kconfig"
994 source "arch/arm/plat-s5p/Kconfig"
996 source "arch/arm/plat-spear/Kconfig"
998 source "arch/arm/plat-tcc/Kconfig"
1001 source "arch/arm/mach-s3c2400/Kconfig"
1002 source "arch/arm/mach-s3c2410/Kconfig"
1003 source "arch/arm/mach-s3c2412/Kconfig"
1004 source "arch/arm/mach-s3c2416/Kconfig"
1005 source "arch/arm/mach-s3c2440/Kconfig"
1006 source "arch/arm/mach-s3c2443/Kconfig"
1010 source "arch/arm/mach-s3c64xx/Kconfig"
1013 source "arch/arm/mach-s5p64x0/Kconfig"
1015 source "arch/arm/mach-s5p6442/Kconfig"
1017 source "arch/arm/mach-s5pc100/Kconfig"
1019 source "arch/arm/mach-s5pv210/Kconfig"
1021 source "arch/arm/mach-s5pv310/Kconfig"
1023 source "arch/arm/mach-shmobile/Kconfig"
1025 source "arch/arm/plat-stmp3xxx/Kconfig"
1027 source "arch/arm/mach-tegra/Kconfig"
1029 source "arch/arm/mach-u300/Kconfig"
1031 source "arch/arm/mach-ux500/Kconfig"
1033 source "arch/arm/mach-versatile/Kconfig"
1035 source "arch/arm/mach-vexpress/Kconfig"
1037 source "arch/arm/mach-vt8500/Kconfig"
1039 source "arch/arm/mach-w90x900/Kconfig"
1041 # Definitions to make life easier
1047 select GENERIC_CLOCKEVENTS
1048 select HAVE_SCHED_CLOCK
1052 select HAVE_SCHED_CLOCK
1057 config PLAT_VERSATILE
1060 config ARM_TIMER_SP804
1063 source arch/arm/mm/Kconfig
1066 bool "Enable iWMMXt support"
1067 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1068 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1070 Enable support for iWMMXt context switching at run time if
1071 running on a CPU that supports it.
1073 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1076 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1080 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1081 (!ARCH_OMAP3 || OMAP3_EMU)
1085 config MULTI_IRQ_HANDLER
1088 Allow each machine to specify it's own IRQ handler at run time.
1091 source "arch/arm/Kconfig-nommu"
1094 config ARM_ERRATA_411920
1095 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1096 depends on CPU_V6 || CPU_V6K
1098 Invalidation of the Instruction Cache operation can
1099 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1100 It does not affect the MPCore. This option enables the ARM Ltd.
1101 recommended workaround.
1103 config ARM_ERRATA_430973
1104 bool "ARM errata: Stale prediction on replaced interworking branch"
1107 This option enables the workaround for the 430973 Cortex-A8
1108 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1109 interworking branch is replaced with another code sequence at the
1110 same virtual address, whether due to self-modifying code or virtual
1111 to physical address re-mapping, Cortex-A8 does not recover from the
1112 stale interworking branch prediction. This results in Cortex-A8
1113 executing the new code sequence in the incorrect ARM or Thumb state.
1114 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1115 and also flushes the branch target cache at every context switch.
1116 Note that setting specific bits in the ACTLR register may not be
1117 available in non-secure mode.
1119 config ARM_ERRATA_458693
1120 bool "ARM errata: Processor deadlock when a false hazard is created"
1123 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1124 erratum. For very specific sequences of memory operations, it is
1125 possible for a hazard condition intended for a cache line to instead
1126 be incorrectly associated with a different cache line. This false
1127 hazard might then cause a processor deadlock. The workaround enables
1128 the L1 caching of the NEON accesses and disables the PLD instruction
1129 in the ACTLR register. Note that setting specific bits in the ACTLR
1130 register may not be available in non-secure mode.
1132 config ARM_ERRATA_460075
1133 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1136 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1137 erratum. Any asynchronous access to the L2 cache may encounter a
1138 situation in which recent store transactions to the L2 cache are lost
1139 and overwritten with stale memory contents from external memory. The
1140 workaround disables the write-allocate mode for the L2 cache via the
1141 ACTLR register. Note that setting specific bits in the ACTLR register
1142 may not be available in non-secure mode.
1144 config ARM_ERRATA_742230
1145 bool "ARM errata: DMB operation may be faulty"
1146 depends on CPU_V7 && SMP
1148 This option enables the workaround for the 742230 Cortex-A9
1149 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1150 between two write operations may not ensure the correct visibility
1151 ordering of the two writes. This workaround sets a specific bit in
1152 the diagnostic register of the Cortex-A9 which causes the DMB
1153 instruction to behave as a DSB, ensuring the correct behaviour of
1156 config ARM_ERRATA_742231
1157 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1158 depends on CPU_V7 && SMP
1160 This option enables the workaround for the 742231 Cortex-A9
1161 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1162 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1163 accessing some data located in the same cache line, may get corrupted
1164 data due to bad handling of the address hazard when the line gets
1165 replaced from one of the CPUs at the same time as another CPU is
1166 accessing it. This workaround sets specific bits in the diagnostic
1167 register of the Cortex-A9 which reduces the linefill issuing
1168 capabilities of the processor.
1170 config PL310_ERRATA_588369
1171 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1172 depends on CACHE_L2X0
1174 The PL310 L2 cache controller implements three types of Clean &
1175 Invalidate maintenance operations: by Physical Address
1176 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1177 They are architecturally defined to behave as the execution of a
1178 clean operation followed immediately by an invalidate operation,
1179 both performing to the same memory location. This functionality
1180 is not correctly implemented in PL310 as clean lines are not
1181 invalidated as a result of these operations.
1183 config ARM_ERRATA_720789
1184 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1185 depends on CPU_V7 && SMP
1187 This option enables the workaround for the 720789 Cortex-A9 (prior to
1188 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1189 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1190 As a consequence of this erratum, some TLB entries which should be
1191 invalidated are not, resulting in an incoherency in the system page
1192 tables. The workaround changes the TLB flushing routines to invalidate
1193 entries regardless of the ASID.
1195 config PL310_ERRATA_727915
1196 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1197 depends on CACHE_L2X0
1199 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1200 operation (offset 0x7FC). This operation runs in background so that
1201 PL310 can handle normal accesses while it is in progress. Under very
1202 rare circumstances, due to this erratum, write data can be lost when
1203 PL310 treats a cacheable write transaction during a Clean &
1204 Invalidate by Way operation.
1206 config ARM_ERRATA_743622
1207 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1210 This option enables the workaround for the 743622 Cortex-A9
1211 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1212 optimisation in the Cortex-A9 Store Buffer may lead to data
1213 corruption. This workaround sets a specific bit in the diagnostic
1214 register of the Cortex-A9 which disables the Store Buffer
1215 optimisation, preventing the defect from occurring. This has no
1216 visible impact on the overall performance or power consumption of the
1219 config ARM_ERRATA_751472
1220 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1221 depends on CPU_V7 && SMP
1223 This option enables the workaround for the 751472 Cortex-A9 (prior
1224 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1225 completion of a following broadcasted operation if the second
1226 operation is received by a CPU before the ICIALLUIS has completed,
1227 potentially leading to corrupted entries in the cache or TLB.
1229 config ARM_ERRATA_753970
1230 bool "ARM errata: cache sync operation may be faulty"
1231 depends on CACHE_PL310
1233 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1235 Under some condition the effect of cache sync operation on
1236 the store buffer still remains when the operation completes.
1237 This means that the store buffer is always asked to drain and
1238 this prevents it from merging any further writes. The workaround
1239 is to replace the normal offset of cache sync operation (0x730)
1240 by another offset targeting an unmapped PL310 register 0x740.
1241 This has the same effect as the cache sync operation: store buffer
1242 drain and waiting for all buffers empty.
1244 config ARM_ERRATA_754322
1245 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1248 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1249 r3p*) erratum. A speculative memory access may cause a page table walk
1250 which starts prior to an ASID switch but completes afterwards. This
1251 can populate the micro-TLB with a stale entry which may be hit with
1252 the new ASID. This workaround places two dsb instructions in the mm
1253 switching code so that no page table walks can cross the ASID switch.
1255 config ARM_ERRATA_754327
1256 bool "ARM errata: no automatic Store Buffer drain"
1257 depends on CPU_V7 && SMP
1259 This option enables the workaround for the 754327 Cortex-A9 (prior to
1260 r2p0) erratum. The Store Buffer does not have any automatic draining
1261 mechanism and therefore a livelock may occur if an external agent
1262 continuously polls a memory location waiting to observe an update.
1263 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1264 written polling loops from denying visibility of updates to memory.
1268 source "arch/arm/common/Kconfig"
1278 Find out whether you have ISA slots on your motherboard. ISA is the
1279 name of a bus system, i.e. the way the CPU talks to the other stuff
1280 inside your box. Other bus systems are PCI, EISA, MicroChannel
1281 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1282 newer boards don't support it. If you have ISA, say Y, otherwise N.
1284 # Select ISA DMA controller support
1289 # Select ISA DMA interface
1294 bool "PCI support" if MIGHT_HAVE_PCI
1296 Find out whether you have a PCI motherboard. PCI is the name of a
1297 bus system, i.e. the way the CPU talks to the other stuff inside
1298 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1299 VESA. If you have PCI, say Y, otherwise N.
1305 config PCI_NANOENGINE
1306 bool "BSE nanoEngine PCI support"
1307 depends on SA1100_NANOENGINE
1309 Enable PCI on the BSE nanoEngine board.
1314 # Select the host bridge type
1315 config PCI_HOST_VIA82C505
1317 depends on PCI && ARCH_SHARK
1320 config PCI_HOST_ITE8152
1322 depends on PCI && MACH_ARMCORE
1326 source "drivers/pci/Kconfig"
1328 source "drivers/pcmcia/Kconfig"
1332 menu "Kernel Features"
1334 source "kernel/time/Kconfig"
1337 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1338 depends on EXPERIMENTAL
1339 depends on CPU_V6K || CPU_V7
1340 depends on GENERIC_CLOCKEVENTS
1341 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1342 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1343 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1344 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1345 select USE_GENERIC_SMP_HELPERS
1346 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1348 This enables support for systems with more than one CPU. If you have
1349 a system with only one CPU, like most personal computers, say N. If
1350 you have a system with more than one CPU, say Y.
1352 If you say N here, the kernel will run on single and multiprocessor
1353 machines, but will use only one CPU of a multiprocessor machine. If
1354 you say Y here, the kernel will run on many, but not all, single
1355 processor machines. On a single processor machine, the kernel will
1356 run faster if you say N here.
1358 See also <file:Documentation/i386/IO-APIC.txt>,
1359 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1360 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1362 If you don't know what to do here, say N.
1365 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1366 depends on EXPERIMENTAL
1367 depends on SMP && !XIP_KERNEL
1370 SMP kernels contain instructions which fail on non-SMP processors.
1371 Enabling this option allows the kernel to modify itself to make
1372 these instructions safe. Disabling it allows about 1K of space
1375 If you don't know what to do here, say Y.
1381 This option enables support for the ARM system coherency unit
1388 This options enables support for the ARM timer and watchdog unit
1391 prompt "Memory split"
1394 Select the desired split between kernel and user memory.
1396 If you are not absolutely sure what you are doing, leave this
1400 bool "3G/1G user/kernel split"
1402 bool "2G/2G user/kernel split"
1404 bool "1G/3G user/kernel split"
1409 default 0x40000000 if VMSPLIT_1G
1410 default 0x80000000 if VMSPLIT_2G
1414 int "Maximum number of CPUs (2-32)"
1420 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1421 depends on SMP && HOTPLUG && EXPERIMENTAL
1422 depends on !ARCH_MSM
1424 Say Y here to experiment with turning CPUs off and on. CPUs
1425 can be controlled through /sys/devices/system/cpu.
1428 bool "Use local timer interrupts"
1431 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1433 Enable support for local timers on SMP platforms, rather then the
1434 legacy IPI broadcast method. Local timers allows the system
1435 accounting to be spread across the timer interval, preventing a
1436 "thundering herd" at every timer tick.
1438 source kernel/Kconfig.preempt
1442 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1443 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1444 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1445 default AT91_TIMER_HZ if ARCH_AT91
1446 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1449 config THUMB2_KERNEL
1450 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1451 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1453 select ARM_ASM_UNIFIED
1455 By enabling this option, the kernel will be compiled in
1456 Thumb-2 mode. A compiler/assembler that understand the unified
1457 ARM-Thumb syntax is needed.
1461 config THUMB2_AVOID_R_ARM_THM_JUMP11
1462 bool "Work around buggy Thumb-2 short branch relocations in gas"
1463 depends on THUMB2_KERNEL && MODULES
1466 Various binutils versions can resolve Thumb-2 branches to
1467 locally-defined, preemptible global symbols as short-range "b.n"
1468 branch instructions.
1470 This is a problem, because there's no guarantee the final
1471 destination of the symbol, or any candidate locations for a
1472 trampoline, are within range of the branch. For this reason, the
1473 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1474 relocation in modules at all, and it makes little sense to add
1477 The symptom is that the kernel fails with an "unsupported
1478 relocation" error when loading some modules.
1480 Until fixed tools are available, passing
1481 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1482 code which hits this problem, at the cost of a bit of extra runtime
1483 stack usage in some cases.
1485 The problem is described in more detail at:
1486 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1488 Only Thumb-2 kernels are affected.
1490 Unless you are sure your tools don't have this problem, say Y.
1492 config ARM_ASM_UNIFIED
1496 bool "Use the ARM EABI to compile the kernel"
1498 This option allows for the kernel to be compiled using the latest
1499 ARM ABI (aka EABI). This is only useful if you are using a user
1500 space environment that is also compiled with EABI.
1502 Since there are major incompatibilities between the legacy ABI and
1503 EABI, especially with regard to structure member alignment, this
1504 option also changes the kernel syscall calling convention to
1505 disambiguate both ABIs and allow for backward compatibility support
1506 (selected with CONFIG_OABI_COMPAT).
1508 To use this you need GCC version 4.0.0 or later.
1511 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1512 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1515 This option preserves the old syscall interface along with the
1516 new (ARM EABI) one. It also provides a compatibility layer to
1517 intercept syscalls that have structure arguments which layout
1518 in memory differs between the legacy ABI and the new ARM EABI
1519 (only for non "thumb" binaries). This option adds a tiny
1520 overhead to all syscalls and produces a slightly larger kernel.
1521 If you know you'll be using only pure EABI user space then you
1522 can say N here. If this option is not selected and you attempt
1523 to execute a legacy ABI binary then the result will be
1524 UNPREDICTABLE (in fact it can be predicted that it won't work
1525 at all). If in doubt say Y.
1527 config ARCH_HAS_HOLES_MEMORYMODEL
1530 config ARCH_SPARSEMEM_ENABLE
1533 config ARCH_SPARSEMEM_DEFAULT
1534 def_bool ARCH_SPARSEMEM_ENABLE
1536 config ARCH_SELECT_MEMORY_MODEL
1537 def_bool ARCH_SPARSEMEM_ENABLE
1540 bool "High Memory Support (EXPERIMENTAL)"
1541 depends on MMU && EXPERIMENTAL
1543 The address space of ARM processors is only 4 Gigabytes large
1544 and it has to accommodate user address space, kernel address
1545 space as well as some memory mapped IO. That means that, if you
1546 have a large amount of physical memory and/or IO, not all of the
1547 memory can be "permanently mapped" by the kernel. The physical
1548 memory that is not permanently mapped is called "high memory".
1550 Depending on the selected kernel/user memory split, minimum
1551 vmalloc space and actual amount of RAM, you may not need this
1552 option which should result in a slightly faster kernel.
1557 bool "Allocate 2nd-level pagetables from highmem"
1559 depends on !OUTER_CACHE
1561 config HW_PERF_EVENTS
1562 bool "Enable hardware performance counter support for perf events"
1563 depends on PERF_EVENTS && CPU_HAS_PMU
1566 Enable hardware performance counter support for perf events. If
1567 disabled, perf events will use software events only.
1571 config FORCE_MAX_ZONEORDER
1572 int "Maximum zone order" if ARCH_SHMOBILE
1573 range 11 64 if ARCH_SHMOBILE
1574 default "9" if SA1111
1577 The kernel memory allocator divides physically contiguous memory
1578 blocks into "zones", where each zone is a power of two number of
1579 pages. This option selects the largest power of two that the kernel
1580 keeps in the memory allocator. If you need to allocate very large
1581 blocks of physically contiguous memory, then you may need to
1582 increase this value.
1584 This config option is actually maximum order plus one. For example,
1585 a value of 11 means that the largest free memory block is 2^10 pages.
1588 bool "Timer and CPU usage LEDs"
1589 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1590 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1591 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1592 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1593 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1594 ARCH_AT91 || ARCH_DAVINCI || \
1595 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1597 If you say Y here, the LEDs on your machine will be used
1598 to provide useful information about your current system status.
1600 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1601 be able to select which LEDs are active using the options below. If
1602 you are compiling a kernel for the EBSA-110 or the LART however, the
1603 red LED will simply flash regularly to indicate that the system is
1604 still functional. It is safe to say Y here if you have a CATS
1605 system, but the driver will do nothing.
1608 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1609 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1610 || MACH_OMAP_PERSEUS2
1612 depends on !GENERIC_CLOCKEVENTS
1613 default y if ARCH_EBSA110
1615 If you say Y here, one of the system LEDs (the green one on the
1616 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1617 will flash regularly to indicate that the system is still
1618 operational. This is mainly useful to kernel hackers who are
1619 debugging unstable kernels.
1621 The LART uses the same LED for both Timer LED and CPU usage LED
1622 functions. You may choose to use both, but the Timer LED function
1623 will overrule the CPU usage LED.
1626 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1628 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1629 || MACH_OMAP_PERSEUS2
1632 If you say Y here, the red LED will be used to give a good real
1633 time indication of CPU usage, by lighting whenever the idle task
1634 is not currently executing.
1636 The LART uses the same LED for both Timer LED and CPU usage LED
1637 functions. You may choose to use both, but the Timer LED function
1638 will overrule the CPU usage LED.
1640 config ALIGNMENT_TRAP
1642 depends on CPU_CP15_MMU
1643 default y if !ARCH_EBSA110
1644 select HAVE_PROC_CPU if PROC_FS
1646 ARM processors cannot fetch/store information which is not
1647 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1648 address divisible by 4. On 32-bit ARM processors, these non-aligned
1649 fetch/store instructions will be emulated in software if you say
1650 here, which has a severe performance impact. This is necessary for
1651 correct operation of some network protocols. With an IP-only
1652 configuration it is safe to say N, otherwise say Y.
1654 config UACCESS_WITH_MEMCPY
1655 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1656 depends on MMU && EXPERIMENTAL
1657 default y if CPU_FEROCEON
1659 Implement faster copy_to_user and clear_user methods for CPU
1660 cores where a 8-word STM instruction give significantly higher
1661 memory write throughput than a sequence of individual 32bit stores.
1663 A possible side effect is a slight increase in scheduling latency
1664 between threads sharing the same address space if they invoke
1665 such copy operations with large buffers.
1667 However, if the CPU data cache is using a write-allocate mode,
1668 this option is unlikely to provide any performance gain.
1672 prompt "Enable seccomp to safely compute untrusted bytecode"
1674 This kernel feature is useful for number crunching applications
1675 that may need to compute untrusted bytecode during their
1676 execution. By using pipes or other transports made available to
1677 the process as file descriptors supporting the read/write
1678 syscalls, it's possible to isolate those applications in
1679 their own address space using seccomp. Once seccomp is
1680 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1681 and the task is only allowed to execute a few safe syscalls
1682 defined by each seccomp mode.
1684 config CC_STACKPROTECTOR
1685 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1686 depends on EXPERIMENTAL
1688 This option turns on the -fstack-protector GCC feature. This
1689 feature puts, at the beginning of functions, a canary value on
1690 the stack just before the return address, and validates
1691 the value just before actually returning. Stack based buffer
1692 overflows (that need to overwrite this return address) now also
1693 overwrite the canary, which gets detected and the attack is then
1694 neutralized via a kernel panic.
1695 This feature requires gcc version 4.2 or above.
1697 config DEPRECATED_PARAM_STRUCT
1698 bool "Provide old way to pass kernel parameters"
1700 This was deprecated in 2001 and announced to live on for 5 years.
1701 Some old boot loaders still use this way.
1707 # Compressed boot loader in ROM. Yes, we really want to ask about
1708 # TEXT and BSS so we preserve their values in the config files.
1709 config ZBOOT_ROM_TEXT
1710 hex "Compressed ROM boot loader base address"
1713 The physical address at which the ROM-able zImage is to be
1714 placed in the target. Platforms which normally make use of
1715 ROM-able zImage formats normally set this to a suitable
1716 value in their defconfig file.
1718 If ZBOOT_ROM is not enabled, this has no effect.
1720 config ZBOOT_ROM_BSS
1721 hex "Compressed ROM boot loader BSS address"
1724 The base address of an area of read/write memory in the target
1725 for the ROM-able zImage which must be available while the
1726 decompressor is running. It must be large enough to hold the
1727 entire decompressed kernel plus an additional 128 KiB.
1728 Platforms which normally make use of ROM-able zImage formats
1729 normally set this to a suitable value in their defconfig file.
1731 If ZBOOT_ROM is not enabled, this has no effect.
1734 bool "Compressed boot loader in ROM/flash"
1735 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1737 Say Y here if you intend to execute your compressed kernel image
1738 (zImage) directly from ROM or flash. If unsure, say N.
1740 config ZBOOT_ROM_MMCIF
1741 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1742 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1744 Say Y here to include experimental MMCIF loading code in the
1745 ROM-able zImage. With this enabled it is possible to write the
1746 the ROM-able zImage kernel image to an MMC card and boot the
1747 kernel straight from the reset vector. At reset the processor
1748 Mask ROM will load the first part of the the ROM-able zImage
1749 which in turn loads the rest the kernel image to RAM using the
1750 MMCIF hardware block.
1753 string "Default kernel command string"
1756 On some architectures (EBSA110 and CATS), there is currently no way
1757 for the boot loader to pass arguments to the kernel. For these
1758 architectures, you should supply some command-line options at build
1759 time by entering them here. As a minimum, you should specify the
1760 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1762 config CMDLINE_FORCE
1763 bool "Always use the default kernel command string"
1764 depends on CMDLINE != ""
1766 Always use the default kernel command string, even if the boot
1767 loader passes other arguments to the kernel.
1768 This is useful if you cannot or don't want to change the
1769 command-line options your boot loader passes to the kernel.
1774 bool "Kernel Execute-In-Place from ROM"
1775 depends on !ZBOOT_ROM
1777 Execute-In-Place allows the kernel to run from non-volatile storage
1778 directly addressable by the CPU, such as NOR flash. This saves RAM
1779 space since the text section of the kernel is not loaded from flash
1780 to RAM. Read-write sections, such as the data section and stack,
1781 are still copied to RAM. The XIP kernel is not compressed since
1782 it has to run directly from flash, so it will take more space to
1783 store it. The flash address used to link the kernel object files,
1784 and for storing it, is configuration dependent. Therefore, if you
1785 say Y here, you must know the proper physical address where to
1786 store the kernel image depending on your own flash memory usage.
1788 Also note that the make target becomes "make xipImage" rather than
1789 "make zImage" or "make Image". The final kernel binary to put in
1790 ROM memory will be arch/arm/boot/xipImage.
1794 config XIP_PHYS_ADDR
1795 hex "XIP Kernel Physical Location"
1796 depends on XIP_KERNEL
1797 default "0x00080000"
1799 This is the physical address in your flash memory the kernel will
1800 be linked for and stored to. This address is dependent on your
1804 bool "Kexec system call (EXPERIMENTAL)"
1805 depends on EXPERIMENTAL
1807 kexec is a system call that implements the ability to shutdown your
1808 current kernel, and to start another kernel. It is like a reboot
1809 but it is independent of the system firmware. And like a reboot
1810 you can start any kernel with it, not just Linux.
1812 It is an ongoing process to be certain the hardware in a machine
1813 is properly shutdown, so do not be surprised if this code does not
1814 initially work for you. It may help to enable device hotplugging
1818 bool "Export atags in procfs"
1822 Should the atags used to boot the kernel be exported in an "atags"
1823 file in procfs. Useful with kexec.
1826 bool "Build kdump crash kernel (EXPERIMENTAL)"
1827 depends on EXPERIMENTAL
1829 Generate crash dump after being started by kexec. This should
1830 be normally only set in special crash dump kernels which are
1831 loaded in the main kernel with kexec-tools into a specially
1832 reserved region and then later executed after a crash by
1833 kdump/kexec. The crash dump kernel must be compiled to a
1834 memory address not used by the main kernel
1836 For more details see Documentation/kdump/kdump.txt
1838 config AUTO_ZRELADDR
1839 bool "Auto calculation of the decompressed kernel image address"
1840 depends on !ZBOOT_ROM && !ARCH_U300
1842 ZRELADDR is the physical address where the decompressed kernel
1843 image will be placed. If AUTO_ZRELADDR is selected, the address
1844 will be determined at run-time by masking the current IP with
1845 0xf8000000. This assumes the zImage being placed in the first 128MB
1846 from start of memory.
1850 menu "CPU Power Management"
1854 source "drivers/cpufreq/Kconfig"
1857 tristate "CPUfreq driver for i.MX CPUs"
1858 depends on ARCH_MXC && CPU_FREQ
1860 This enables the CPUfreq driver for i.MX CPUs.
1862 config CPU_FREQ_SA1100
1865 config CPU_FREQ_SA1110
1868 config CPU_FREQ_INTEGRATOR
1869 tristate "CPUfreq driver for ARM Integrator CPUs"
1870 depends on ARCH_INTEGRATOR && CPU_FREQ
1873 This enables the CPUfreq driver for ARM Integrator CPUs.
1875 For details, take a look at <file:Documentation/cpu-freq>.
1881 depends on CPU_FREQ && ARCH_PXA && PXA25x
1883 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1885 config CPU_FREQ_S3C64XX
1886 bool "CPUfreq support for Samsung S3C64XX CPUs"
1887 depends on CPU_FREQ && CPU_S3C6410
1892 Internal configuration node for common cpufreq on Samsung SoC
1894 config CPU_FREQ_S3C24XX
1895 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1896 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1899 This enables the CPUfreq driver for the Samsung S3C24XX family
1902 For details, take a look at <file:Documentation/cpu-freq>.
1906 config CPU_FREQ_S3C24XX_PLL
1907 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1908 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1910 Compile in support for changing the PLL frequency from the
1911 S3C24XX series CPUfreq driver. The PLL takes time to settle
1912 after a frequency change, so by default it is not enabled.
1914 This also means that the PLL tables for the selected CPU(s) will
1915 be built which may increase the size of the kernel image.
1917 config CPU_FREQ_S3C24XX_DEBUG
1918 bool "Debug CPUfreq Samsung driver core"
1919 depends on CPU_FREQ_S3C24XX
1921 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1923 config CPU_FREQ_S3C24XX_IODEBUG
1924 bool "Debug CPUfreq Samsung driver IO timing"
1925 depends on CPU_FREQ_S3C24XX
1927 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1929 config CPU_FREQ_S3C24XX_DEBUGFS
1930 bool "Export debugfs for CPUFreq"
1931 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1933 Export status information via debugfs.
1937 source "drivers/cpuidle/Kconfig"
1941 menu "Floating point emulation"
1943 comment "At least one emulation must be selected"
1946 bool "NWFPE math emulation"
1947 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1949 Say Y to include the NWFPE floating point emulator in the kernel.
1950 This is necessary to run most binaries. Linux does not currently
1951 support floating point hardware so you need to say Y here even if
1952 your machine has an FPA or floating point co-processor podule.
1954 You may say N here if you are going to load the Acorn FPEmulator
1955 early in the bootup.
1958 bool "Support extended precision"
1959 depends on FPE_NWFPE
1961 Say Y to include 80-bit support in the kernel floating-point
1962 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1963 Note that gcc does not generate 80-bit operations by default,
1964 so in most cases this option only enlarges the size of the
1965 floating point emulator without any good reason.
1967 You almost surely want to say N here.
1970 bool "FastFPE math emulation (EXPERIMENTAL)"
1971 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1973 Say Y here to include the FAST floating point emulator in the kernel.
1974 This is an experimental much faster emulator which now also has full
1975 precision for the mantissa. It does not support any exceptions.
1976 It is very simple, and approximately 3-6 times faster than NWFPE.
1978 It should be sufficient for most programs. It may be not suitable
1979 for scientific calculations, but you have to check this for yourself.
1980 If you do not feel you need a faster FP emulation you should better
1984 bool "VFP-format floating point maths"
1985 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1987 Say Y to include VFP support code in the kernel. This is needed
1988 if your hardware includes a VFP unit.
1990 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1991 release notes and additional status information.
1993 Say N if your target does not have VFP hardware.
2001 bool "Advanced SIMD (NEON) Extension support"
2002 depends on VFPv3 && CPU_V7
2004 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2009 menu "Userspace binary formats"
2011 source "fs/Kconfig.binfmt"
2014 tristate "RISC OS personality"
2017 Say Y here to include the kernel code necessary if you want to run
2018 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2019 experimental; if this sounds frightening, say N and sleep in peace.
2020 You can also say M here to compile this support as a module (which
2021 will be called arthur).
2025 menu "Power management options"
2027 source "kernel/power/Kconfig"
2029 config ARCH_SUSPEND_POSSIBLE
2034 source "net/Kconfig"
2036 source "drivers/Kconfig"
2040 source "arch/arm/Kconfig.debug"
2042 source "security/Kconfig"
2044 source "crypto/Kconfig"
2046 source "lib/Kconfig"