5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
219 source "init/Kconfig"
221 source "kernel/Kconfig.freezer"
226 bool "MMU-based Paged Memory Management Support"
229 Select if you want MMU-based virtualised addressing space
230 support by paged memory management. If unsure, say 'Y'.
233 # The "ARM system type" choice list is ordered alphabetically by option
234 # text. Please add new entries in the option alphabetic order.
237 prompt "ARM system type"
238 default ARCH_VERSATILE
240 config ARCH_INTEGRATOR
241 bool "ARM Ltd. Integrator family"
243 select ARCH_HAS_CPUFREQ
245 select HAVE_MACH_CLKDEV
247 select GENERIC_CLOCKEVENTS
248 select PLAT_VERSATILE
249 select PLAT_VERSATILE_FPGA_IRQ
251 Support for ARM's Integrator platform.
254 bool "ARM Ltd. RealView family"
257 select HAVE_MACH_CLKDEV
259 select GENERIC_CLOCKEVENTS
260 select ARCH_WANT_OPTIONAL_GPIOLIB
261 select PLAT_VERSATILE
262 select PLAT_VERSATILE_CLCD
263 select ARM_TIMER_SP804
264 select GPIO_PL061 if GPIOLIB
266 This enables support for ARM Ltd RealView boards.
268 config ARCH_VERSATILE
269 bool "ARM Ltd. Versatile family"
273 select HAVE_MACH_CLKDEV
275 select GENERIC_CLOCKEVENTS
276 select ARCH_WANT_OPTIONAL_GPIOLIB
277 select PLAT_VERSATILE
278 select PLAT_VERSATILE_CLCD
279 select PLAT_VERSATILE_FPGA_IRQ
280 select ARM_TIMER_SP804
282 This enables support for ARM Ltd Versatile board.
285 bool "ARM Ltd. Versatile Express family"
286 select ARCH_WANT_OPTIONAL_GPIOLIB
288 select ARM_TIMER_SP804
290 select HAVE_MACH_CLKDEV
291 select GENERIC_CLOCKEVENTS
293 select HAVE_PATA_PLATFORM
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
298 This enables support for the ARM Ltd Versatile Express boards.
302 select ARCH_REQUIRE_GPIOLIB
306 This enables support for systems based on the Atmel AT91RM9200,
307 AT91SAM9 and AT91CAP9 processors.
310 bool "Broadcom BCMRING"
314 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select ARCH_WANT_OPTIONAL_GPIOLIB
319 Support for Broadcom's BCMRing platform.
322 bool "Cirrus Logic CLPS711x/EP721x-based"
324 select ARCH_USES_GETTIMEOFFSET
326 Support for Cirrus Logic 711x/721x based boards.
329 bool "Cavium Networks CNS3XXX family"
331 select GENERIC_CLOCKEVENTS
333 select MIGHT_HAVE_PCI
334 select PCI_DOMAINS if PCI
336 Support for Cavium Networks CNS3XXX platform.
339 bool "Cortina Systems Gemini"
341 select ARCH_REQUIRE_GPIOLIB
342 select ARCH_USES_GETTIMEOFFSET
344 Support for the Cortina Systems Gemini family SoCs
347 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
351 select GENERIC_CLOCKEVENTS
353 select GENERIC_IRQ_CHIP
357 Support for CSR SiRFSoC ARM Cortex A9 Platform
364 select ARCH_USES_GETTIMEOFFSET
366 This is an evaluation board for the StrongARM processor available
367 from Digital. It has limited hardware on-board, including an
368 Ethernet interface, two PCMCIA sockets, two serial ports and a
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_HAS_HOLES_MEMORYMODEL
379 select ARCH_USES_GETTIMEOFFSET
381 This enables support for the Cirrus EP93xx series of CPUs.
383 config ARCH_FOOTBRIDGE
387 select GENERIC_CLOCKEVENTS
389 Support for systems based on the DC21285 companion chip
390 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
393 bool "Freescale MXC/iMX-based"
394 select GENERIC_CLOCKEVENTS
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_IRQ_CHIP
399 select HAVE_SCHED_CLOCK
401 Support for Freescale MXC/iMX-based family of processors
404 bool "Freescale MXS-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
410 Support for Freescale MXS-based family of processors
413 bool "Hilscher NetX based"
417 select GENERIC_CLOCKEVENTS
419 This enables support for systems based on the Hilscher NetX Soc
422 bool "Hynix HMS720x-based"
425 select ARCH_USES_GETTIMEOFFSET
427 This enables support for systems based on the Hynix HMS720x
435 select ARCH_SUPPORTS_MSI
438 Support for Intel's IOP13XX (XScale) family of processors.
446 select ARCH_REQUIRE_GPIOLIB
448 Support for Intel's 80219 and IOP32X (XScale) family of
457 select ARCH_REQUIRE_GPIOLIB
459 Support for Intel's IOP33X (XScale) family of processors.
466 select ARCH_USES_GETTIMEOFFSET
468 Support for Intel's IXP23xx (XScale) family of processors.
471 bool "IXP2400/2800-based"
475 select ARCH_USES_GETTIMEOFFSET
477 Support for Intel's IXP2400/2800 (XScale) family of processors.
485 select GENERIC_CLOCKEVENTS
486 select HAVE_SCHED_CLOCK
487 select MIGHT_HAVE_PCI
488 select DMABOUNCE if PCI
490 Support for Intel's IXP4XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Dove SoC 88AP510
503 bool "Marvell Kirkwood"
506 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
510 Support for the following Marvell Kirkwood series SoCs:
511 88F6180, 88F6192 and 88F6281.
517 select ARCH_REQUIRE_GPIOLIB
520 select USB_ARCH_HAS_OHCI
523 select GENERIC_CLOCKEVENTS
525 Support for the NXP LPC32XX family of processors
528 bool "Marvell MV78xx0"
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 Support for the following Marvell MV78xx0 series SoCs:
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
557 select HAVE_SCHED_CLOCK
562 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
565 bool "Micrel/Kendin KS8695"
567 select ARCH_REQUIRE_GPIOLIB
568 select ARCH_USES_GETTIMEOFFSET
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
576 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
590 bool "Nuvoton NUC93X CPU"
594 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
595 low-power and high performance MPEG-4/JPEG multimedia controller chip.
602 select GENERIC_CLOCKEVENTS
605 select HAVE_SCHED_CLOCK
606 select ARCH_HAS_CPUFREQ
608 This enables support for NVIDIA Tegra based systems (Tegra APX,
609 Tegra 6xx and Tegra 2 series).
612 bool "Philips Nexperia PNX4008 Mobile"
615 select ARCH_USES_GETTIMEOFFSET
617 This enables support for Philips PNX4008 mobile platform.
620 bool "PXA2xx/PXA3xx-based"
623 select ARCH_HAS_CPUFREQ
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
628 select HAVE_SCHED_CLOCK
633 select MULTI_IRQ_HANDLER
635 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
640 select GENERIC_CLOCKEVENTS
641 select ARCH_REQUIRE_GPIOLIB
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
651 bool "Renesas SH-Mobile / R-Mobile"
654 select HAVE_MACH_CLKDEV
655 select GENERIC_CLOCKEVENTS
658 select MULTI_IRQ_HANDLER
659 select PM_GENERIC_DOMAINS if PM
661 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
668 select ARCH_MAY_HAVE_PC_FDC
669 select HAVE_PATA_PLATFORM
672 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_USES_GETTIMEOFFSET
675 On the Acorn Risc-PC, Linux can support the internal IDE disk and
676 CD-ROM interface, serial and parallel port, and the floppy drive.
683 select ARCH_SPARSEMEM_ENABLE
685 select ARCH_HAS_CPUFREQ
687 select GENERIC_CLOCKEVENTS
689 select HAVE_SCHED_CLOCK
691 select ARCH_REQUIRE_GPIOLIB
693 Support for StrongARM 11x0 based boards.
696 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
698 select ARCH_HAS_CPUFREQ
701 select ARCH_USES_GETTIMEOFFSET
702 select HAVE_S3C2410_I2C if I2C
704 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
705 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
706 the Samsung SMDK2410 development board (and derivatives).
708 Note, the S3C2416 and the S3C2450 are so close that they even share
709 the same SoC ID code. This means that there is no separate machine
710 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
713 bool "Samsung S3C64XX"
720 select ARCH_USES_GETTIMEOFFSET
721 select ARCH_HAS_CPUFREQ
722 select ARCH_REQUIRE_GPIOLIB
723 select SAMSUNG_CLKSRC
724 select SAMSUNG_IRQ_VIC_TIMER
725 select SAMSUNG_IRQ_UART
726 select S3C_GPIO_TRACK
727 select S3C_GPIO_PULL_UPDOWN
728 select S3C_GPIO_CFG_S3C24XX
729 select S3C_GPIO_CFG_S3C64XX
731 select USB_ARCH_HAS_OHCI
732 select SAMSUNG_GPIOLIB_4BIT
733 select HAVE_S3C2410_I2C if I2C
734 select HAVE_S3C2410_WATCHDOG if WATCHDOG
736 Samsung S3C64XX series based systems
739 bool "Samsung S5P6440 S5P6450"
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 select GENERIC_CLOCKEVENTS
747 select HAVE_SCHED_CLOCK
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C_RTC if RTC_CLASS
751 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
755 bool "Samsung S5PC100"
760 select ARM_L1_CACHE_SHIFT_6
761 select ARCH_USES_GETTIMEOFFSET
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C_RTC if RTC_CLASS
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 Samsung S5PC100 series based systems
769 bool "Samsung S5PV210/S5PC110"
771 select ARCH_SPARSEMEM_ENABLE
772 select ARCH_HAS_HOLES_MEMORYMODEL
777 select ARM_L1_CACHE_SHIFT_6
778 select ARCH_HAS_CPUFREQ
779 select GENERIC_CLOCKEVENTS
780 select HAVE_SCHED_CLOCK
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C_RTC if RTC_CLASS
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 Samsung S5PV210/S5PC110 series based systems
788 bool "Samsung EXYNOS4"
790 select ARCH_SPARSEMEM_ENABLE
791 select ARCH_HAS_HOLES_MEMORYMODEL
795 select ARCH_HAS_CPUFREQ
796 select GENERIC_CLOCKEVENTS
797 select HAVE_S3C_RTC if RTC_CLASS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 Samsung EXYNOS4 series based systems
810 select ARCH_USES_GETTIMEOFFSET
812 Support for the StrongARM based Digital DNARD machine, also known
813 as "Shark" (<http://www.shark-linux.de/shark.html>).
816 bool "Telechips TCC ARM926-based systems"
821 select GENERIC_CLOCKEVENTS
823 Support for Telechips TCC ARM926-based systems.
826 bool "ST-Ericsson U300 Series"
830 select HAVE_SCHED_CLOCK
834 select GENERIC_CLOCKEVENTS
836 select HAVE_MACH_CLKDEV
838 select ARCH_REQUIRE_GPIOLIB
840 Support for ST-Ericsson U300 series mobile platforms.
843 bool "ST-Ericsson U8500 Series"
846 select GENERIC_CLOCKEVENTS
848 select ARCH_REQUIRE_GPIOLIB
849 select ARCH_HAS_CPUFREQ
851 Support for ST-Ericsson's Ux500 architecture
854 bool "STMicroelectronics Nomadik"
859 select GENERIC_CLOCKEVENTS
860 select ARCH_REQUIRE_GPIOLIB
862 Support for the Nomadik platform by ST-Ericsson
866 select GENERIC_CLOCKEVENTS
867 select ARCH_REQUIRE_GPIOLIB
871 select GENERIC_ALLOCATOR
872 select GENERIC_IRQ_CHIP
873 select ARCH_HAS_HOLES_MEMORYMODEL
875 Support for TI's DaVinci platform.
880 select ARCH_REQUIRE_GPIOLIB
881 select ARCH_HAS_CPUFREQ
883 select GENERIC_CLOCKEVENTS
884 select HAVE_SCHED_CLOCK
885 select ARCH_HAS_HOLES_MEMORYMODEL
887 Support for TI's OMAP platform (OMAP1/2/3/4).
892 select ARCH_REQUIRE_GPIOLIB
895 select GENERIC_CLOCKEVENTS
898 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
901 bool "VIA/WonderMedia 85xx"
904 select ARCH_HAS_CPUFREQ
905 select GENERIC_CLOCKEVENTS
906 select ARCH_REQUIRE_GPIOLIB
909 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
912 bool "Xilinx Zynq ARM Cortex A9 Platform"
915 select GENERIC_CLOCKEVENTS
922 Support for Xilinx Zynq ARM Cortex A9 Platform
926 # This is sorted alphabetically by mach-* pathname. However, plat-*
927 # Kconfigs may be included either alphabetically (according to the
928 # plat- suffix) or along side the corresponding mach-* source.
930 source "arch/arm/mach-at91/Kconfig"
932 source "arch/arm/mach-bcmring/Kconfig"
934 source "arch/arm/mach-clps711x/Kconfig"
936 source "arch/arm/mach-cns3xxx/Kconfig"
938 source "arch/arm/mach-davinci/Kconfig"
940 source "arch/arm/mach-dove/Kconfig"
942 source "arch/arm/mach-ep93xx/Kconfig"
944 source "arch/arm/mach-footbridge/Kconfig"
946 source "arch/arm/mach-gemini/Kconfig"
948 source "arch/arm/mach-h720x/Kconfig"
950 source "arch/arm/mach-integrator/Kconfig"
952 source "arch/arm/mach-iop32x/Kconfig"
954 source "arch/arm/mach-iop33x/Kconfig"
956 source "arch/arm/mach-iop13xx/Kconfig"
958 source "arch/arm/mach-ixp4xx/Kconfig"
960 source "arch/arm/mach-ixp2000/Kconfig"
962 source "arch/arm/mach-ixp23xx/Kconfig"
964 source "arch/arm/mach-kirkwood/Kconfig"
966 source "arch/arm/mach-ks8695/Kconfig"
968 source "arch/arm/mach-lpc32xx/Kconfig"
970 source "arch/arm/mach-msm/Kconfig"
972 source "arch/arm/mach-mv78xx0/Kconfig"
974 source "arch/arm/plat-mxc/Kconfig"
976 source "arch/arm/mach-mxs/Kconfig"
978 source "arch/arm/mach-netx/Kconfig"
980 source "arch/arm/mach-nomadik/Kconfig"
981 source "arch/arm/plat-nomadik/Kconfig"
983 source "arch/arm/mach-nuc93x/Kconfig"
985 source "arch/arm/plat-omap/Kconfig"
987 source "arch/arm/mach-omap1/Kconfig"
989 source "arch/arm/mach-omap2/Kconfig"
991 source "arch/arm/mach-orion5x/Kconfig"
993 source "arch/arm/mach-pxa/Kconfig"
994 source "arch/arm/plat-pxa/Kconfig"
996 source "arch/arm/mach-mmp/Kconfig"
998 source "arch/arm/mach-realview/Kconfig"
1000 source "arch/arm/mach-sa1100/Kconfig"
1002 source "arch/arm/plat-samsung/Kconfig"
1003 source "arch/arm/plat-s3c24xx/Kconfig"
1004 source "arch/arm/plat-s5p/Kconfig"
1006 source "arch/arm/plat-spear/Kconfig"
1008 source "arch/arm/plat-tcc/Kconfig"
1011 source "arch/arm/mach-s3c2410/Kconfig"
1012 source "arch/arm/mach-s3c2412/Kconfig"
1013 source "arch/arm/mach-s3c2416/Kconfig"
1014 source "arch/arm/mach-s3c2440/Kconfig"
1015 source "arch/arm/mach-s3c2443/Kconfig"
1019 source "arch/arm/mach-s3c64xx/Kconfig"
1022 source "arch/arm/mach-s5p64x0/Kconfig"
1024 source "arch/arm/mach-s5pc100/Kconfig"
1026 source "arch/arm/mach-s5pv210/Kconfig"
1028 source "arch/arm/mach-exynos4/Kconfig"
1030 source "arch/arm/mach-shmobile/Kconfig"
1032 source "arch/arm/mach-tegra/Kconfig"
1034 source "arch/arm/mach-u300/Kconfig"
1036 source "arch/arm/mach-ux500/Kconfig"
1038 source "arch/arm/mach-versatile/Kconfig"
1040 source "arch/arm/mach-vexpress/Kconfig"
1041 source "arch/arm/plat-versatile/Kconfig"
1043 source "arch/arm/mach-vt8500/Kconfig"
1045 source "arch/arm/mach-w90x900/Kconfig"
1047 # Definitions to make life easier
1053 select GENERIC_CLOCKEVENTS
1054 select HAVE_SCHED_CLOCK
1059 select GENERIC_IRQ_CHIP
1060 select HAVE_SCHED_CLOCK
1065 config PLAT_VERSATILE
1068 config ARM_TIMER_SP804
1072 source arch/arm/mm/Kconfig
1075 bool "Enable iWMMXt support"
1076 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1077 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1079 Enable support for iWMMXt context switching at run time if
1080 running on a CPU that supports it.
1082 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1085 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1089 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1090 (!ARCH_OMAP3 || OMAP3_EMU)
1094 config MULTI_IRQ_HANDLER
1097 Allow each machine to specify it's own IRQ handler at run time.
1100 source "arch/arm/Kconfig-nommu"
1103 config ARM_ERRATA_411920
1104 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1105 depends on CPU_V6 || CPU_V6K
1107 Invalidation of the Instruction Cache operation can
1108 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1109 It does not affect the MPCore. This option enables the ARM Ltd.
1110 recommended workaround.
1112 config ARM_ERRATA_430973
1113 bool "ARM errata: Stale prediction on replaced interworking branch"
1116 This option enables the workaround for the 430973 Cortex-A8
1117 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1118 interworking branch is replaced with another code sequence at the
1119 same virtual address, whether due to self-modifying code or virtual
1120 to physical address re-mapping, Cortex-A8 does not recover from the
1121 stale interworking branch prediction. This results in Cortex-A8
1122 executing the new code sequence in the incorrect ARM or Thumb state.
1123 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1124 and also flushes the branch target cache at every context switch.
1125 Note that setting specific bits in the ACTLR register may not be
1126 available in non-secure mode.
1128 config ARM_ERRATA_458693
1129 bool "ARM errata: Processor deadlock when a false hazard is created"
1132 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1133 erratum. For very specific sequences of memory operations, it is
1134 possible for a hazard condition intended for a cache line to instead
1135 be incorrectly associated with a different cache line. This false
1136 hazard might then cause a processor deadlock. The workaround enables
1137 the L1 caching of the NEON accesses and disables the PLD instruction
1138 in the ACTLR register. Note that setting specific bits in the ACTLR
1139 register may not be available in non-secure mode.
1141 config ARM_ERRATA_460075
1142 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1145 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1146 erratum. Any asynchronous access to the L2 cache may encounter a
1147 situation in which recent store transactions to the L2 cache are lost
1148 and overwritten with stale memory contents from external memory. The
1149 workaround disables the write-allocate mode for the L2 cache via the
1150 ACTLR register. Note that setting specific bits in the ACTLR register
1151 may not be available in non-secure mode.
1153 config ARM_ERRATA_742230
1154 bool "ARM errata: DMB operation may be faulty"
1155 depends on CPU_V7 && SMP
1157 This option enables the workaround for the 742230 Cortex-A9
1158 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1159 between two write operations may not ensure the correct visibility
1160 ordering of the two writes. This workaround sets a specific bit in
1161 the diagnostic register of the Cortex-A9 which causes the DMB
1162 instruction to behave as a DSB, ensuring the correct behaviour of
1165 config ARM_ERRATA_742231
1166 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1167 depends on CPU_V7 && SMP
1169 This option enables the workaround for the 742231 Cortex-A9
1170 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1171 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1172 accessing some data located in the same cache line, may get corrupted
1173 data due to bad handling of the address hazard when the line gets
1174 replaced from one of the CPUs at the same time as another CPU is
1175 accessing it. This workaround sets specific bits in the diagnostic
1176 register of the Cortex-A9 which reduces the linefill issuing
1177 capabilities of the processor.
1179 config PL310_ERRATA_588369
1180 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1181 depends on CACHE_L2X0
1183 The PL310 L2 cache controller implements three types of Clean &
1184 Invalidate maintenance operations: by Physical Address
1185 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1186 They are architecturally defined to behave as the execution of a
1187 clean operation followed immediately by an invalidate operation,
1188 both performing to the same memory location. This functionality
1189 is not correctly implemented in PL310 as clean lines are not
1190 invalidated as a result of these operations.
1192 config ARM_ERRATA_720789
1193 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for the 720789 Cortex-A9 (prior to
1197 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1198 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1199 As a consequence of this erratum, some TLB entries which should be
1200 invalidated are not, resulting in an incoherency in the system page
1201 tables. The workaround changes the TLB flushing routines to invalidate
1202 entries regardless of the ASID.
1204 config PL310_ERRATA_727915
1205 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1206 depends on CACHE_L2X0
1208 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1209 operation (offset 0x7FC). This operation runs in background so that
1210 PL310 can handle normal accesses while it is in progress. Under very
1211 rare circumstances, due to this erratum, write data can be lost when
1212 PL310 treats a cacheable write transaction during a Clean &
1213 Invalidate by Way operation.
1215 config ARM_ERRATA_743622
1216 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1219 This option enables the workaround for the 743622 Cortex-A9
1220 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1221 optimisation in the Cortex-A9 Store Buffer may lead to data
1222 corruption. This workaround sets a specific bit in the diagnostic
1223 register of the Cortex-A9 which disables the Store Buffer
1224 optimisation, preventing the defect from occurring. This has no
1225 visible impact on the overall performance or power consumption of the
1228 config ARM_ERRATA_751472
1229 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 751472 Cortex-A9 (prior
1233 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1234 completion of a following broadcasted operation if the second
1235 operation is received by a CPU before the ICIALLUIS has completed,
1236 potentially leading to corrupted entries in the cache or TLB.
1238 config ARM_ERRATA_753970
1239 bool "ARM errata: cache sync operation may be faulty"
1240 depends on CACHE_PL310
1242 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1244 Under some condition the effect of cache sync operation on
1245 the store buffer still remains when the operation completes.
1246 This means that the store buffer is always asked to drain and
1247 this prevents it from merging any further writes. The workaround
1248 is to replace the normal offset of cache sync operation (0x730)
1249 by another offset targeting an unmapped PL310 register 0x740.
1250 This has the same effect as the cache sync operation: store buffer
1251 drain and waiting for all buffers empty.
1253 config ARM_ERRATA_754322
1254 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1257 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1258 r3p*) erratum. A speculative memory access may cause a page table walk
1259 which starts prior to an ASID switch but completes afterwards. This
1260 can populate the micro-TLB with a stale entry which may be hit with
1261 the new ASID. This workaround places two dsb instructions in the mm
1262 switching code so that no page table walks can cross the ASID switch.
1264 config ARM_ERRATA_754327
1265 bool "ARM errata: no automatic Store Buffer drain"
1266 depends on CPU_V7 && SMP
1268 This option enables the workaround for the 754327 Cortex-A9 (prior to
1269 r2p0) erratum. The Store Buffer does not have any automatic draining
1270 mechanism and therefore a livelock may occur if an external agent
1271 continuously polls a memory location waiting to observe an update.
1272 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1273 written polling loops from denying visibility of updates to memory.
1275 config ARM_ERRATA_364296
1276 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1277 depends on CPU_V6 && !SMP
1279 This options enables the workaround for the 364296 ARM1136
1280 r0p2 erratum (possible cache data corruption with
1281 hit-under-miss enabled). It sets the undocumented bit 31 in
1282 the auxiliary control register and the FI bit in the control
1283 register, thus disabling hit-under-miss without putting the
1284 processor into full low interrupt latency mode. ARM11MPCore
1289 source "arch/arm/common/Kconfig"
1299 Find out whether you have ISA slots on your motherboard. ISA is the
1300 name of a bus system, i.e. the way the CPU talks to the other stuff
1301 inside your box. Other bus systems are PCI, EISA, MicroChannel
1302 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1303 newer boards don't support it. If you have ISA, say Y, otherwise N.
1305 # Select ISA DMA controller support
1310 # Select ISA DMA interface
1315 bool "PCI support" if MIGHT_HAVE_PCI
1317 Find out whether you have a PCI motherboard. PCI is the name of a
1318 bus system, i.e. the way the CPU talks to the other stuff inside
1319 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1320 VESA. If you have PCI, say Y, otherwise N.
1326 config PCI_NANOENGINE
1327 bool "BSE nanoEngine PCI support"
1328 depends on SA1100_NANOENGINE
1330 Enable PCI on the BSE nanoEngine board.
1335 # Select the host bridge type
1336 config PCI_HOST_VIA82C505
1338 depends on PCI && ARCH_SHARK
1341 config PCI_HOST_ITE8152
1343 depends on PCI && MACH_ARMCORE
1347 source "drivers/pci/Kconfig"
1349 source "drivers/pcmcia/Kconfig"
1353 menu "Kernel Features"
1355 source "kernel/time/Kconfig"
1358 bool "Symmetric Multi-Processing"
1359 depends on CPU_V6K || CPU_V7
1360 depends on GENERIC_CLOCKEVENTS
1361 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1362 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1363 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1364 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1365 select USE_GENERIC_SMP_HELPERS
1366 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1368 This enables support for systems with more than one CPU. If you have
1369 a system with only one CPU, like most personal computers, say N. If
1370 you have a system with more than one CPU, say Y.
1372 If you say N here, the kernel will run on single and multiprocessor
1373 machines, but will use only one CPU of a multiprocessor machine. If
1374 you say Y here, the kernel will run on many, but not all, single
1375 processor machines. On a single processor machine, the kernel will
1376 run faster if you say N here.
1378 See also <file:Documentation/i386/IO-APIC.txt>,
1379 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1380 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1382 If you don't know what to do here, say N.
1385 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1386 depends on EXPERIMENTAL
1387 depends on SMP && !XIP_KERNEL
1390 SMP kernels contain instructions which fail on non-SMP processors.
1391 Enabling this option allows the kernel to modify itself to make
1392 these instructions safe. Disabling it allows about 1K of space
1395 If you don't know what to do here, say Y.
1397 config ARM_CPU_TOPOLOGY
1398 bool "Support cpu topology definition"
1399 depends on SMP && CPU_V7
1402 Support ARM cpu topology definition. The MPIDR register defines
1403 affinity between processors which is then used to describe the cpu
1404 topology of an ARM System.
1407 bool "Multi-core scheduler support"
1408 depends on ARM_CPU_TOPOLOGY
1410 Multi-core scheduler support improves the CPU scheduler's decision
1411 making when dealing with multi-core CPU chips at a cost of slightly
1412 increased overhead in some places. If unsure say N here.
1415 bool "SMT scheduler support"
1416 depends on ARM_CPU_TOPOLOGY
1418 Improves the CPU scheduler's decision making when dealing with
1419 MultiThreading at a cost of slightly increased overhead in some
1420 places. If unsure say N here.
1425 This option enables support for the ARM system coherency unit
1432 This options enables support for the ARM timer and watchdog unit
1435 prompt "Memory split"
1438 Select the desired split between kernel and user memory.
1440 If you are not absolutely sure what you are doing, leave this
1444 bool "3G/1G user/kernel split"
1446 bool "2G/2G user/kernel split"
1448 bool "1G/3G user/kernel split"
1453 default 0x40000000 if VMSPLIT_1G
1454 default 0x80000000 if VMSPLIT_2G
1458 int "Maximum number of CPUs (2-32)"
1464 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1465 depends on SMP && HOTPLUG && EXPERIMENTAL
1467 Say Y here to experiment with turning CPUs off and on. CPUs
1468 can be controlled through /sys/devices/system/cpu.
1471 bool "Use local timer interrupts"
1474 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1476 Enable support for local timers on SMP platforms, rather then the
1477 legacy IPI broadcast method. Local timers allows the system
1478 accounting to be spread across the timer interval, preventing a
1479 "thundering herd" at every timer tick.
1481 source kernel/Kconfig.preempt
1485 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1486 ARCH_S5PV210 || ARCH_EXYNOS4
1487 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1488 default AT91_TIMER_HZ if ARCH_AT91
1489 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1492 config THUMB2_KERNEL
1493 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1494 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1496 select ARM_ASM_UNIFIED
1498 By enabling this option, the kernel will be compiled in
1499 Thumb-2 mode. A compiler/assembler that understand the unified
1500 ARM-Thumb syntax is needed.
1504 config THUMB2_AVOID_R_ARM_THM_JUMP11
1505 bool "Work around buggy Thumb-2 short branch relocations in gas"
1506 depends on THUMB2_KERNEL && MODULES
1509 Various binutils versions can resolve Thumb-2 branches to
1510 locally-defined, preemptible global symbols as short-range "b.n"
1511 branch instructions.
1513 This is a problem, because there's no guarantee the final
1514 destination of the symbol, or any candidate locations for a
1515 trampoline, are within range of the branch. For this reason, the
1516 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1517 relocation in modules at all, and it makes little sense to add
1520 The symptom is that the kernel fails with an "unsupported
1521 relocation" error when loading some modules.
1523 Until fixed tools are available, passing
1524 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1525 code which hits this problem, at the cost of a bit of extra runtime
1526 stack usage in some cases.
1528 The problem is described in more detail at:
1529 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1531 Only Thumb-2 kernels are affected.
1533 Unless you are sure your tools don't have this problem, say Y.
1535 config ARM_ASM_UNIFIED
1539 bool "Use the ARM EABI to compile the kernel"
1541 This option allows for the kernel to be compiled using the latest
1542 ARM ABI (aka EABI). This is only useful if you are using a user
1543 space environment that is also compiled with EABI.
1545 Since there are major incompatibilities between the legacy ABI and
1546 EABI, especially with regard to structure member alignment, this
1547 option also changes the kernel syscall calling convention to
1548 disambiguate both ABIs and allow for backward compatibility support
1549 (selected with CONFIG_OABI_COMPAT).
1551 To use this you need GCC version 4.0.0 or later.
1554 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1555 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1558 This option preserves the old syscall interface along with the
1559 new (ARM EABI) one. It also provides a compatibility layer to
1560 intercept syscalls that have structure arguments which layout
1561 in memory differs between the legacy ABI and the new ARM EABI
1562 (only for non "thumb" binaries). This option adds a tiny
1563 overhead to all syscalls and produces a slightly larger kernel.
1564 If you know you'll be using only pure EABI user space then you
1565 can say N here. If this option is not selected and you attempt
1566 to execute a legacy ABI binary then the result will be
1567 UNPREDICTABLE (in fact it can be predicted that it won't work
1568 at all). If in doubt say Y.
1570 config ARCH_HAS_HOLES_MEMORYMODEL
1573 config ARCH_SPARSEMEM_ENABLE
1576 config ARCH_SPARSEMEM_DEFAULT
1577 def_bool ARCH_SPARSEMEM_ENABLE
1579 config ARCH_SELECT_MEMORY_MODEL
1580 def_bool ARCH_SPARSEMEM_ENABLE
1582 config HAVE_ARCH_PFN_VALID
1583 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1586 bool "High Memory Support"
1589 The address space of ARM processors is only 4 Gigabytes large
1590 and it has to accommodate user address space, kernel address
1591 space as well as some memory mapped IO. That means that, if you
1592 have a large amount of physical memory and/or IO, not all of the
1593 memory can be "permanently mapped" by the kernel. The physical
1594 memory that is not permanently mapped is called "high memory".
1596 Depending on the selected kernel/user memory split, minimum
1597 vmalloc space and actual amount of RAM, you may not need this
1598 option which should result in a slightly faster kernel.
1603 bool "Allocate 2nd-level pagetables from highmem"
1606 config HW_PERF_EVENTS
1607 bool "Enable hardware performance counter support for perf events"
1608 depends on PERF_EVENTS && CPU_HAS_PMU
1611 Enable hardware performance counter support for perf events. If
1612 disabled, perf events will use software events only.
1616 config FORCE_MAX_ZONEORDER
1617 int "Maximum zone order" if ARCH_SHMOBILE
1618 range 11 64 if ARCH_SHMOBILE
1619 default "9" if SA1111
1622 The kernel memory allocator divides physically contiguous memory
1623 blocks into "zones", where each zone is a power of two number of
1624 pages. This option selects the largest power of two that the kernel
1625 keeps in the memory allocator. If you need to allocate very large
1626 blocks of physically contiguous memory, then you may need to
1627 increase this value.
1629 This config option is actually maximum order plus one. For example,
1630 a value of 11 means that the largest free memory block is 2^10 pages.
1633 bool "Timer and CPU usage LEDs"
1634 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1635 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1636 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1637 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1638 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1639 ARCH_AT91 || ARCH_DAVINCI || \
1640 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1642 If you say Y here, the LEDs on your machine will be used
1643 to provide useful information about your current system status.
1645 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1646 be able to select which LEDs are active using the options below. If
1647 you are compiling a kernel for the EBSA-110 or the LART however, the
1648 red LED will simply flash regularly to indicate that the system is
1649 still functional. It is safe to say Y here if you have a CATS
1650 system, but the driver will do nothing.
1653 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1654 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1655 || MACH_OMAP_PERSEUS2
1657 depends on !GENERIC_CLOCKEVENTS
1658 default y if ARCH_EBSA110
1660 If you say Y here, one of the system LEDs (the green one on the
1661 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1662 will flash regularly to indicate that the system is still
1663 operational. This is mainly useful to kernel hackers who are
1664 debugging unstable kernels.
1666 The LART uses the same LED for both Timer LED and CPU usage LED
1667 functions. You may choose to use both, but the Timer LED function
1668 will overrule the CPU usage LED.
1671 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1673 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1674 || MACH_OMAP_PERSEUS2
1677 If you say Y here, the red LED will be used to give a good real
1678 time indication of CPU usage, by lighting whenever the idle task
1679 is not currently executing.
1681 The LART uses the same LED for both Timer LED and CPU usage LED
1682 functions. You may choose to use both, but the Timer LED function
1683 will overrule the CPU usage LED.
1685 config ALIGNMENT_TRAP
1687 depends on CPU_CP15_MMU
1688 default y if !ARCH_EBSA110
1689 select HAVE_PROC_CPU if PROC_FS
1691 ARM processors cannot fetch/store information which is not
1692 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1693 address divisible by 4. On 32-bit ARM processors, these non-aligned
1694 fetch/store instructions will be emulated in software if you say
1695 here, which has a severe performance impact. This is necessary for
1696 correct operation of some network protocols. With an IP-only
1697 configuration it is safe to say N, otherwise say Y.
1699 config UACCESS_WITH_MEMCPY
1700 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1701 depends on MMU && EXPERIMENTAL
1702 default y if CPU_FEROCEON
1704 Implement faster copy_to_user and clear_user methods for CPU
1705 cores where a 8-word STM instruction give significantly higher
1706 memory write throughput than a sequence of individual 32bit stores.
1708 A possible side effect is a slight increase in scheduling latency
1709 between threads sharing the same address space if they invoke
1710 such copy operations with large buffers.
1712 However, if the CPU data cache is using a write-allocate mode,
1713 this option is unlikely to provide any performance gain.
1717 prompt "Enable seccomp to safely compute untrusted bytecode"
1719 This kernel feature is useful for number crunching applications
1720 that may need to compute untrusted bytecode during their
1721 execution. By using pipes or other transports made available to
1722 the process as file descriptors supporting the read/write
1723 syscalls, it's possible to isolate those applications in
1724 their own address space using seccomp. Once seccomp is
1725 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1726 and the task is only allowed to execute a few safe syscalls
1727 defined by each seccomp mode.
1729 config CC_STACKPROTECTOR
1730 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1731 depends on EXPERIMENTAL
1733 This option turns on the -fstack-protector GCC feature. This
1734 feature puts, at the beginning of functions, a canary value on
1735 the stack just before the return address, and validates
1736 the value just before actually returning. Stack based buffer
1737 overflows (that need to overwrite this return address) now also
1738 overwrite the canary, which gets detected and the attack is then
1739 neutralized via a kernel panic.
1740 This feature requires gcc version 4.2 or above.
1742 config DEPRECATED_PARAM_STRUCT
1743 bool "Provide old way to pass kernel parameters"
1745 This was deprecated in 2001 and announced to live on for 5 years.
1746 Some old boot loaders still use this way.
1753 bool "Flattened Device Tree support"
1755 select OF_EARLY_FLATTREE
1758 Include support for flattened device tree machine descriptions.
1760 # Compressed boot loader in ROM. Yes, we really want to ask about
1761 # TEXT and BSS so we preserve their values in the config files.
1762 config ZBOOT_ROM_TEXT
1763 hex "Compressed ROM boot loader base address"
1766 The physical address at which the ROM-able zImage is to be
1767 placed in the target. Platforms which normally make use of
1768 ROM-able zImage formats normally set this to a suitable
1769 value in their defconfig file.
1771 If ZBOOT_ROM is not enabled, this has no effect.
1773 config ZBOOT_ROM_BSS
1774 hex "Compressed ROM boot loader BSS address"
1777 The base address of an area of read/write memory in the target
1778 for the ROM-able zImage which must be available while the
1779 decompressor is running. It must be large enough to hold the
1780 entire decompressed kernel plus an additional 128 KiB.
1781 Platforms which normally make use of ROM-able zImage formats
1782 normally set this to a suitable value in their defconfig file.
1784 If ZBOOT_ROM is not enabled, this has no effect.
1787 bool "Compressed boot loader in ROM/flash"
1788 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1790 Say Y here if you intend to execute your compressed kernel image
1791 (zImage) directly from ROM or flash. If unsure, say N.
1794 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1795 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1796 default ZBOOT_ROM_NONE
1798 Include experimental SD/MMC loading code in the ROM-able zImage.
1799 With this enabled it is possible to write the the ROM-able zImage
1800 kernel image to an MMC or SD card and boot the kernel straight
1801 from the reset vector. At reset the processor Mask ROM will load
1802 the first part of the the ROM-able zImage which in turn loads the
1803 rest the kernel image to RAM.
1805 config ZBOOT_ROM_NONE
1806 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1808 Do not load image from SD or MMC
1810 config ZBOOT_ROM_MMCIF
1811 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1813 Load image from MMCIF hardware block.
1815 config ZBOOT_ROM_SH_MOBILE_SDHI
1816 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1818 Load image from SDHI hardware block
1822 config ARM_APPENDED_DTB
1823 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1824 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1826 With this option, the boot code will look for a device tree binary
1827 (DTB) appended to zImage
1828 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1830 This is meant as a backward compatibility convenience for those
1831 systems with a bootloader that can't be upgraded to accommodate
1832 the documented boot protocol using a device tree.
1834 Beware that there is very little in terms of protection against
1835 this option being confused by leftover garbage in memory that might
1836 look like a DTB header after a reboot if no actual DTB is appended
1837 to zImage. Do not leave this option active in a production kernel
1838 if you don't intend to always append a DTB. Proper passing of the
1839 location into r2 of a bootloader provided DTB is always preferable
1842 config ARM_ATAG_DTB_COMPAT
1843 bool "Supplement the appended DTB with traditional ATAG information"
1844 depends on ARM_APPENDED_DTB
1846 Some old bootloaders can't be updated to a DTB capable one, yet
1847 they provide ATAGs with memory configuration, the ramdisk address,
1848 the kernel cmdline string, etc. Such information is dynamically
1849 provided by the bootloader and can't always be stored in a static
1850 DTB. To allow a device tree enabled kernel to be used with such
1851 bootloaders, this option allows zImage to extract the information
1852 from the ATAG list and store it at run time into the appended DTB.
1855 string "Default kernel command string"
1858 On some architectures (EBSA110 and CATS), there is currently no way
1859 for the boot loader to pass arguments to the kernel. For these
1860 architectures, you should supply some command-line options at build
1861 time by entering them here. As a minimum, you should specify the
1862 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1865 prompt "Kernel command line type" if CMDLINE != ""
1866 default CMDLINE_FROM_BOOTLOADER
1868 config CMDLINE_FROM_BOOTLOADER
1869 bool "Use bootloader kernel arguments if available"
1871 Uses the command-line options passed by the boot loader. If
1872 the boot loader doesn't provide any, the default kernel command
1873 string provided in CMDLINE will be used.
1875 config CMDLINE_EXTEND
1876 bool "Extend bootloader kernel arguments"
1878 The command-line arguments provided by the boot loader will be
1879 appended to the default kernel command string.
1881 config CMDLINE_FORCE
1882 bool "Always use the default kernel command string"
1884 Always use the default kernel command string, even if the boot
1885 loader passes other arguments to the kernel.
1886 This is useful if you cannot or don't want to change the
1887 command-line options your boot loader passes to the kernel.
1891 bool "Kernel Execute-In-Place from ROM"
1892 depends on !ZBOOT_ROM
1894 Execute-In-Place allows the kernel to run from non-volatile storage
1895 directly addressable by the CPU, such as NOR flash. This saves RAM
1896 space since the text section of the kernel is not loaded from flash
1897 to RAM. Read-write sections, such as the data section and stack,
1898 are still copied to RAM. The XIP kernel is not compressed since
1899 it has to run directly from flash, so it will take more space to
1900 store it. The flash address used to link the kernel object files,
1901 and for storing it, is configuration dependent. Therefore, if you
1902 say Y here, you must know the proper physical address where to
1903 store the kernel image depending on your own flash memory usage.
1905 Also note that the make target becomes "make xipImage" rather than
1906 "make zImage" or "make Image". The final kernel binary to put in
1907 ROM memory will be arch/arm/boot/xipImage.
1911 config XIP_PHYS_ADDR
1912 hex "XIP Kernel Physical Location"
1913 depends on XIP_KERNEL
1914 default "0x00080000"
1916 This is the physical address in your flash memory the kernel will
1917 be linked for and stored to. This address is dependent on your
1921 bool "Kexec system call (EXPERIMENTAL)"
1922 depends on EXPERIMENTAL
1924 kexec is a system call that implements the ability to shutdown your
1925 current kernel, and to start another kernel. It is like a reboot
1926 but it is independent of the system firmware. And like a reboot
1927 you can start any kernel with it, not just Linux.
1929 It is an ongoing process to be certain the hardware in a machine
1930 is properly shutdown, so do not be surprised if this code does not
1931 initially work for you. It may help to enable device hotplugging
1935 bool "Export atags in procfs"
1939 Should the atags used to boot the kernel be exported in an "atags"
1940 file in procfs. Useful with kexec.
1943 bool "Build kdump crash kernel (EXPERIMENTAL)"
1944 depends on EXPERIMENTAL
1946 Generate crash dump after being started by kexec. This should
1947 be normally only set in special crash dump kernels which are
1948 loaded in the main kernel with kexec-tools into a specially
1949 reserved region and then later executed after a crash by
1950 kdump/kexec. The crash dump kernel must be compiled to a
1951 memory address not used by the main kernel
1953 For more details see Documentation/kdump/kdump.txt
1955 config AUTO_ZRELADDR
1956 bool "Auto calculation of the decompressed kernel image address"
1957 depends on !ZBOOT_ROM && !ARCH_U300
1959 ZRELADDR is the physical address where the decompressed kernel
1960 image will be placed. If AUTO_ZRELADDR is selected, the address
1961 will be determined at run-time by masking the current IP with
1962 0xf8000000. This assumes the zImage being placed in the first 128MB
1963 from start of memory.
1967 menu "CPU Power Management"
1971 source "drivers/cpufreq/Kconfig"
1974 tristate "CPUfreq driver for i.MX CPUs"
1975 depends on ARCH_MXC && CPU_FREQ
1977 This enables the CPUfreq driver for i.MX CPUs.
1979 config CPU_FREQ_SA1100
1982 config CPU_FREQ_SA1110
1985 config CPU_FREQ_INTEGRATOR
1986 tristate "CPUfreq driver for ARM Integrator CPUs"
1987 depends on ARCH_INTEGRATOR && CPU_FREQ
1990 This enables the CPUfreq driver for ARM Integrator CPUs.
1992 For details, take a look at <file:Documentation/cpu-freq>.
1998 depends on CPU_FREQ && ARCH_PXA && PXA25x
2000 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2005 Internal configuration node for common cpufreq on Samsung SoC
2007 config CPU_FREQ_S3C24XX
2008 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2009 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2012 This enables the CPUfreq driver for the Samsung S3C24XX family
2015 For details, take a look at <file:Documentation/cpu-freq>.
2019 config CPU_FREQ_S3C24XX_PLL
2020 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2021 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2023 Compile in support for changing the PLL frequency from the
2024 S3C24XX series CPUfreq driver. The PLL takes time to settle
2025 after a frequency change, so by default it is not enabled.
2027 This also means that the PLL tables for the selected CPU(s) will
2028 be built which may increase the size of the kernel image.
2030 config CPU_FREQ_S3C24XX_DEBUG
2031 bool "Debug CPUfreq Samsung driver core"
2032 depends on CPU_FREQ_S3C24XX
2034 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2036 config CPU_FREQ_S3C24XX_IODEBUG
2037 bool "Debug CPUfreq Samsung driver IO timing"
2038 depends on CPU_FREQ_S3C24XX
2040 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2042 config CPU_FREQ_S3C24XX_DEBUGFS
2043 bool "Export debugfs for CPUFreq"
2044 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2046 Export status information via debugfs.
2050 source "drivers/cpuidle/Kconfig"
2054 menu "Floating point emulation"
2056 comment "At least one emulation must be selected"
2059 bool "NWFPE math emulation"
2060 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2062 Say Y to include the NWFPE floating point emulator in the kernel.
2063 This is necessary to run most binaries. Linux does not currently
2064 support floating point hardware so you need to say Y here even if
2065 your machine has an FPA or floating point co-processor podule.
2067 You may say N here if you are going to load the Acorn FPEmulator
2068 early in the bootup.
2071 bool "Support extended precision"
2072 depends on FPE_NWFPE
2074 Say Y to include 80-bit support in the kernel floating-point
2075 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2076 Note that gcc does not generate 80-bit operations by default,
2077 so in most cases this option only enlarges the size of the
2078 floating point emulator without any good reason.
2080 You almost surely want to say N here.
2083 bool "FastFPE math emulation (EXPERIMENTAL)"
2084 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2086 Say Y here to include the FAST floating point emulator in the kernel.
2087 This is an experimental much faster emulator which now also has full
2088 precision for the mantissa. It does not support any exceptions.
2089 It is very simple, and approximately 3-6 times faster than NWFPE.
2091 It should be sufficient for most programs. It may be not suitable
2092 for scientific calculations, but you have to check this for yourself.
2093 If you do not feel you need a faster FP emulation you should better
2097 bool "VFP-format floating point maths"
2098 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2100 Say Y to include VFP support code in the kernel. This is needed
2101 if your hardware includes a VFP unit.
2103 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2104 release notes and additional status information.
2106 Say N if your target does not have VFP hardware.
2114 bool "Advanced SIMD (NEON) Extension support"
2115 depends on VFPv3 && CPU_V7
2117 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2122 menu "Userspace binary formats"
2124 source "fs/Kconfig.binfmt"
2127 tristate "RISC OS personality"
2130 Say Y here to include the kernel code necessary if you want to run
2131 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2132 experimental; if this sounds frightening, say N and sleep in peace.
2133 You can also say M here to compile this support as a module (which
2134 will be called arthur).
2138 menu "Power management options"
2140 source "kernel/power/Kconfig"
2142 config ARCH_SUSPEND_POSSIBLE
2143 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2144 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2145 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2150 source "net/Kconfig"
2152 source "drivers/Kconfig"
2156 source "arch/arm/Kconfig.debug"
2158 source "security/Kconfig"
2160 source "crypto/Kconfig"
2162 source "lib/Kconfig"