4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_GENERIC_SPINLOCK
172 config RWSEM_XCHGADD_ALGORITHM
175 config ARCH_HAS_ILOG2_U32
178 config ARCH_HAS_ILOG2_U64
181 config ARCH_HAS_CPUFREQ
184 Internal node to signify that the ARCH has CPUFREQ support
185 and that the relevant menu configurations are displayed for
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_SUPPORTS_UPROBES
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_GPIO_H
255 Select this when mach/gpio.h is required to provide special
256 definitions for this platform. The need for mach/gpio.h should
257 be avoided when possible.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276 default DRAM_BASE if !MMU
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 source "init/Kconfig"
287 source "kernel/Kconfig.freezer"
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARCH_VERSATILE if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_HAS_SG_CHAIN
312 select ARM_PATCH_PHYS_VIRT
316 select GENERIC_CLOCKEVENTS
317 select MULTI_IRQ_HANDLER
321 config ARCH_INTEGRATOR
322 bool "ARM Ltd. Integrator family"
323 select ARCH_HAS_CPUFREQ
325 select ARM_PATCH_PHYS_VIRT
328 select COMMON_CLK_VERSATILE
329 select GENERIC_CLOCKEVENTS
332 select MULTI_IRQ_HANDLER
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
337 select VERSATILE_FPGA_IRQ
339 Support for ARM's Integrator platform.
342 bool "ARM Ltd. RealView family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
347 select COMMON_CLK_VERSATILE
348 select GENERIC_CLOCKEVENTS
349 select GPIO_PL061 if GPIOLIB
351 select NEED_MACH_MEMORY_H
352 select PLAT_VERSATILE
353 select PLAT_VERSATILE_CLCD
355 This enables support for ARM Ltd RealView boards.
357 config ARCH_VERSATILE
358 bool "ARM Ltd. Versatile family"
359 select ARCH_WANT_OPTIONAL_GPIOLIB
361 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select HAVE_MACH_CLKDEV
367 select PLAT_VERSATILE
368 select PLAT_VERSATILE_CLCD
369 select PLAT_VERSATILE_CLOCK
370 select VERSATILE_FPGA_IRQ
372 This enables support for ARM Ltd Versatile board.
376 select ARCH_REQUIRE_GPIOLIB
379 select NEED_MACH_IO_H if PCCARD
381 select PINCTRL_AT91 if USE_OF
383 This enables support for systems based on Atmel
384 AT91RM9200 and AT91SAM9* processors.
387 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
388 select ARCH_REQUIRE_GPIOLIB
393 select GENERIC_CLOCKEVENTS
396 Support for Cirrus Logic 711x/721x/731x based boards.
399 bool "Cortina Systems Gemini"
400 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
405 Support for the Cortina Systems Gemini family SoCs
409 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 bool "Energy Micro efm32"
424 select ARCH_REQUIRE_GPIOLIB
430 select GENERIC_CLOCKEVENTS
436 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
441 select ARCH_HAS_HOLES_MEMORYMODEL
442 select ARCH_REQUIRE_GPIOLIB
443 select ARCH_USES_GETTIMEOFFSET
448 select NEED_MACH_MEMORY_H
450 This enables support for the Cirrus EP93xx series of CPUs.
452 config ARCH_FOOTBRIDGE
456 select GENERIC_CLOCKEVENTS
458 select NEED_MACH_IO_H if !MMU
459 select NEED_MACH_MEMORY_H
461 Support for systems based on the DC21285 companion chip
462 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
465 bool "Hilscher NetX based"
469 select GENERIC_CLOCKEVENTS
471 This enables support for systems based on the Hilscher NetX Soc
477 select NEED_MACH_MEMORY_H
478 select NEED_RET_TO_USER
483 Support for Intel's IOP13XX (XScale) family of processors.
488 select ARCH_REQUIRE_GPIOLIB
491 select NEED_RET_TO_USER
495 Support for Intel's 80219 and IOP32X (XScale) family of
501 select ARCH_REQUIRE_GPIOLIB
504 select NEED_RET_TO_USER
508 Support for Intel's IOP33X (XScale) family of processors.
513 select ARCH_HAS_DMA_SET_COHERENT_MASK
514 select ARCH_REQUIRE_GPIOLIB
515 select ARCH_SUPPORTS_BIG_ENDIAN
518 select DMABOUNCE if PCI
519 select GENERIC_CLOCKEVENTS
520 select MIGHT_HAVE_PCI
521 select NEED_MACH_IO_H
522 select USB_EHCI_BIG_ENDIAN_DESC
523 select USB_EHCI_BIG_ENDIAN_MMIO
525 Support for Intel's IXP4XX (XScale) family of processors.
529 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
532 select MIGHT_HAVE_PCI
536 select PLAT_ORION_LEGACY
538 Support for the Marvell Dove SoC 88AP510
541 bool "Marvell Kirkwood"
542 select ARCH_HAS_CPUFREQ
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
550 select PINCTRL_KIRKWOOD
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Kirkwood series SoCs:
554 88F6180, 88F6192 and 88F6281.
557 bool "Marvell MV78xx0"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
563 select PLAT_ORION_LEGACY
565 Support for the following Marvell MV78xx0 series SoCs:
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
576 select PLAT_ORION_LEGACY
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
583 bool "Marvell PXA168/910/MMP2"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
591 select MULTI_IRQ_HANDLER
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
636 Support for the NXP LPC32XX family of processors
639 bool "PXA2xx/PXA3xx-based"
641 select ARCH_HAS_CPUFREQ
643 select ARCH_REQUIRE_GPIOLIB
644 select ARM_CPU_SUSPEND if PM
648 select GENERIC_CLOCKEVENTS
651 select MULTI_IRQ_HANDLER
655 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
658 bool "Qualcomm MSM (non-multiplatform)"
659 select ARCH_REQUIRE_GPIOLIB
661 select GENERIC_CLOCKEVENTS
663 Support for Qualcomm MSM/QSD based systems. This runs on the
664 apps processor of the MSM/QSD and depends on a shared memory
665 interface to the modem processor which runs the baseband
666 stack and controls some vital subsystems
667 (clock and power control, etc).
669 config ARCH_SHMOBILE_LEGACY
670 bool "Renesas ARM SoCs (non-multiplatform)"
672 select ARM_PATCH_PHYS_VIRT
674 select GENERIC_CLOCKEVENTS
675 select HAVE_ARM_SCU if SMP
676 select HAVE_ARM_TWD if SMP
677 select HAVE_MACH_CLKDEV
679 select MIGHT_HAVE_CACHE_L2X0
680 select MULTI_IRQ_HANDLER
683 select PM_GENERIC_DOMAINS if PM
686 Support for Renesas ARM SoC platforms using a non-multiplatform
687 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
693 select ARCH_MAY_HAVE_PC_FDC
694 select ARCH_SPARSEMEM_ENABLE
695 select ARCH_USES_GETTIMEOFFSET
699 select HAVE_PATA_PLATFORM
701 select NEED_MACH_IO_H
702 select NEED_MACH_MEMORY_H
706 On the Acorn Risc-PC, Linux can support the internal IDE disk and
707 CD-ROM interface, serial and parallel port, and the floppy drive.
711 select ARCH_HAS_CPUFREQ
713 select ARCH_REQUIRE_GPIOLIB
714 select ARCH_SPARSEMEM_ENABLE
719 select GENERIC_CLOCKEVENTS
722 select NEED_MACH_MEMORY_H
725 Support for StrongARM 11x0 based boards.
728 bool "Samsung S3C24XX SoCs"
729 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
734 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select HAVE_S3C_RTC if RTC_CLASS
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H
743 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
744 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
745 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
746 Samsung SMDK2410 development board (and derivatives).
749 bool "Samsung S3C64XX"
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
756 select CLKSRC_SAMSUNG_PWM
759 select GENERIC_CLOCKEVENTS
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 select PM_GENERIC_DOMAINS if PM
768 select S3C_GPIO_TRACK
770 select SAMSUNG_WAKEMASK
771 select SAMSUNG_WDT_RESET
773 Samsung S3C64XX series based systems
776 bool "Samsung S5P6440 S5P6450"
779 select CLKSRC_SAMSUNG_PWM
781 select GENERIC_CLOCKEVENTS
783 select HAVE_S3C2410_I2C if I2C
784 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 select HAVE_S3C_RTC if RTC_CLASS
786 select NEED_MACH_GPIO_H
788 select SAMSUNG_WDT_RESET
790 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
794 bool "Samsung S5PC100"
795 select ARCH_REQUIRE_GPIOLIB
798 select CLKSRC_SAMSUNG_PWM
800 select GENERIC_CLOCKEVENTS
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select HAVE_S3C_RTC if RTC_CLASS
805 select NEED_MACH_GPIO_H
807 select SAMSUNG_WDT_RESET
809 Samsung S5PC100 series based systems
812 bool "Samsung S5PV210/S5PC110"
813 select ARCH_HAS_CPUFREQ
814 select ARCH_HAS_HOLES_MEMORYMODEL
815 select ARCH_SPARSEMEM_ENABLE
818 select CLKSRC_SAMSUNG_PWM
820 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_GPIO_H
826 select NEED_MACH_MEMORY_H
829 Samsung S5PV210/S5PC110 series based systems
832 bool "Samsung EXYNOS"
833 select ARCH_HAS_CPUFREQ
834 select ARCH_HAS_HOLES_MEMORYMODEL
835 select ARCH_REQUIRE_GPIOLIB
836 select ARCH_SPARSEMEM_ENABLE
840 select GENERIC_CLOCKEVENTS
841 select HAVE_S3C2410_I2C if I2C
842 select HAVE_S3C2410_WATCHDOG if WATCHDOG
843 select HAVE_S3C_RTC if RTC_CLASS
844 select NEED_MACH_MEMORY_H
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_REQUIRE_GPIOLIB
856 select GENERIC_ALLOCATOR
857 select GENERIC_CLOCKEVENTS
858 select GENERIC_IRQ_CHIP
864 Support for TI's DaVinci platform.
869 select ARCH_HAS_CPUFREQ
870 select ARCH_HAS_HOLES_MEMORYMODEL
872 select ARCH_REQUIRE_GPIOLIB
875 select GENERIC_CLOCKEVENTS
876 select GENERIC_IRQ_CHIP
879 select NEED_MACH_IO_H if PCCARD
880 select NEED_MACH_MEMORY_H
882 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
886 menu "Multiple platform selection"
887 depends on ARCH_MULTIPLATFORM
889 comment "CPU Core family selection"
892 bool "ARMv4 based platforms (FA526)"
893 depends on !ARCH_MULTI_V6_V7
894 select ARCH_MULTI_V4_V5
897 config ARCH_MULTI_V4T
898 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
899 depends on !ARCH_MULTI_V6_V7
900 select ARCH_MULTI_V4_V5
901 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
902 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
903 CPU_ARM925T || CPU_ARM940T)
906 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
907 depends on !ARCH_MULTI_V6_V7
908 select ARCH_MULTI_V4_V5
909 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
910 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
911 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
913 config ARCH_MULTI_V4_V5
917 bool "ARMv6 based platforms (ARM11)"
918 select ARCH_MULTI_V6_V7
922 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
924 select ARCH_MULTI_V6_V7
928 config ARCH_MULTI_V6_V7
930 select MIGHT_HAVE_CACHE_L2X0
932 config ARCH_MULTI_CPU_AUTO
933 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
939 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
943 select HAVE_ARM_ARCH_TIMER
946 # This is sorted alphabetically by mach-* pathname. However, plat-*
947 # Kconfigs may be included either alphabetically (according to the
948 # plat- suffix) or along side the corresponding mach-* source.
950 source "arch/arm/mach-mvebu/Kconfig"
952 source "arch/arm/mach-at91/Kconfig"
954 source "arch/arm/mach-axxia/Kconfig"
956 source "arch/arm/mach-bcm/Kconfig"
958 source "arch/arm/mach-berlin/Kconfig"
960 source "arch/arm/mach-clps711x/Kconfig"
962 source "arch/arm/mach-cns3xxx/Kconfig"
964 source "arch/arm/mach-davinci/Kconfig"
966 source "arch/arm/mach-dove/Kconfig"
968 source "arch/arm/mach-ep93xx/Kconfig"
970 source "arch/arm/mach-footbridge/Kconfig"
972 source "arch/arm/mach-gemini/Kconfig"
974 source "arch/arm/mach-highbank/Kconfig"
976 source "arch/arm/mach-hisi/Kconfig"
978 source "arch/arm/mach-integrator/Kconfig"
980 source "arch/arm/mach-iop32x/Kconfig"
982 source "arch/arm/mach-iop33x/Kconfig"
984 source "arch/arm/mach-iop13xx/Kconfig"
986 source "arch/arm/mach-ixp4xx/Kconfig"
988 source "arch/arm/mach-keystone/Kconfig"
990 source "arch/arm/mach-kirkwood/Kconfig"
992 source "arch/arm/mach-ks8695/Kconfig"
994 source "arch/arm/mach-msm/Kconfig"
996 source "arch/arm/mach-moxart/Kconfig"
998 source "arch/arm/mach-mv78xx0/Kconfig"
1000 source "arch/arm/mach-imx/Kconfig"
1002 source "arch/arm/mach-mxs/Kconfig"
1004 source "arch/arm/mach-netx/Kconfig"
1006 source "arch/arm/mach-nomadik/Kconfig"
1008 source "arch/arm/mach-nspire/Kconfig"
1010 source "arch/arm/plat-omap/Kconfig"
1012 source "arch/arm/mach-omap1/Kconfig"
1014 source "arch/arm/mach-omap2/Kconfig"
1016 source "arch/arm/mach-orion5x/Kconfig"
1018 source "arch/arm/mach-picoxcell/Kconfig"
1020 source "arch/arm/mach-pxa/Kconfig"
1021 source "arch/arm/plat-pxa/Kconfig"
1023 source "arch/arm/mach-mmp/Kconfig"
1025 source "arch/arm/mach-qcom/Kconfig"
1027 source "arch/arm/mach-realview/Kconfig"
1029 source "arch/arm/mach-rockchip/Kconfig"
1031 source "arch/arm/mach-sa1100/Kconfig"
1033 source "arch/arm/plat-samsung/Kconfig"
1035 source "arch/arm/mach-socfpga/Kconfig"
1037 source "arch/arm/mach-spear/Kconfig"
1039 source "arch/arm/mach-sti/Kconfig"
1041 source "arch/arm/mach-s3c24xx/Kconfig"
1043 source "arch/arm/mach-s3c64xx/Kconfig"
1045 source "arch/arm/mach-s5p64x0/Kconfig"
1047 source "arch/arm/mach-s5pc100/Kconfig"
1049 source "arch/arm/mach-s5pv210/Kconfig"
1051 source "arch/arm/mach-exynos/Kconfig"
1053 source "arch/arm/mach-shmobile/Kconfig"
1055 source "arch/arm/mach-sunxi/Kconfig"
1057 source "arch/arm/mach-prima2/Kconfig"
1059 source "arch/arm/mach-tegra/Kconfig"
1061 source "arch/arm/mach-u300/Kconfig"
1063 source "arch/arm/mach-ux500/Kconfig"
1065 source "arch/arm/mach-versatile/Kconfig"
1067 source "arch/arm/mach-vexpress/Kconfig"
1068 source "arch/arm/plat-versatile/Kconfig"
1070 source "arch/arm/mach-vt8500/Kconfig"
1072 source "arch/arm/mach-w90x900/Kconfig"
1074 source "arch/arm/mach-zynq/Kconfig"
1076 # Definitions to make life easier
1082 select GENERIC_CLOCKEVENTS
1088 select GENERIC_IRQ_CHIP
1091 config PLAT_ORION_LEGACY
1098 config PLAT_VERSATILE
1101 config ARM_TIMER_SP804
1104 select CLKSRC_OF if OF
1106 source "arch/arm/firmware/Kconfig"
1108 source arch/arm/mm/Kconfig
1112 default 16 if ARCH_EP93XX
1116 bool "Enable iWMMXt support"
1117 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1118 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1120 Enable support for iWMMXt context switching at run time if
1121 running on a CPU that supports it.
1123 config MULTI_IRQ_HANDLER
1126 Allow each machine to specify it's own IRQ handler at run time.
1129 source "arch/arm/Kconfig-nommu"
1132 config PJ4B_ERRATA_4742
1133 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1134 depends on CPU_PJ4B && MACH_ARMADA_370
1137 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1138 Event (WFE) IDLE states, a specific timing sensitivity exists between
1139 the retiring WFI/WFE instructions and the newly issued subsequent
1140 instructions. This sensitivity can result in a CPU hang scenario.
1142 The software must insert either a Data Synchronization Barrier (DSB)
1143 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1146 config ARM_ERRATA_326103
1147 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1150 Executing a SWP instruction to read-only memory does not set bit 11
1151 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1152 treat the access as a read, preventing a COW from occurring and
1153 causing the faulting task to livelock.
1155 config ARM_ERRATA_411920
1156 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1157 depends on CPU_V6 || CPU_V6K
1159 Invalidation of the Instruction Cache operation can
1160 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1161 It does not affect the MPCore. This option enables the ARM Ltd.
1162 recommended workaround.
1164 config ARM_ERRATA_430973
1165 bool "ARM errata: Stale prediction on replaced interworking branch"
1168 This option enables the workaround for the 430973 Cortex-A8
1169 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1170 interworking branch is replaced with another code sequence at the
1171 same virtual address, whether due to self-modifying code or virtual
1172 to physical address re-mapping, Cortex-A8 does not recover from the
1173 stale interworking branch prediction. This results in Cortex-A8
1174 executing the new code sequence in the incorrect ARM or Thumb state.
1175 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1176 and also flushes the branch target cache at every context switch.
1177 Note that setting specific bits in the ACTLR register may not be
1178 available in non-secure mode.
1180 config ARM_ERRATA_458693
1181 bool "ARM errata: Processor deadlock when a false hazard is created"
1183 depends on !ARCH_MULTIPLATFORM
1185 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1186 erratum. For very specific sequences of memory operations, it is
1187 possible for a hazard condition intended for a cache line to instead
1188 be incorrectly associated with a different cache line. This false
1189 hazard might then cause a processor deadlock. The workaround enables
1190 the L1 caching of the NEON accesses and disables the PLD instruction
1191 in the ACTLR register. Note that setting specific bits in the ACTLR
1192 register may not be available in non-secure mode.
1194 config ARM_ERRATA_460075
1195 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1197 depends on !ARCH_MULTIPLATFORM
1199 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1200 erratum. Any asynchronous access to the L2 cache may encounter a
1201 situation in which recent store transactions to the L2 cache are lost
1202 and overwritten with stale memory contents from external memory. The
1203 workaround disables the write-allocate mode for the L2 cache via the
1204 ACTLR register. Note that setting specific bits in the ACTLR register
1205 may not be available in non-secure mode.
1207 config ARM_ERRATA_742230
1208 bool "ARM errata: DMB operation may be faulty"
1209 depends on CPU_V7 && SMP
1210 depends on !ARCH_MULTIPLATFORM
1212 This option enables the workaround for the 742230 Cortex-A9
1213 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1214 between two write operations may not ensure the correct visibility
1215 ordering of the two writes. This workaround sets a specific bit in
1216 the diagnostic register of the Cortex-A9 which causes the DMB
1217 instruction to behave as a DSB, ensuring the correct behaviour of
1220 config ARM_ERRATA_742231
1221 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1222 depends on CPU_V7 && SMP
1223 depends on !ARCH_MULTIPLATFORM
1225 This option enables the workaround for the 742231 Cortex-A9
1226 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1227 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1228 accessing some data located in the same cache line, may get corrupted
1229 data due to bad handling of the address hazard when the line gets
1230 replaced from one of the CPUs at the same time as another CPU is
1231 accessing it. This workaround sets specific bits in the diagnostic
1232 register of the Cortex-A9 which reduces the linefill issuing
1233 capabilities of the processor.
1235 config PL310_ERRATA_588369
1236 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1237 depends on CACHE_L2X0
1239 The PL310 L2 cache controller implements three types of Clean &
1240 Invalidate maintenance operations: by Physical Address
1241 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1242 They are architecturally defined to behave as the execution of a
1243 clean operation followed immediately by an invalidate operation,
1244 both performing to the same memory location. This functionality
1245 is not correctly implemented in PL310 as clean lines are not
1246 invalidated as a result of these operations.
1248 config ARM_ERRATA_643719
1249 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1250 depends on CPU_V7 && SMP
1252 This option enables the workaround for the 643719 Cortex-A9 (prior to
1253 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1254 register returns zero when it should return one. The workaround
1255 corrects this value, ensuring cache maintenance operations which use
1256 it behave as intended and avoiding data corruption.
1258 config ARM_ERRATA_720789
1259 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1262 This option enables the workaround for the 720789 Cortex-A9 (prior to
1263 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1264 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1265 As a consequence of this erratum, some TLB entries which should be
1266 invalidated are not, resulting in an incoherency in the system page
1267 tables. The workaround changes the TLB flushing routines to invalidate
1268 entries regardless of the ASID.
1270 config PL310_ERRATA_727915
1271 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1272 depends on CACHE_L2X0
1274 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1275 operation (offset 0x7FC). This operation runs in background so that
1276 PL310 can handle normal accesses while it is in progress. Under very
1277 rare circumstances, due to this erratum, write data can be lost when
1278 PL310 treats a cacheable write transaction during a Clean &
1279 Invalidate by Way operation.
1281 config ARM_ERRATA_743622
1282 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1284 depends on !ARCH_MULTIPLATFORM
1286 This option enables the workaround for the 743622 Cortex-A9
1287 (r2p*) erratum. Under very rare conditions, a faulty
1288 optimisation in the Cortex-A9 Store Buffer may lead to data
1289 corruption. This workaround sets a specific bit in the diagnostic
1290 register of the Cortex-A9 which disables the Store Buffer
1291 optimisation, preventing the defect from occurring. This has no
1292 visible impact on the overall performance or power consumption of the
1295 config ARM_ERRATA_751472
1296 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1298 depends on !ARCH_MULTIPLATFORM
1300 This option enables the workaround for the 751472 Cortex-A9 (prior
1301 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1302 completion of a following broadcasted operation if the second
1303 operation is received by a CPU before the ICIALLUIS has completed,
1304 potentially leading to corrupted entries in the cache or TLB.
1306 config PL310_ERRATA_753970
1307 bool "PL310 errata: cache sync operation may be faulty"
1308 depends on CACHE_PL310
1310 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1312 Under some condition the effect of cache sync operation on
1313 the store buffer still remains when the operation completes.
1314 This means that the store buffer is always asked to drain and
1315 this prevents it from merging any further writes. The workaround
1316 is to replace the normal offset of cache sync operation (0x730)
1317 by another offset targeting an unmapped PL310 register 0x740.
1318 This has the same effect as the cache sync operation: store buffer
1319 drain and waiting for all buffers empty.
1321 config ARM_ERRATA_754322
1322 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1325 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1326 r3p*) erratum. A speculative memory access may cause a page table walk
1327 which starts prior to an ASID switch but completes afterwards. This
1328 can populate the micro-TLB with a stale entry which may be hit with
1329 the new ASID. This workaround places two dsb instructions in the mm
1330 switching code so that no page table walks can cross the ASID switch.
1332 config ARM_ERRATA_754327
1333 bool "ARM errata: no automatic Store Buffer drain"
1334 depends on CPU_V7 && SMP
1336 This option enables the workaround for the 754327 Cortex-A9 (prior to
1337 r2p0) erratum. The Store Buffer does not have any automatic draining
1338 mechanism and therefore a livelock may occur if an external agent
1339 continuously polls a memory location waiting to observe an update.
1340 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1341 written polling loops from denying visibility of updates to memory.
1343 config ARM_ERRATA_364296
1344 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1347 This options enables the workaround for the 364296 ARM1136
1348 r0p2 erratum (possible cache data corruption with
1349 hit-under-miss enabled). It sets the undocumented bit 31 in
1350 the auxiliary control register and the FI bit in the control
1351 register, thus disabling hit-under-miss without putting the
1352 processor into full low interrupt latency mode. ARM11MPCore
1355 config ARM_ERRATA_764369
1356 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1357 depends on CPU_V7 && SMP
1359 This option enables the workaround for erratum 764369
1360 affecting Cortex-A9 MPCore with two or more processors (all
1361 current revisions). Under certain timing circumstances, a data
1362 cache line maintenance operation by MVA targeting an Inner
1363 Shareable memory region may fail to proceed up to either the
1364 Point of Coherency or to the Point of Unification of the
1365 system. This workaround adds a DSB instruction before the
1366 relevant cache maintenance functions and sets a specific bit
1367 in the diagnostic control register of the SCU.
1369 config PL310_ERRATA_769419
1370 bool "PL310 errata: no automatic Store Buffer drain"
1371 depends on CACHE_L2X0
1373 On revisions of the PL310 prior to r3p2, the Store Buffer does
1374 not automatically drain. This can cause normal, non-cacheable
1375 writes to be retained when the memory system is idle, leading
1376 to suboptimal I/O performance for drivers using coherent DMA.
1377 This option adds a write barrier to the cpu_idle loop so that,
1378 on systems with an outer cache, the store buffer is drained
1381 config ARM_ERRATA_775420
1382 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1385 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1386 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1387 operation aborts with MMU exception, it might cause the processor
1388 to deadlock. This workaround puts DSB before executing ISB if
1389 an abort may occur on cache maintenance.
1391 config ARM_ERRATA_798181
1392 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1393 depends on CPU_V7 && SMP
1395 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1396 adequately shooting down all use of the old entries. This
1397 option enables the Linux kernel workaround for this erratum
1398 which sends an IPI to the CPUs that are running the same ASID
1399 as the one being invalidated.
1401 config ARM_ERRATA_773022
1402 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1405 This option enables the workaround for the 773022 Cortex-A15
1406 (up to r0p4) erratum. In certain rare sequences of code, the
1407 loop buffer may deliver incorrect instructions. This
1408 workaround disables the loop buffer to avoid the erratum.
1412 source "arch/arm/common/Kconfig"
1422 Find out whether you have ISA slots on your motherboard. ISA is the
1423 name of a bus system, i.e. the way the CPU talks to the other stuff
1424 inside your box. Other bus systems are PCI, EISA, MicroChannel
1425 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1426 newer boards don't support it. If you have ISA, say Y, otherwise N.
1428 # Select ISA DMA controller support
1433 # Select ISA DMA interface
1438 bool "PCI support" if MIGHT_HAVE_PCI
1440 Find out whether you have a PCI motherboard. PCI is the name of a
1441 bus system, i.e. the way the CPU talks to the other stuff inside
1442 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1443 VESA. If you have PCI, say Y, otherwise N.
1449 config PCI_NANOENGINE
1450 bool "BSE nanoEngine PCI support"
1451 depends on SA1100_NANOENGINE
1453 Enable PCI on the BSE nanoEngine board.
1458 config PCI_HOST_ITE8152
1460 depends on PCI && MACH_ARMCORE
1464 source "drivers/pci/Kconfig"
1465 source "drivers/pci/pcie/Kconfig"
1467 source "drivers/pcmcia/Kconfig"
1471 menu "Kernel Features"
1476 This option should be selected by machines which have an SMP-
1479 The only effect of this option is to make the SMP-related
1480 options available to the user for configuration.
1483 bool "Symmetric Multi-Processing"
1484 depends on CPU_V6K || CPU_V7
1485 depends on GENERIC_CLOCKEVENTS
1487 depends on MMU || ARM_MPU
1489 This enables support for systems with more than one CPU. If you have
1490 a system with only one CPU, say N. If you have a system with more
1491 than one CPU, say Y.
1493 If you say N here, the kernel will run on uni- and multiprocessor
1494 machines, but will use only one CPU of a multiprocessor machine. If
1495 you say Y here, the kernel will run on many, but not all,
1496 uniprocessor machines. On a uniprocessor machine, the kernel
1497 will run faster if you say N here.
1499 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1500 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1501 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1503 If you don't know what to do here, say N.
1506 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1507 depends on SMP && !XIP_KERNEL && MMU
1510 SMP kernels contain instructions which fail on non-SMP processors.
1511 Enabling this option allows the kernel to modify itself to make
1512 these instructions safe. Disabling it allows about 1K of space
1515 If you don't know what to do here, say Y.
1517 config ARM_CPU_TOPOLOGY
1518 bool "Support cpu topology definition"
1519 depends on SMP && CPU_V7
1522 Support ARM cpu topology definition. The MPIDR register defines
1523 affinity between processors which is then used to describe the cpu
1524 topology of an ARM System.
1527 bool "Multi-core scheduler support"
1528 depends on ARM_CPU_TOPOLOGY
1530 Multi-core scheduler support improves the CPU scheduler's decision
1531 making when dealing with multi-core CPU chips at a cost of slightly
1532 increased overhead in some places. If unsure say N here.
1535 bool "SMT scheduler support"
1536 depends on ARM_CPU_TOPOLOGY
1538 Improves the CPU scheduler's decision making when dealing with
1539 MultiThreading at a cost of slightly increased overhead in some
1540 places. If unsure say N here.
1545 This option enables support for the ARM system coherency unit
1547 config HAVE_ARM_ARCH_TIMER
1548 bool "Architected timer support"
1550 select ARM_ARCH_TIMER
1551 select GENERIC_CLOCKEVENTS
1553 This option enables support for the ARM architected timer
1558 select CLKSRC_OF if OF
1560 This options enables support for the ARM timer and watchdog unit
1563 bool "Multi-Cluster Power Management"
1564 depends on CPU_V7 && SMP
1566 This option provides the common power management infrastructure
1567 for (multi-)cluster based systems, such as big.LITTLE based
1571 bool "big.LITTLE support (Experimental)"
1572 depends on CPU_V7 && SMP
1575 This option enables support selections for the big.LITTLE
1576 system architecture.
1579 bool "big.LITTLE switcher support"
1580 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1581 select ARM_CPU_SUSPEND
1584 The big.LITTLE "switcher" provides the core functionality to
1585 transparently handle transition between a cluster of A15's
1586 and a cluster of A7's in a big.LITTLE system.
1588 config BL_SWITCHER_DUMMY_IF
1589 tristate "Simple big.LITTLE switcher user interface"
1590 depends on BL_SWITCHER && DEBUG_KERNEL
1592 This is a simple and dummy char dev interface to control
1593 the big.LITTLE switcher core code. It is meant for
1594 debugging purposes only.
1597 prompt "Memory split"
1601 Select the desired split between kernel and user memory.
1603 If you are not absolutely sure what you are doing, leave this
1607 bool "3G/1G user/kernel split"
1609 bool "2G/2G user/kernel split"
1611 bool "1G/3G user/kernel split"
1616 default PHYS_OFFSET if !MMU
1617 default 0x40000000 if VMSPLIT_1G
1618 default 0x80000000 if VMSPLIT_2G
1622 int "Maximum number of CPUs (2-32)"
1628 bool "Support for hot-pluggable CPUs"
1631 Say Y here to experiment with turning CPUs off and on. CPUs
1632 can be controlled through /sys/devices/system/cpu.
1635 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1638 Say Y here if you want Linux to communicate with system firmware
1639 implementing the PSCI specification for CPU-centric power
1640 management operations described in ARM document number ARM DEN
1641 0022A ("Power State Coordination Interface System Software on
1644 # The GPIO number here must be sorted by descending number. In case of
1645 # a multiplatform kernel, we just want the highest value required by the
1646 # selected platforms.
1649 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1650 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1651 default 392 if ARCH_U8500
1652 default 352 if ARCH_VT8500
1653 default 288 if ARCH_SUNXI
1654 default 264 if MACH_H4700
1657 Maximum number of GPIOs in the system.
1659 If unsure, leave the default value.
1661 source kernel/Kconfig.preempt
1665 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1666 ARCH_S5PV210 || ARCH_EXYNOS4
1667 default AT91_TIMER_HZ if ARCH_AT91
1668 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1672 depends on HZ_FIXED = 0
1673 prompt "Timer frequency"
1697 default HZ_FIXED if HZ_FIXED != 0
1698 default 100 if HZ_100
1699 default 200 if HZ_200
1700 default 250 if HZ_250
1701 default 300 if HZ_300
1702 default 500 if HZ_500
1706 def_bool HIGH_RES_TIMERS
1708 config THUMB2_KERNEL
1709 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1710 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1711 default y if CPU_THUMBONLY
1713 select ARM_ASM_UNIFIED
1716 By enabling this option, the kernel will be compiled in
1717 Thumb-2 mode. A compiler/assembler that understand the unified
1718 ARM-Thumb syntax is needed.
1722 config THUMB2_AVOID_R_ARM_THM_JUMP11
1723 bool "Work around buggy Thumb-2 short branch relocations in gas"
1724 depends on THUMB2_KERNEL && MODULES
1727 Various binutils versions can resolve Thumb-2 branches to
1728 locally-defined, preemptible global symbols as short-range "b.n"
1729 branch instructions.
1731 This is a problem, because there's no guarantee the final
1732 destination of the symbol, or any candidate locations for a
1733 trampoline, are within range of the branch. For this reason, the
1734 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1735 relocation in modules at all, and it makes little sense to add
1738 The symptom is that the kernel fails with an "unsupported
1739 relocation" error when loading some modules.
1741 Until fixed tools are available, passing
1742 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1743 code which hits this problem, at the cost of a bit of extra runtime
1744 stack usage in some cases.
1746 The problem is described in more detail at:
1747 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1749 Only Thumb-2 kernels are affected.
1751 Unless you are sure your tools don't have this problem, say Y.
1753 config ARM_ASM_UNIFIED
1757 bool "Use the ARM EABI to compile the kernel"
1759 This option allows for the kernel to be compiled using the latest
1760 ARM ABI (aka EABI). This is only useful if you are using a user
1761 space environment that is also compiled with EABI.
1763 Since there are major incompatibilities between the legacy ABI and
1764 EABI, especially with regard to structure member alignment, this
1765 option also changes the kernel syscall calling convention to
1766 disambiguate both ABIs and allow for backward compatibility support
1767 (selected with CONFIG_OABI_COMPAT).
1769 To use this you need GCC version 4.0.0 or later.
1772 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1773 depends on AEABI && !THUMB2_KERNEL
1775 This option preserves the old syscall interface along with the
1776 new (ARM EABI) one. It also provides a compatibility layer to
1777 intercept syscalls that have structure arguments which layout
1778 in memory differs between the legacy ABI and the new ARM EABI
1779 (only for non "thumb" binaries). This option adds a tiny
1780 overhead to all syscalls and produces a slightly larger kernel.
1782 The seccomp filter system will not be available when this is
1783 selected, since there is no way yet to sensibly distinguish
1784 between calling conventions during filtering.
1786 If you know you'll be using only pure EABI user space then you
1787 can say N here. If this option is not selected and you attempt
1788 to execute a legacy ABI binary then the result will be
1789 UNPREDICTABLE (in fact it can be predicted that it won't work
1790 at all). If in doubt say N.
1792 config ARCH_HAS_HOLES_MEMORYMODEL
1795 config ARCH_SPARSEMEM_ENABLE
1798 config ARCH_SPARSEMEM_DEFAULT
1799 def_bool ARCH_SPARSEMEM_ENABLE
1801 config ARCH_SELECT_MEMORY_MODEL
1802 def_bool ARCH_SPARSEMEM_ENABLE
1804 config HAVE_ARCH_PFN_VALID
1805 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1808 bool "High Memory Support"
1811 The address space of ARM processors is only 4 Gigabytes large
1812 and it has to accommodate user address space, kernel address
1813 space as well as some memory mapped IO. That means that, if you
1814 have a large amount of physical memory and/or IO, not all of the
1815 memory can be "permanently mapped" by the kernel. The physical
1816 memory that is not permanently mapped is called "high memory".
1818 Depending on the selected kernel/user memory split, minimum
1819 vmalloc space and actual amount of RAM, you may not need this
1820 option which should result in a slightly faster kernel.
1825 bool "Allocate 2nd-level pagetables from highmem"
1828 config HW_PERF_EVENTS
1829 bool "Enable hardware performance counter support for perf events"
1830 depends on PERF_EVENTS
1833 Enable hardware performance counter support for perf events. If
1834 disabled, perf events will use software events only.
1836 config SYS_SUPPORTS_HUGETLBFS
1840 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1844 config ARCH_WANT_GENERAL_HUGETLB
1849 config FORCE_MAX_ZONEORDER
1850 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1851 range 11 64 if ARCH_SHMOBILE_LEGACY
1852 default "12" if SOC_AM33XX
1853 default "9" if SA1111 || ARCH_EFM32
1856 The kernel memory allocator divides physically contiguous memory
1857 blocks into "zones", where each zone is a power of two number of
1858 pages. This option selects the largest power of two that the kernel
1859 keeps in the memory allocator. If you need to allocate very large
1860 blocks of physically contiguous memory, then you may need to
1861 increase this value.
1863 This config option is actually maximum order plus one. For example,
1864 a value of 11 means that the largest free memory block is 2^10 pages.
1866 config ALIGNMENT_TRAP
1868 depends on CPU_CP15_MMU
1869 default y if !ARCH_EBSA110
1870 select HAVE_PROC_CPU if PROC_FS
1872 ARM processors cannot fetch/store information which is not
1873 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1874 address divisible by 4. On 32-bit ARM processors, these non-aligned
1875 fetch/store instructions will be emulated in software if you say
1876 here, which has a severe performance impact. This is necessary for
1877 correct operation of some network protocols. With an IP-only
1878 configuration it is safe to say N, otherwise say Y.
1880 config UACCESS_WITH_MEMCPY
1881 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1883 default y if CPU_FEROCEON
1885 Implement faster copy_to_user and clear_user methods for CPU
1886 cores where a 8-word STM instruction give significantly higher
1887 memory write throughput than a sequence of individual 32bit stores.
1889 A possible side effect is a slight increase in scheduling latency
1890 between threads sharing the same address space if they invoke
1891 such copy operations with large buffers.
1893 However, if the CPU data cache is using a write-allocate mode,
1894 this option is unlikely to provide any performance gain.
1898 prompt "Enable seccomp to safely compute untrusted bytecode"
1900 This kernel feature is useful for number crunching applications
1901 that may need to compute untrusted bytecode during their
1902 execution. By using pipes or other transports made available to
1903 the process as file descriptors supporting the read/write
1904 syscalls, it's possible to isolate those applications in
1905 their own address space using seccomp. Once seccomp is
1906 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1907 and the task is only allowed to execute a few safe syscalls
1908 defined by each seccomp mode.
1921 bool "Xen guest support on ARM (EXPERIMENTAL)"
1922 depends on ARM && AEABI && OF
1923 depends on CPU_V7 && !CPU_V6
1924 depends on !GENERIC_ATOMIC64
1926 select ARCH_DMA_ADDR_T_64BIT
1930 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1937 bool "Flattened Device Tree support"
1940 select OF_EARLY_FLATTREE
1941 select OF_RESERVED_MEM
1943 Include support for flattened device tree machine descriptions.
1946 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1949 This is the traditional way of passing data to the kernel at boot
1950 time. If you are solely relying on the flattened device tree (or
1951 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1952 to remove ATAGS support from your kernel binary. If unsure,
1955 config DEPRECATED_PARAM_STRUCT
1956 bool "Provide old way to pass kernel parameters"
1959 This was deprecated in 2001 and announced to live on for 5 years.
1960 Some old boot loaders still use this way.
1962 # Compressed boot loader in ROM. Yes, we really want to ask about
1963 # TEXT and BSS so we preserve their values in the config files.
1964 config ZBOOT_ROM_TEXT
1965 hex "Compressed ROM boot loader base address"
1968 The physical address at which the ROM-able zImage is to be
1969 placed in the target. Platforms which normally make use of
1970 ROM-able zImage formats normally set this to a suitable
1971 value in their defconfig file.
1973 If ZBOOT_ROM is not enabled, this has no effect.
1975 config ZBOOT_ROM_BSS
1976 hex "Compressed ROM boot loader BSS address"
1979 The base address of an area of read/write memory in the target
1980 for the ROM-able zImage which must be available while the
1981 decompressor is running. It must be large enough to hold the
1982 entire decompressed kernel plus an additional 128 KiB.
1983 Platforms which normally make use of ROM-able zImage formats
1984 normally set this to a suitable value in their defconfig file.
1986 If ZBOOT_ROM is not enabled, this has no effect.
1989 bool "Compressed boot loader in ROM/flash"
1990 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1991 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1993 Say Y here if you intend to execute your compressed kernel image
1994 (zImage) directly from ROM or flash. If unsure, say N.
1997 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1998 depends on ZBOOT_ROM && ARCH_SH7372
1999 default ZBOOT_ROM_NONE
2001 Include experimental SD/MMC loading code in the ROM-able zImage.
2002 With this enabled it is possible to write the ROM-able zImage
2003 kernel image to an MMC or SD card and boot the kernel straight
2004 from the reset vector. At reset the processor Mask ROM will load
2005 the first part of the ROM-able zImage which in turn loads the
2006 rest the kernel image to RAM.
2008 config ZBOOT_ROM_NONE
2009 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2011 Do not load image from SD or MMC
2013 config ZBOOT_ROM_MMCIF
2014 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2016 Load image from MMCIF hardware block.
2018 config ZBOOT_ROM_SH_MOBILE_SDHI
2019 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2021 Load image from SDHI hardware block
2025 config ARM_APPENDED_DTB
2026 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2029 With this option, the boot code will look for a device tree binary
2030 (DTB) appended to zImage
2031 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2033 This is meant as a backward compatibility convenience for those
2034 systems with a bootloader that can't be upgraded to accommodate
2035 the documented boot protocol using a device tree.
2037 Beware that there is very little in terms of protection against
2038 this option being confused by leftover garbage in memory that might
2039 look like a DTB header after a reboot if no actual DTB is appended
2040 to zImage. Do not leave this option active in a production kernel
2041 if you don't intend to always append a DTB. Proper passing of the
2042 location into r2 of a bootloader provided DTB is always preferable
2045 config ARM_ATAG_DTB_COMPAT
2046 bool "Supplement the appended DTB with traditional ATAG information"
2047 depends on ARM_APPENDED_DTB
2049 Some old bootloaders can't be updated to a DTB capable one, yet
2050 they provide ATAGs with memory configuration, the ramdisk address,
2051 the kernel cmdline string, etc. Such information is dynamically
2052 provided by the bootloader and can't always be stored in a static
2053 DTB. To allow a device tree enabled kernel to be used with such
2054 bootloaders, this option allows zImage to extract the information
2055 from the ATAG list and store it at run time into the appended DTB.
2058 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2059 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2061 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2062 bool "Use bootloader kernel arguments if available"
2064 Uses the command-line options passed by the boot loader instead of
2065 the device tree bootargs property. If the boot loader doesn't provide
2066 any, the device tree bootargs property will be used.
2068 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2069 bool "Extend with bootloader kernel arguments"
2071 The command-line arguments provided by the boot loader will be
2072 appended to the the device tree bootargs property.
2077 string "Default kernel command string"
2080 On some architectures (EBSA110 and CATS), there is currently no way
2081 for the boot loader to pass arguments to the kernel. For these
2082 architectures, you should supply some command-line options at build
2083 time by entering them here. As a minimum, you should specify the
2084 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2087 prompt "Kernel command line type" if CMDLINE != ""
2088 default CMDLINE_FROM_BOOTLOADER
2091 config CMDLINE_FROM_BOOTLOADER
2092 bool "Use bootloader kernel arguments if available"
2094 Uses the command-line options passed by the boot loader. If
2095 the boot loader doesn't provide any, the default kernel command
2096 string provided in CMDLINE will be used.
2098 config CMDLINE_EXTEND
2099 bool "Extend bootloader kernel arguments"
2101 The command-line arguments provided by the boot loader will be
2102 appended to the default kernel command string.
2104 config CMDLINE_FORCE
2105 bool "Always use the default kernel command string"
2107 Always use the default kernel command string, even if the boot
2108 loader passes other arguments to the kernel.
2109 This is useful if you cannot or don't want to change the
2110 command-line options your boot loader passes to the kernel.
2114 bool "Kernel Execute-In-Place from ROM"
2115 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2117 Execute-In-Place allows the kernel to run from non-volatile storage
2118 directly addressable by the CPU, such as NOR flash. This saves RAM
2119 space since the text section of the kernel is not loaded from flash
2120 to RAM. Read-write sections, such as the data section and stack,
2121 are still copied to RAM. The XIP kernel is not compressed since
2122 it has to run directly from flash, so it will take more space to
2123 store it. The flash address used to link the kernel object files,
2124 and for storing it, is configuration dependent. Therefore, if you
2125 say Y here, you must know the proper physical address where to
2126 store the kernel image depending on your own flash memory usage.
2128 Also note that the make target becomes "make xipImage" rather than
2129 "make zImage" or "make Image". The final kernel binary to put in
2130 ROM memory will be arch/arm/boot/xipImage.
2134 config XIP_PHYS_ADDR
2135 hex "XIP Kernel Physical Location"
2136 depends on XIP_KERNEL
2137 default "0x00080000"
2139 This is the physical address in your flash memory the kernel will
2140 be linked for and stored to. This address is dependent on your
2144 bool "Kexec system call (EXPERIMENTAL)"
2145 depends on (!SMP || PM_SLEEP_SMP)
2147 kexec is a system call that implements the ability to shutdown your
2148 current kernel, and to start another kernel. It is like a reboot
2149 but it is independent of the system firmware. And like a reboot
2150 you can start any kernel with it, not just Linux.
2152 It is an ongoing process to be certain the hardware in a machine
2153 is properly shutdown, so do not be surprised if this code does not
2154 initially work for you.
2157 bool "Export atags in procfs"
2158 depends on ATAGS && KEXEC
2161 Should the atags used to boot the kernel be exported in an "atags"
2162 file in procfs. Useful with kexec.
2165 bool "Build kdump crash kernel (EXPERIMENTAL)"
2167 Generate crash dump after being started by kexec. This should
2168 be normally only set in special crash dump kernels which are
2169 loaded in the main kernel with kexec-tools into a specially
2170 reserved region and then later executed after a crash by
2171 kdump/kexec. The crash dump kernel must be compiled to a
2172 memory address not used by the main kernel
2174 For more details see Documentation/kdump/kdump.txt
2176 config AUTO_ZRELADDR
2177 bool "Auto calculation of the decompressed kernel image address"
2179 ZRELADDR is the physical address where the decompressed kernel
2180 image will be placed. If AUTO_ZRELADDR is selected, the address
2181 will be determined at run-time by masking the current IP with
2182 0xf8000000. This assumes the zImage being placed in the first 128MB
2183 from start of memory.
2187 menu "CPU Power Management"
2190 source "drivers/cpufreq/Kconfig"
2193 source "drivers/cpuidle/Kconfig"
2197 menu "Floating point emulation"
2199 comment "At least one emulation must be selected"
2202 bool "NWFPE math emulation"
2203 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2205 Say Y to include the NWFPE floating point emulator in the kernel.
2206 This is necessary to run most binaries. Linux does not currently
2207 support floating point hardware so you need to say Y here even if
2208 your machine has an FPA or floating point co-processor podule.
2210 You may say N here if you are going to load the Acorn FPEmulator
2211 early in the bootup.
2214 bool "Support extended precision"
2215 depends on FPE_NWFPE
2217 Say Y to include 80-bit support in the kernel floating-point
2218 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2219 Note that gcc does not generate 80-bit operations by default,
2220 so in most cases this option only enlarges the size of the
2221 floating point emulator without any good reason.
2223 You almost surely want to say N here.
2226 bool "FastFPE math emulation (EXPERIMENTAL)"
2227 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2229 Say Y here to include the FAST floating point emulator in the kernel.
2230 This is an experimental much faster emulator which now also has full
2231 precision for the mantissa. It does not support any exceptions.
2232 It is very simple, and approximately 3-6 times faster than NWFPE.
2234 It should be sufficient for most programs. It may be not suitable
2235 for scientific calculations, but you have to check this for yourself.
2236 If you do not feel you need a faster FP emulation you should better
2240 bool "VFP-format floating point maths"
2241 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2243 Say Y to include VFP support code in the kernel. This is needed
2244 if your hardware includes a VFP unit.
2246 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2247 release notes and additional status information.
2249 Say N if your target does not have VFP hardware.
2257 bool "Advanced SIMD (NEON) Extension support"
2258 depends on VFPv3 && CPU_V7
2260 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2263 config KERNEL_MODE_NEON
2264 bool "Support for NEON in kernel mode"
2265 depends on NEON && AEABI
2267 Say Y to include support for NEON in kernel mode.
2271 menu "Userspace binary formats"
2273 source "fs/Kconfig.binfmt"
2276 tristate "RISC OS personality"
2279 Say Y here to include the kernel code necessary if you want to run
2280 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2281 experimental; if this sounds frightening, say N and sleep in peace.
2282 You can also say M here to compile this support as a module (which
2283 will be called arthur).
2287 menu "Power management options"
2289 source "kernel/power/Kconfig"
2291 config ARCH_SUSPEND_POSSIBLE
2292 depends on !ARCH_S5PC100
2293 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2294 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2297 config ARM_CPU_SUSPEND
2302 source "net/Kconfig"
2304 source "drivers/Kconfig"
2308 source "arch/arm/Kconfig.debug"
2310 source "security/Kconfig"
2312 source "crypto/Kconfig"
2314 source "lib/Kconfig"
2316 source "arch/arm/kvm/Kconfig"