4 select ARCH_CLOCKSOURCE_DATA
5 select ARCH_HAS_DEBUG_VIRTUAL
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
9 select ARCH_HAVE_CUSTOM_GPIO_H
10 select ARCH_HAS_GCOV_PROFILE_ALL
11 select ARCH_MIGHT_HAVE_PC_PARPORT
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_USE_BUILTIN_BSWAP
14 select ARCH_USE_CMPXCHG_LOCKREF
15 select ARCH_WANT_IPC_PARSE_VERSION
16 select BUILDTIME_EXTABLE_SORT if MMU
17 select CLONE_BACKWARDS
18 select CPU_PM if (SUSPEND || CPU_IDLE)
19 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
21 select EDAC_ATOMIC_SCRUB
22 select GENERIC_ALLOCATOR
23 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
24 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
25 select GENERIC_EARLY_IOREMAP
26 select GENERIC_IDLE_POLL_SETUP
27 select GENERIC_IRQ_PROBE
28 select GENERIC_IRQ_SHOW
29 select GENERIC_IRQ_SHOW_LEVEL
30 select GENERIC_PCI_IOMAP
31 select GENERIC_SCHED_CLOCK
32 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_STRNCPY_FROM_USER
34 select GENERIC_STRNLEN_USER
35 select HANDLE_DOMAIN_IRQ
36 select HARDIRQS_SW_RESEND
37 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
38 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
39 select HAVE_ARCH_HARDENED_USERCOPY
40 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
41 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
42 select HAVE_ARCH_MMAP_RND_BITS if MMU
43 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
44 select HAVE_ARCH_TRACEHOOK
45 select HAVE_ARM_SMCCC if CPU_V7
47 select HAVE_CC_STACKPROTECTOR
48 select HAVE_CONTEXT_TRACKING
49 select HAVE_C_RECORDMCOUNT
50 select HAVE_DEBUG_KMEMLEAK
51 select HAVE_DMA_API_DEBUG
52 select HAVE_DMA_CONTIGUOUS if MMU
53 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
54 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
55 select HAVE_EXIT_THREAD
56 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
57 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
58 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
59 select HAVE_GCC_PLUGINS
60 select HAVE_GENERIC_DMA_COHERENT
61 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
62 select HAVE_IDE if PCI || ISA || PCMCIA
63 select HAVE_IRQ_TIME_ACCOUNTING
64 select HAVE_KERNEL_GZIP
65 select HAVE_KERNEL_LZ4
66 select HAVE_KERNEL_LZMA
67 select HAVE_KERNEL_LZO
69 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
70 select HAVE_KRETPROBES if (HAVE_KPROBES)
72 select HAVE_MOD_ARCH_SPECIFIC
74 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
75 select HAVE_OPTPROBES if !THUMB2_KERNEL
76 select HAVE_PERF_EVENTS
78 select HAVE_PERF_USER_STACK_DUMP
79 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
80 select HAVE_REGS_AND_STACK_ACCESS_API
81 select HAVE_SYSCALL_TRACEPOINTS
83 select HAVE_VIRT_CPU_ACCOUNTING_GEN
84 select IRQ_FORCED_THREADING
85 select MODULES_USE_ELF_REL
87 select OF_EARLY_FLATTREE if OF
88 select OF_RESERVED_MEM if OF
90 select OLD_SIGSUSPEND3
91 select PERF_USE_VMALLOC
93 select SYS_SUPPORTS_APM_EMULATION
94 # Above selects are sorted alphabetically; please add new ones
95 # according to that. Thanks.
97 The ARM series is a line of low-power-consumption RISC chip designs
98 licensed by ARM Ltd and targeted at embedded applications and
99 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
100 manufactured, but legacy ARM-based PC hardware remains popular in
101 Europe. There is an ARM Linux project with a web page at
102 <http://www.arm.linux.org.uk/>.
104 config ARM_HAS_SG_CHAIN
105 select ARCH_HAS_SG_CHAIN
108 config NEED_SG_DMA_LENGTH
111 config ARM_DMA_USE_IOMMU
113 select ARM_HAS_SG_CHAIN
114 select NEED_SG_DMA_LENGTH
118 config ARM_DMA_IOMMU_ALIGNMENT
119 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
123 DMA mapping framework by default aligns all buffers to the smallest
124 PAGE_SIZE order which is greater than or equal to the requested buffer
125 size. This works well for buffers up to a few hundreds kilobytes, but
126 for larger buffers it just a waste of address space. Drivers which has
127 relatively small addressing window (like 64Mib) might run out of
128 virtual space with just a few allocations.
130 With this parameter you can specify the maximum PAGE_SIZE order for
131 DMA IOMMU buffers. Larger buffers will be aligned only to this
132 specified order. The order is expressed as a power of two multiplied
137 config MIGHT_HAVE_PCI
140 config SYS_SUPPORTS_APM_EMULATION
145 select GENERIC_ALLOCATOR
156 The Extended Industry Standard Architecture (EISA) bus was
157 developed as an open alternative to the IBM MicroChannel bus.
159 The EISA bus provided some of the features of the IBM MicroChannel
160 bus while maintaining backward compatibility with cards made for
161 the older ISA bus. The EISA bus saw limited use between 1988 and
162 1995 when it was made obsolete by the PCI bus.
164 Say Y here if you are building a kernel for an EISA-based machine.
171 config STACKTRACE_SUPPORT
175 config LOCKDEP_SUPPORT
179 config TRACE_IRQFLAGS_SUPPORT
183 config RWSEM_XCHGADD_ALGORITHM
187 config ARCH_HAS_ILOG2_U32
190 config ARCH_HAS_ILOG2_U64
193 config ARCH_HAS_BANDGAP
196 config FIX_EARLYCON_MEM
199 config GENERIC_HWEIGHT
203 config GENERIC_CALIBRATE_DELAY
207 config ARCH_MAY_HAVE_PC_FDC
213 config NEED_DMA_MAP_STATE
216 config ARCH_SUPPORTS_UPROBES
219 config ARCH_HAS_DMA_SET_COHERENT_MASK
222 config GENERIC_ISA_DMA
228 config NEED_RET_TO_USER
236 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
237 default DRAM_BASE if REMAP_VECTORS_TO_RAM
240 The base address of exception vectors. This must be two pages
243 config ARM_PATCH_PHYS_VIRT
244 bool "Patch physical to virtual translations at runtime" if EMBEDDED
246 depends on !XIP_KERNEL && MMU
248 Patch phys-to-virt and virt-to-phys translation functions at
249 boot and module load time according to the position of the
250 kernel in system memory.
252 This can only be used with non-XIP MMU kernels where the base
253 of physical memory is at a 16MB boundary.
255 Only disable this option if you know that you do not require
256 this feature (eg, building a kernel for a single machine) and
257 you need to shrink the kernel to the minimal size.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT
276 default DRAM_BASE if !MMU
277 default 0x00000000 if ARCH_EBSA110 || \
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x20000000 if ARCH_S5PV210
285 default 0xc0000000 if ARCH_SA1100
287 Please provide the physical address corresponding to the
288 location of main memory in your system.
294 config PGTABLE_LEVELS
296 default 3 if ARM_LPAE
299 source "init/Kconfig"
301 source "kernel/Kconfig.freezer"
306 bool "MMU-based Paged Memory Management Support"
309 Select if you want MMU-based virtualised addressing space
310 support by paged memory management. If unsure, say 'Y'.
312 config ARCH_MMAP_RND_BITS_MIN
315 config ARCH_MMAP_RND_BITS_MAX
316 default 14 if PAGE_OFFSET=0x40000000
317 default 15 if PAGE_OFFSET=0x80000000
321 # The "ARM system type" choice list is ordered alphabetically by option
322 # text. Please add new entries in the option alphabetic order.
325 prompt "ARM system type"
326 default ARM_SINGLE_ARMV7M if !MMU
327 default ARCH_MULTIPLATFORM if MMU
329 config ARCH_MULTIPLATFORM
330 bool "Allow multiple platforms to be selected"
332 select ARM_HAS_SG_CHAIN
333 select ARM_PATCH_PHYS_VIRT
337 select GENERIC_CLOCKEVENTS
338 select MIGHT_HAVE_PCI
339 select MULTI_IRQ_HANDLER
340 select PCI_DOMAINS if PCI
344 config ARM_SINGLE_ARMV7M
345 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
352 select GENERIC_CLOCKEVENTS
358 bool "Cortina Systems Gemini"
361 select GENERIC_CLOCKEVENTS
364 Support for the Cortina Systems Gemini family SoCs
368 select ARCH_USES_GETTIMEOFFSET
371 select NEED_MACH_IO_H
372 select NEED_MACH_MEMORY_H
375 This is an evaluation board for the StrongARM processor available
376 from Digital. It has limited hardware on-board, including an
377 Ethernet interface, two PCMCIA sockets, two serial ports and a
382 select ARCH_HAS_HOLES_MEMORYMODEL
384 select ARM_PATCH_PHYS_VIRT
390 select GENERIC_CLOCKEVENTS
393 This enables support for the Cirrus EP93xx series of CPUs.
395 config ARCH_FOOTBRIDGE
399 select GENERIC_CLOCKEVENTS
401 select NEED_MACH_IO_H if !MMU
402 select NEED_MACH_MEMORY_H
404 Support for systems based on the DC21285 companion chip
405 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
408 bool "Hilscher NetX based"
412 select GENERIC_CLOCKEVENTS
414 This enables support for systems based on the Hilscher NetX Soc
420 select NEED_MACH_MEMORY_H
421 select NEED_RET_TO_USER
427 Support for Intel's IOP13XX (XScale) family of processors.
435 select NEED_RET_TO_USER
439 Support for Intel's 80219 and IOP32X (XScale) family of
448 select NEED_RET_TO_USER
452 Support for Intel's IOP33X (XScale) family of processors.
457 select ARCH_HAS_DMA_SET_COHERENT_MASK
458 select ARCH_SUPPORTS_BIG_ENDIAN
461 select DMABOUNCE if PCI
462 select GENERIC_CLOCKEVENTS
464 select MIGHT_HAVE_PCI
465 select NEED_MACH_IO_H
466 select USB_EHCI_BIG_ENDIAN_DESC
467 select USB_EHCI_BIG_ENDIAN_MMIO
469 Support for Intel's IXP4XX (XScale) family of processors.
474 select GENERIC_CLOCKEVENTS
476 select MIGHT_HAVE_PCI
477 select MULTI_IRQ_HANDLER
481 select PLAT_ORION_LEGACY
483 select PM_GENERIC_DOMAINS if PM
485 Support for the Marvell Dove SoC 88AP510
488 bool "Micrel/Kendin KS8695"
491 select GENERIC_CLOCKEVENTS
493 select NEED_MACH_MEMORY_H
495 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
496 System-on-Chip devices.
499 bool "Nuvoton W90X900 CPU"
503 select GENERIC_CLOCKEVENTS
506 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
507 At present, the w90x900 has been renamed nuc900, regarding
508 the ARM series product line, you can login the following
509 link address to know more.
511 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
512 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
518 select CLKSRC_LPC32XX
521 select GENERIC_CLOCKEVENTS
523 select MULTI_IRQ_HANDLER
527 Support for the NXP LPC32XX family of processors
530 bool "PXA2xx/PXA3xx-based"
533 select ARM_CPU_SUSPEND if PM
540 select CPU_XSCALE if !CPU_XSC3
541 select GENERIC_CLOCKEVENTS
546 select MULTI_IRQ_HANDLER
550 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
556 select ARCH_MAY_HAVE_PC_FDC
557 select ARCH_SPARSEMEM_ENABLE
558 select ARCH_USES_GETTIMEOFFSET
562 select HAVE_PATA_PLATFORM
564 select NEED_MACH_IO_H
565 select NEED_MACH_MEMORY_H
568 On the Acorn Risc-PC, Linux can support the internal IDE disk and
569 CD-ROM interface, serial and parallel port, and the floppy drive.
574 select ARCH_SPARSEMEM_ENABLE
578 select CLKSRC_OF if OF
581 select GENERIC_CLOCKEVENTS
586 select MULTI_IRQ_HANDLER
587 select NEED_MACH_MEMORY_H
590 Support for StrongARM 11x0 based boards.
593 bool "Samsung S3C24XX SoCs"
596 select CLKSRC_SAMSUNG_PWM
597 select GENERIC_CLOCKEVENTS
600 select HAVE_S3C2410_I2C if I2C
601 select HAVE_S3C2410_WATCHDOG if WATCHDOG
602 select HAVE_S3C_RTC if RTC_CLASS
603 select MULTI_IRQ_HANDLER
604 select NEED_MACH_IO_H
607 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
608 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
609 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
610 Samsung SMDK2410 development board (and derivatives).
614 select ARCH_HAS_HOLES_MEMORYMODEL
617 select GENERIC_ALLOCATOR
618 select GENERIC_CLOCKEVENTS
619 select GENERIC_IRQ_CHIP
625 Support for TI's DaVinci platform.
630 select ARCH_HAS_HOLES_MEMORYMODEL
634 select GENERIC_CLOCKEVENTS
635 select GENERIC_IRQ_CHIP
639 select MULTI_IRQ_HANDLER
640 select NEED_MACH_IO_H if PCCARD
641 select NEED_MACH_MEMORY_H
644 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
648 menu "Multiple platform selection"
649 depends on ARCH_MULTIPLATFORM
651 comment "CPU Core family selection"
654 bool "ARMv4 based platforms (FA526)"
655 depends on !ARCH_MULTI_V6_V7
656 select ARCH_MULTI_V4_V5
659 config ARCH_MULTI_V4T
660 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
661 depends on !ARCH_MULTI_V6_V7
662 select ARCH_MULTI_V4_V5
663 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
664 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
665 CPU_ARM925T || CPU_ARM940T)
668 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
669 depends on !ARCH_MULTI_V6_V7
670 select ARCH_MULTI_V4_V5
671 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
672 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
673 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
675 config ARCH_MULTI_V4_V5
679 bool "ARMv6 based platforms (ARM11)"
680 select ARCH_MULTI_V6_V7
684 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
686 select ARCH_MULTI_V6_V7
690 config ARCH_MULTI_V6_V7
692 select MIGHT_HAVE_CACHE_L2X0
694 config ARCH_MULTI_CPU_AUTO
695 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
701 bool "Dummy Virtual Machine"
702 depends on ARCH_MULTI_V7
705 select ARM_GIC_V2M if PCI
707 select ARM_GIC_V3_ITS if PCI
709 select HAVE_ARM_ARCH_TIMER
712 # This is sorted alphabetically by mach-* pathname. However, plat-*
713 # Kconfigs may be included either alphabetically (according to the
714 # plat- suffix) or along side the corresponding mach-* source.
716 source "arch/arm/mach-mvebu/Kconfig"
718 source "arch/arm/mach-alpine/Kconfig"
720 source "arch/arm/mach-artpec/Kconfig"
722 source "arch/arm/mach-asm9260/Kconfig"
724 source "arch/arm/mach-at91/Kconfig"
726 source "arch/arm/mach-axxia/Kconfig"
728 source "arch/arm/mach-bcm/Kconfig"
730 source "arch/arm/mach-berlin/Kconfig"
732 source "arch/arm/mach-clps711x/Kconfig"
734 source "arch/arm/mach-cns3xxx/Kconfig"
736 source "arch/arm/mach-davinci/Kconfig"
738 source "arch/arm/mach-digicolor/Kconfig"
740 source "arch/arm/mach-dove/Kconfig"
742 source "arch/arm/mach-ep93xx/Kconfig"
744 source "arch/arm/mach-footbridge/Kconfig"
746 source "arch/arm/mach-gemini/Kconfig"
748 source "arch/arm/mach-highbank/Kconfig"
750 source "arch/arm/mach-hisi/Kconfig"
752 source "arch/arm/mach-integrator/Kconfig"
754 source "arch/arm/mach-iop32x/Kconfig"
756 source "arch/arm/mach-iop33x/Kconfig"
758 source "arch/arm/mach-iop13xx/Kconfig"
760 source "arch/arm/mach-ixp4xx/Kconfig"
762 source "arch/arm/mach-keystone/Kconfig"
764 source "arch/arm/mach-ks8695/Kconfig"
766 source "arch/arm/mach-meson/Kconfig"
768 source "arch/arm/mach-moxart/Kconfig"
770 source "arch/arm/mach-aspeed/Kconfig"
772 source "arch/arm/mach-mv78xx0/Kconfig"
774 source "arch/arm/mach-imx/Kconfig"
776 source "arch/arm/mach-mediatek/Kconfig"
778 source "arch/arm/mach-mxs/Kconfig"
780 source "arch/arm/mach-netx/Kconfig"
782 source "arch/arm/mach-nomadik/Kconfig"
784 source "arch/arm/mach-nspire/Kconfig"
786 source "arch/arm/plat-omap/Kconfig"
788 source "arch/arm/mach-omap1/Kconfig"
790 source "arch/arm/mach-omap2/Kconfig"
792 source "arch/arm/mach-orion5x/Kconfig"
794 source "arch/arm/mach-picoxcell/Kconfig"
796 source "arch/arm/mach-pxa/Kconfig"
797 source "arch/arm/plat-pxa/Kconfig"
799 source "arch/arm/mach-mmp/Kconfig"
801 source "arch/arm/mach-oxnas/Kconfig"
803 source "arch/arm/mach-qcom/Kconfig"
805 source "arch/arm/mach-realview/Kconfig"
807 source "arch/arm/mach-rockchip/Kconfig"
809 source "arch/arm/mach-sa1100/Kconfig"
811 source "arch/arm/mach-socfpga/Kconfig"
813 source "arch/arm/mach-spear/Kconfig"
815 source "arch/arm/mach-sti/Kconfig"
817 source "arch/arm/mach-s3c24xx/Kconfig"
819 source "arch/arm/mach-s3c64xx/Kconfig"
821 source "arch/arm/mach-s5pv210/Kconfig"
823 source "arch/arm/mach-exynos/Kconfig"
824 source "arch/arm/plat-samsung/Kconfig"
826 source "arch/arm/mach-shmobile/Kconfig"
828 source "arch/arm/mach-sunxi/Kconfig"
830 source "arch/arm/mach-prima2/Kconfig"
832 source "arch/arm/mach-tango/Kconfig"
834 source "arch/arm/mach-tegra/Kconfig"
836 source "arch/arm/mach-u300/Kconfig"
838 source "arch/arm/mach-uniphier/Kconfig"
840 source "arch/arm/mach-ux500/Kconfig"
842 source "arch/arm/mach-versatile/Kconfig"
844 source "arch/arm/mach-vexpress/Kconfig"
845 source "arch/arm/plat-versatile/Kconfig"
847 source "arch/arm/mach-vt8500/Kconfig"
849 source "arch/arm/mach-w90x900/Kconfig"
851 source "arch/arm/mach-zx/Kconfig"
853 source "arch/arm/mach-zynq/Kconfig"
855 # ARMv7-M architecture
857 bool "Energy Micro efm32"
858 depends on ARM_SINGLE_ARMV7M
861 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
865 bool "NXP LPC18xx/LPC43xx"
866 depends on ARM_SINGLE_ARMV7M
867 select ARCH_HAS_RESET_CONTROLLER
869 select CLKSRC_LPC32XX
872 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
873 high performance microcontrollers.
876 bool "STMicrolectronics STM32"
877 depends on ARM_SINGLE_ARMV7M
878 select ARCH_HAS_RESET_CONTROLLER
879 select ARMV7M_SYSTICK
882 select RESET_CONTROLLER
885 Support for STMicroelectronics STM32 processors.
887 config MACH_STM32F429
888 bool "STMicrolectronics STM32F429"
889 depends on ARCH_STM32
892 config MACH_STM32F746
893 bool "STMicrolectronics STM32F746"
894 depends on ARCH_STM32
898 bool "ARM MPS2 platform"
899 depends on ARM_SINGLE_ARMV7M
903 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
904 with a range of available cores like Cortex-M3/M4/M7.
906 Please, note that depends which Application Note is used memory map
907 for the platform may vary, so adjustment of RAM base might be needed.
909 # Definitions to make life easier
915 select GENERIC_CLOCKEVENTS
921 select GENERIC_IRQ_CHIP
924 config PLAT_ORION_LEGACY
931 config PLAT_VERSATILE
934 source "arch/arm/firmware/Kconfig"
936 source arch/arm/mm/Kconfig
939 bool "Enable iWMMXt support"
940 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
941 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
943 Enable support for iWMMXt context switching at run time if
944 running on a CPU that supports it.
946 config MULTI_IRQ_HANDLER
949 Allow each machine to specify it's own IRQ handler at run time.
952 source "arch/arm/Kconfig-nommu"
955 config PJ4B_ERRATA_4742
956 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
957 depends on CPU_PJ4B && MACH_ARMADA_370
960 When coming out of either a Wait for Interrupt (WFI) or a Wait for
961 Event (WFE) IDLE states, a specific timing sensitivity exists between
962 the retiring WFI/WFE instructions and the newly issued subsequent
963 instructions. This sensitivity can result in a CPU hang scenario.
965 The software must insert either a Data Synchronization Barrier (DSB)
966 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
969 config ARM_ERRATA_326103
970 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
973 Executing a SWP instruction to read-only memory does not set bit 11
974 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
975 treat the access as a read, preventing a COW from occurring and
976 causing the faulting task to livelock.
978 config ARM_ERRATA_411920
979 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
980 depends on CPU_V6 || CPU_V6K
982 Invalidation of the Instruction Cache operation can
983 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
984 It does not affect the MPCore. This option enables the ARM Ltd.
985 recommended workaround.
987 config ARM_ERRATA_430973
988 bool "ARM errata: Stale prediction on replaced interworking branch"
991 This option enables the workaround for the 430973 Cortex-A8
992 r1p* erratum. If a code sequence containing an ARM/Thumb
993 interworking branch is replaced with another code sequence at the
994 same virtual address, whether due to self-modifying code or virtual
995 to physical address re-mapping, Cortex-A8 does not recover from the
996 stale interworking branch prediction. This results in Cortex-A8
997 executing the new code sequence in the incorrect ARM or Thumb state.
998 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
999 and also flushes the branch target cache at every context switch.
1000 Note that setting specific bits in the ACTLR register may not be
1001 available in non-secure mode.
1003 config ARM_ERRATA_458693
1004 bool "ARM errata: Processor deadlock when a false hazard is created"
1006 depends on !ARCH_MULTIPLATFORM
1008 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1009 erratum. For very specific sequences of memory operations, it is
1010 possible for a hazard condition intended for a cache line to instead
1011 be incorrectly associated with a different cache line. This false
1012 hazard might then cause a processor deadlock. The workaround enables
1013 the L1 caching of the NEON accesses and disables the PLD instruction
1014 in the ACTLR register. Note that setting specific bits in the ACTLR
1015 register may not be available in non-secure mode.
1017 config ARM_ERRATA_460075
1018 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1020 depends on !ARCH_MULTIPLATFORM
1022 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1023 erratum. Any asynchronous access to the L2 cache may encounter a
1024 situation in which recent store transactions to the L2 cache are lost
1025 and overwritten with stale memory contents from external memory. The
1026 workaround disables the write-allocate mode for the L2 cache via the
1027 ACTLR register. Note that setting specific bits in the ACTLR register
1028 may not be available in non-secure mode.
1030 config ARM_ERRATA_742230
1031 bool "ARM errata: DMB operation may be faulty"
1032 depends on CPU_V7 && SMP
1033 depends on !ARCH_MULTIPLATFORM
1035 This option enables the workaround for the 742230 Cortex-A9
1036 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1037 between two write operations may not ensure the correct visibility
1038 ordering of the two writes. This workaround sets a specific bit in
1039 the diagnostic register of the Cortex-A9 which causes the DMB
1040 instruction to behave as a DSB, ensuring the correct behaviour of
1043 config ARM_ERRATA_742231
1044 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1045 depends on CPU_V7 && SMP
1046 depends on !ARCH_MULTIPLATFORM
1048 This option enables the workaround for the 742231 Cortex-A9
1049 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1050 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1051 accessing some data located in the same cache line, may get corrupted
1052 data due to bad handling of the address hazard when the line gets
1053 replaced from one of the CPUs at the same time as another CPU is
1054 accessing it. This workaround sets specific bits in the diagnostic
1055 register of the Cortex-A9 which reduces the linefill issuing
1056 capabilities of the processor.
1058 config ARM_ERRATA_643719
1059 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1060 depends on CPU_V7 && SMP
1063 This option enables the workaround for the 643719 Cortex-A9 (prior to
1064 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1065 register returns zero when it should return one. The workaround
1066 corrects this value, ensuring cache maintenance operations which use
1067 it behave as intended and avoiding data corruption.
1069 config ARM_ERRATA_720789
1070 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1073 This option enables the workaround for the 720789 Cortex-A9 (prior to
1074 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1075 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1076 As a consequence of this erratum, some TLB entries which should be
1077 invalidated are not, resulting in an incoherency in the system page
1078 tables. The workaround changes the TLB flushing routines to invalidate
1079 entries regardless of the ASID.
1081 config ARM_ERRATA_743622
1082 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1084 depends on !ARCH_MULTIPLATFORM
1086 This option enables the workaround for the 743622 Cortex-A9
1087 (r2p*) erratum. Under very rare conditions, a faulty
1088 optimisation in the Cortex-A9 Store Buffer may lead to data
1089 corruption. This workaround sets a specific bit in the diagnostic
1090 register of the Cortex-A9 which disables the Store Buffer
1091 optimisation, preventing the defect from occurring. This has no
1092 visible impact on the overall performance or power consumption of the
1095 config ARM_ERRATA_751472
1096 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1098 depends on !ARCH_MULTIPLATFORM
1100 This option enables the workaround for the 751472 Cortex-A9 (prior
1101 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1102 completion of a following broadcasted operation if the second
1103 operation is received by a CPU before the ICIALLUIS has completed,
1104 potentially leading to corrupted entries in the cache or TLB.
1106 config ARM_ERRATA_754322
1107 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1110 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1111 r3p*) erratum. A speculative memory access may cause a page table walk
1112 which starts prior to an ASID switch but completes afterwards. This
1113 can populate the micro-TLB with a stale entry which may be hit with
1114 the new ASID. This workaround places two dsb instructions in the mm
1115 switching code so that no page table walks can cross the ASID switch.
1117 config ARM_ERRATA_754327
1118 bool "ARM errata: no automatic Store Buffer drain"
1119 depends on CPU_V7 && SMP
1121 This option enables the workaround for the 754327 Cortex-A9 (prior to
1122 r2p0) erratum. The Store Buffer does not have any automatic draining
1123 mechanism and therefore a livelock may occur if an external agent
1124 continuously polls a memory location waiting to observe an update.
1125 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1126 written polling loops from denying visibility of updates to memory.
1128 config ARM_ERRATA_364296
1129 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1132 This options enables the workaround for the 364296 ARM1136
1133 r0p2 erratum (possible cache data corruption with
1134 hit-under-miss enabled). It sets the undocumented bit 31 in
1135 the auxiliary control register and the FI bit in the control
1136 register, thus disabling hit-under-miss without putting the
1137 processor into full low interrupt latency mode. ARM11MPCore
1140 config ARM_ERRATA_764369
1141 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1142 depends on CPU_V7 && SMP
1144 This option enables the workaround for erratum 764369
1145 affecting Cortex-A9 MPCore with two or more processors (all
1146 current revisions). Under certain timing circumstances, a data
1147 cache line maintenance operation by MVA targeting an Inner
1148 Shareable memory region may fail to proceed up to either the
1149 Point of Coherency or to the Point of Unification of the
1150 system. This workaround adds a DSB instruction before the
1151 relevant cache maintenance functions and sets a specific bit
1152 in the diagnostic control register of the SCU.
1154 config ARM_ERRATA_775420
1155 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1158 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1159 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1160 operation aborts with MMU exception, it might cause the processor
1161 to deadlock. This workaround puts DSB before executing ISB if
1162 an abort may occur on cache maintenance.
1164 config ARM_ERRATA_798181
1165 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1166 depends on CPU_V7 && SMP
1168 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1169 adequately shooting down all use of the old entries. This
1170 option enables the Linux kernel workaround for this erratum
1171 which sends an IPI to the CPUs that are running the same ASID
1172 as the one being invalidated.
1174 config ARM_ERRATA_773022
1175 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1178 This option enables the workaround for the 773022 Cortex-A15
1179 (up to r0p4) erratum. In certain rare sequences of code, the
1180 loop buffer may deliver incorrect instructions. This
1181 workaround disables the loop buffer to avoid the erratum.
1183 config ARM_ERRATA_818325_852422
1184 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1187 This option enables the workaround for:
1188 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1189 instruction might deadlock. Fixed in r0p1.
1190 - Cortex-A12 852422: Execution of a sequence of instructions might
1191 lead to either a data corruption or a CPU deadlock. Not fixed in
1192 any Cortex-A12 cores yet.
1193 This workaround for all both errata involves setting bit[12] of the
1194 Feature Register. This bit disables an optimisation applied to a
1195 sequence of 2 instructions that use opposing condition codes.
1197 config ARM_ERRATA_821420
1198 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1201 This option enables the workaround for the 821420 Cortex-A12
1202 (all revs) erratum. In very rare timing conditions, a sequence
1203 of VMOV to Core registers instructions, for which the second
1204 one is in the shadow of a branch or abort, can lead to a
1205 deadlock when the VMOV instructions are issued out-of-order.
1207 config ARM_ERRATA_825619
1208 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1211 This option enables the workaround for the 825619 Cortex-A12
1212 (all revs) erratum. Within rare timing constraints, executing a
1213 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1214 and Device/Strongly-Ordered loads and stores might cause deadlock
1216 config ARM_ERRATA_852421
1217 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1220 This option enables the workaround for the 852421 Cortex-A17
1221 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1222 execution of a DMB ST instruction might fail to properly order
1223 stores from GroupA and stores from GroupB.
1225 config ARM_ERRATA_852423
1226 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1229 This option enables the workaround for:
1230 - Cortex-A17 852423: Execution of a sequence of instructions might
1231 lead to either a data corruption or a CPU deadlock. Not fixed in
1232 any Cortex-A17 cores yet.
1233 This is identical to Cortex-A12 erratum 852422. It is a separate
1234 config option from the A12 erratum due to the way errata are checked
1239 source "arch/arm/common/Kconfig"
1246 Find out whether you have ISA slots on your motherboard. ISA is the
1247 name of a bus system, i.e. the way the CPU talks to the other stuff
1248 inside your box. Other bus systems are PCI, EISA, MicroChannel
1249 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1250 newer boards don't support it. If you have ISA, say Y, otherwise N.
1252 # Select ISA DMA controller support
1257 # Select ISA DMA interface
1262 bool "PCI support" if MIGHT_HAVE_PCI
1264 Find out whether you have a PCI motherboard. PCI is the name of a
1265 bus system, i.e. the way the CPU talks to the other stuff inside
1266 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1267 VESA. If you have PCI, say Y, otherwise N.
1273 config PCI_DOMAINS_GENERIC
1274 def_bool PCI_DOMAINS
1276 config PCI_NANOENGINE
1277 bool "BSE nanoEngine PCI support"
1278 depends on SA1100_NANOENGINE
1280 Enable PCI on the BSE nanoEngine board.
1285 config PCI_HOST_ITE8152
1287 depends on PCI && MACH_ARMCORE
1291 source "drivers/pci/Kconfig"
1293 source "drivers/pcmcia/Kconfig"
1297 menu "Kernel Features"
1302 This option should be selected by machines which have an SMP-
1305 The only effect of this option is to make the SMP-related
1306 options available to the user for configuration.
1309 bool "Symmetric Multi-Processing"
1310 depends on CPU_V6K || CPU_V7
1311 depends on GENERIC_CLOCKEVENTS
1313 depends on MMU || ARM_MPU
1316 This enables support for systems with more than one CPU. If you have
1317 a system with only one CPU, say N. If you have a system with more
1318 than one CPU, say Y.
1320 If you say N here, the kernel will run on uni- and multiprocessor
1321 machines, but will use only one CPU of a multiprocessor machine. If
1322 you say Y here, the kernel will run on many, but not all,
1323 uniprocessor machines. On a uniprocessor machine, the kernel
1324 will run faster if you say N here.
1326 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1327 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1328 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1330 If you don't know what to do here, say N.
1333 bool "Allow booting SMP kernel on uniprocessor systems"
1334 depends on SMP && !XIP_KERNEL && MMU
1337 SMP kernels contain instructions which fail on non-SMP processors.
1338 Enabling this option allows the kernel to modify itself to make
1339 these instructions safe. Disabling it allows about 1K of space
1342 If you don't know what to do here, say Y.
1344 config ARM_CPU_TOPOLOGY
1345 bool "Support cpu topology definition"
1346 depends on SMP && CPU_V7
1349 Support ARM cpu topology definition. The MPIDR register defines
1350 affinity between processors which is then used to describe the cpu
1351 topology of an ARM System.
1354 bool "Multi-core scheduler support"
1355 depends on ARM_CPU_TOPOLOGY
1357 Multi-core scheduler support improves the CPU scheduler's decision
1358 making when dealing with multi-core CPU chips at a cost of slightly
1359 increased overhead in some places. If unsure say N here.
1362 bool "SMT scheduler support"
1363 depends on ARM_CPU_TOPOLOGY
1365 Improves the CPU scheduler's decision making when dealing with
1366 MultiThreading at a cost of slightly increased overhead in some
1367 places. If unsure say N here.
1372 This option enables support for the ARM system coherency unit
1374 config HAVE_ARM_ARCH_TIMER
1375 bool "Architected timer support"
1377 select ARM_ARCH_TIMER
1378 select GENERIC_CLOCKEVENTS
1380 This option enables support for the ARM architected timer
1384 select CLKSRC_OF if OF
1386 This options enables support for the ARM timer and watchdog unit
1389 bool "Multi-Cluster Power Management"
1390 depends on CPU_V7 && SMP
1392 This option provides the common power management infrastructure
1393 for (multi-)cluster based systems, such as big.LITTLE based
1396 config MCPM_QUAD_CLUSTER
1400 To avoid wasting resources unnecessarily, MCPM only supports up
1401 to 2 clusters by default.
1402 Platforms with 3 or 4 clusters that use MCPM must select this
1403 option to allow the additional clusters to be managed.
1406 bool "big.LITTLE support (Experimental)"
1407 depends on CPU_V7 && SMP
1410 This option enables support selections for the big.LITTLE
1411 system architecture.
1414 bool "big.LITTLE switcher support"
1415 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1418 The big.LITTLE "switcher" provides the core functionality to
1419 transparently handle transition between a cluster of A15's
1420 and a cluster of A7's in a big.LITTLE system.
1422 config BL_SWITCHER_DUMMY_IF
1423 tristate "Simple big.LITTLE switcher user interface"
1424 depends on BL_SWITCHER && DEBUG_KERNEL
1426 This is a simple and dummy char dev interface to control
1427 the big.LITTLE switcher core code. It is meant for
1428 debugging purposes only.
1431 prompt "Memory split"
1435 Select the desired split between kernel and user memory.
1437 If you are not absolutely sure what you are doing, leave this
1441 bool "3G/1G user/kernel split"
1442 config VMSPLIT_3G_OPT
1443 bool "3G/1G user/kernel split (for full 1G low memory)"
1445 bool "2G/2G user/kernel split"
1447 bool "1G/3G user/kernel split"
1452 default PHYS_OFFSET if !MMU
1453 default 0x40000000 if VMSPLIT_1G
1454 default 0x80000000 if VMSPLIT_2G
1455 default 0xB0000000 if VMSPLIT_3G_OPT
1459 int "Maximum number of CPUs (2-32)"
1465 bool "Support for hot-pluggable CPUs"
1468 Say Y here to experiment with turning CPUs off and on. CPUs
1469 can be controlled through /sys/devices/system/cpu.
1472 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1473 depends on HAVE_ARM_SMCCC
1476 Say Y here if you want Linux to communicate with system firmware
1477 implementing the PSCI specification for CPU-centric power
1478 management operations described in ARM document number ARM DEN
1479 0022A ("Power State Coordination Interface System Software on
1482 # The GPIO number here must be sorted by descending number. In case of
1483 # a multiplatform kernel, we just want the highest value required by the
1484 # selected platforms.
1487 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1489 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1490 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1491 default 416 if ARCH_SUNXI
1492 default 392 if ARCH_U8500
1493 default 352 if ARCH_VT8500
1494 default 288 if ARCH_ROCKCHIP
1495 default 264 if MACH_H4700
1498 Maximum number of GPIOs in the system.
1500 If unsure, leave the default value.
1502 source kernel/Kconfig.preempt
1506 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1507 ARCH_S5PV210 || ARCH_EXYNOS4
1508 default 128 if SOC_AT91RM9200
1512 depends on HZ_FIXED = 0
1513 prompt "Timer frequency"
1537 default HZ_FIXED if HZ_FIXED != 0
1538 default 100 if HZ_100
1539 default 200 if HZ_200
1540 default 250 if HZ_250
1541 default 300 if HZ_300
1542 default 500 if HZ_500
1546 def_bool HIGH_RES_TIMERS
1548 config THUMB2_KERNEL
1549 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1550 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1551 default y if CPU_THUMBONLY
1553 select ARM_ASM_UNIFIED
1556 By enabling this option, the kernel will be compiled in
1557 Thumb-2 mode. A compiler/assembler that understand the unified
1558 ARM-Thumb syntax is needed.
1562 config THUMB2_AVOID_R_ARM_THM_JUMP11
1563 bool "Work around buggy Thumb-2 short branch relocations in gas"
1564 depends on THUMB2_KERNEL && MODULES
1567 Various binutils versions can resolve Thumb-2 branches to
1568 locally-defined, preemptible global symbols as short-range "b.n"
1569 branch instructions.
1571 This is a problem, because there's no guarantee the final
1572 destination of the symbol, or any candidate locations for a
1573 trampoline, are within range of the branch. For this reason, the
1574 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1575 relocation in modules at all, and it makes little sense to add
1578 The symptom is that the kernel fails with an "unsupported
1579 relocation" error when loading some modules.
1581 Until fixed tools are available, passing
1582 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1583 code which hits this problem, at the cost of a bit of extra runtime
1584 stack usage in some cases.
1586 The problem is described in more detail at:
1587 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1589 Only Thumb-2 kernels are affected.
1591 Unless you are sure your tools don't have this problem, say Y.
1593 config ARM_ASM_UNIFIED
1596 config ARM_PATCH_IDIV
1597 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1598 depends on CPU_32v7 && !XIP_KERNEL
1601 The ARM compiler inserts calls to __aeabi_idiv() and
1602 __aeabi_uidiv() when it needs to perform division on signed
1603 and unsigned integers. Some v7 CPUs have support for the sdiv
1604 and udiv instructions that can be used to implement those
1607 Enabling this option allows the kernel to modify itself to
1608 replace the first two instructions of these library functions
1609 with the sdiv or udiv plus "bx lr" instructions when the CPU
1610 it is running on supports them. Typically this will be faster
1611 and less power intensive than running the original library
1612 code to do integer division.
1615 bool "Use the ARM EABI to compile the kernel"
1617 This option allows for the kernel to be compiled using the latest
1618 ARM ABI (aka EABI). This is only useful if you are using a user
1619 space environment that is also compiled with EABI.
1621 Since there are major incompatibilities between the legacy ABI and
1622 EABI, especially with regard to structure member alignment, this
1623 option also changes the kernel syscall calling convention to
1624 disambiguate both ABIs and allow for backward compatibility support
1625 (selected with CONFIG_OABI_COMPAT).
1627 To use this you need GCC version 4.0.0 or later.
1630 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1631 depends on AEABI && !THUMB2_KERNEL
1633 This option preserves the old syscall interface along with the
1634 new (ARM EABI) one. It also provides a compatibility layer to
1635 intercept syscalls that have structure arguments which layout
1636 in memory differs between the legacy ABI and the new ARM EABI
1637 (only for non "thumb" binaries). This option adds a tiny
1638 overhead to all syscalls and produces a slightly larger kernel.
1640 The seccomp filter system will not be available when this is
1641 selected, since there is no way yet to sensibly distinguish
1642 between calling conventions during filtering.
1644 If you know you'll be using only pure EABI user space then you
1645 can say N here. If this option is not selected and you attempt
1646 to execute a legacy ABI binary then the result will be
1647 UNPREDICTABLE (in fact it can be predicted that it won't work
1648 at all). If in doubt say N.
1650 config ARCH_HAS_HOLES_MEMORYMODEL
1653 config ARCH_SPARSEMEM_ENABLE
1656 config ARCH_SPARSEMEM_DEFAULT
1657 def_bool ARCH_SPARSEMEM_ENABLE
1659 config ARCH_SELECT_MEMORY_MODEL
1660 def_bool ARCH_SPARSEMEM_ENABLE
1662 config HAVE_ARCH_PFN_VALID
1663 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1665 config HAVE_GENERIC_RCU_GUP
1670 bool "High Memory Support"
1673 The address space of ARM processors is only 4 Gigabytes large
1674 and it has to accommodate user address space, kernel address
1675 space as well as some memory mapped IO. That means that, if you
1676 have a large amount of physical memory and/or IO, not all of the
1677 memory can be "permanently mapped" by the kernel. The physical
1678 memory that is not permanently mapped is called "high memory".
1680 Depending on the selected kernel/user memory split, minimum
1681 vmalloc space and actual amount of RAM, you may not need this
1682 option which should result in a slightly faster kernel.
1687 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1691 The VM uses one page of physical memory for each page table.
1692 For systems with a lot of processes, this can use a lot of
1693 precious low memory, eventually leading to low memory being
1694 consumed by page tables. Setting this option will allow
1695 user-space 2nd level page tables to reside in high memory.
1697 config CPU_SW_DOMAIN_PAN
1698 bool "Enable use of CPU domains to implement privileged no-access"
1699 depends on MMU && !ARM_LPAE
1702 Increase kernel security by ensuring that normal kernel accesses
1703 are unable to access userspace addresses. This can help prevent
1704 use-after-free bugs becoming an exploitable privilege escalation
1705 by ensuring that magic values (such as LIST_POISON) will always
1706 fault when dereferenced.
1708 CPUs with low-vector mappings use a best-efforts implementation.
1709 Their lower 1MB needs to remain accessible for the vectors, but
1710 the remainder of userspace will become appropriately inaccessible.
1712 config HW_PERF_EVENTS
1716 config SYS_SUPPORTS_HUGETLBFS
1720 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1724 config ARCH_WANT_GENERAL_HUGETLB
1727 config ARM_MODULE_PLTS
1728 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1731 Allocate PLTs when loading modules so that jumps and calls whose
1732 targets are too far away for their relative offsets to be encoded
1733 in the instructions themselves can be bounced via veneers in the
1734 module's PLT. This allows modules to be allocated in the generic
1735 vmalloc area after the dedicated module memory area has been
1736 exhausted. The modules will use slightly more memory, but after
1737 rounding up to page size, the actual memory footprint is usually
1740 Say y if you are getting out of memory errors while loading modules
1744 config FORCE_MAX_ZONEORDER
1745 int "Maximum zone order"
1746 default "12" if SOC_AM33XX
1747 default "9" if SA1111 || ARCH_EFM32
1750 The kernel memory allocator divides physically contiguous memory
1751 blocks into "zones", where each zone is a power of two number of
1752 pages. This option selects the largest power of two that the kernel
1753 keeps in the memory allocator. If you need to allocate very large
1754 blocks of physically contiguous memory, then you may need to
1755 increase this value.
1757 This config option is actually maximum order plus one. For example,
1758 a value of 11 means that the largest free memory block is 2^10 pages.
1760 config ALIGNMENT_TRAP
1762 depends on CPU_CP15_MMU
1763 default y if !ARCH_EBSA110
1764 select HAVE_PROC_CPU if PROC_FS
1766 ARM processors cannot fetch/store information which is not
1767 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1768 address divisible by 4. On 32-bit ARM processors, these non-aligned
1769 fetch/store instructions will be emulated in software if you say
1770 here, which has a severe performance impact. This is necessary for
1771 correct operation of some network protocols. With an IP-only
1772 configuration it is safe to say N, otherwise say Y.
1774 config UACCESS_WITH_MEMCPY
1775 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1777 default y if CPU_FEROCEON
1779 Implement faster copy_to_user and clear_user methods for CPU
1780 cores where a 8-word STM instruction give significantly higher
1781 memory write throughput than a sequence of individual 32bit stores.
1783 A possible side effect is a slight increase in scheduling latency
1784 between threads sharing the same address space if they invoke
1785 such copy operations with large buffers.
1787 However, if the CPU data cache is using a write-allocate mode,
1788 this option is unlikely to provide any performance gain.
1792 prompt "Enable seccomp to safely compute untrusted bytecode"
1794 This kernel feature is useful for number crunching applications
1795 that may need to compute untrusted bytecode during their
1796 execution. By using pipes or other transports made available to
1797 the process as file descriptors supporting the read/write
1798 syscalls, it's possible to isolate those applications in
1799 their own address space using seccomp. Once seccomp is
1800 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1801 and the task is only allowed to execute a few safe syscalls
1802 defined by each seccomp mode.
1811 bool "Enable paravirtualization code"
1813 This changes the kernel so it can modify itself when it is run
1814 under a hypervisor, potentially improving performance significantly
1815 over full virtualization.
1817 config PARAVIRT_TIME_ACCOUNTING
1818 bool "Paravirtual steal time accounting"
1822 Select this option to enable fine granularity task steal time
1823 accounting. Time spent executing other tasks in parallel with
1824 the current vCPU is discounted from the vCPU power. To account for
1825 that, there can be a small performance impact.
1827 If in doubt, say N here.
1834 bool "Xen guest support on ARM"
1835 depends on ARM && AEABI && OF
1836 depends on CPU_V7 && !CPU_V6
1837 depends on !GENERIC_ATOMIC64
1839 select ARCH_DMA_ADDR_T_64BIT
1844 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1851 bool "Flattened Device Tree support"
1855 Include support for flattened device tree machine descriptions.
1858 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1861 This is the traditional way of passing data to the kernel at boot
1862 time. If you are solely relying on the flattened device tree (or
1863 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1864 to remove ATAGS support from your kernel binary. If unsure,
1867 config DEPRECATED_PARAM_STRUCT
1868 bool "Provide old way to pass kernel parameters"
1871 This was deprecated in 2001 and announced to live on for 5 years.
1872 Some old boot loaders still use this way.
1874 # Compressed boot loader in ROM. Yes, we really want to ask about
1875 # TEXT and BSS so we preserve their values in the config files.
1876 config ZBOOT_ROM_TEXT
1877 hex "Compressed ROM boot loader base address"
1880 The physical address at which the ROM-able zImage is to be
1881 placed in the target. Platforms which normally make use of
1882 ROM-able zImage formats normally set this to a suitable
1883 value in their defconfig file.
1885 If ZBOOT_ROM is not enabled, this has no effect.
1887 config ZBOOT_ROM_BSS
1888 hex "Compressed ROM boot loader BSS address"
1891 The base address of an area of read/write memory in the target
1892 for the ROM-able zImage which must be available while the
1893 decompressor is running. It must be large enough to hold the
1894 entire decompressed kernel plus an additional 128 KiB.
1895 Platforms which normally make use of ROM-able zImage formats
1896 normally set this to a suitable value in their defconfig file.
1898 If ZBOOT_ROM is not enabled, this has no effect.
1901 bool "Compressed boot loader in ROM/flash"
1902 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1903 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1905 Say Y here if you intend to execute your compressed kernel image
1906 (zImage) directly from ROM or flash. If unsure, say N.
1908 config ARM_APPENDED_DTB
1909 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1912 With this option, the boot code will look for a device tree binary
1913 (DTB) appended to zImage
1914 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1916 This is meant as a backward compatibility convenience for those
1917 systems with a bootloader that can't be upgraded to accommodate
1918 the documented boot protocol using a device tree.
1920 Beware that there is very little in terms of protection against
1921 this option being confused by leftover garbage in memory that might
1922 look like a DTB header after a reboot if no actual DTB is appended
1923 to zImage. Do not leave this option active in a production kernel
1924 if you don't intend to always append a DTB. Proper passing of the
1925 location into r2 of a bootloader provided DTB is always preferable
1928 config ARM_ATAG_DTB_COMPAT
1929 bool "Supplement the appended DTB with traditional ATAG information"
1930 depends on ARM_APPENDED_DTB
1932 Some old bootloaders can't be updated to a DTB capable one, yet
1933 they provide ATAGs with memory configuration, the ramdisk address,
1934 the kernel cmdline string, etc. Such information is dynamically
1935 provided by the bootloader and can't always be stored in a static
1936 DTB. To allow a device tree enabled kernel to be used with such
1937 bootloaders, this option allows zImage to extract the information
1938 from the ATAG list and store it at run time into the appended DTB.
1941 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1942 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1944 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1945 bool "Use bootloader kernel arguments if available"
1947 Uses the command-line options passed by the boot loader instead of
1948 the device tree bootargs property. If the boot loader doesn't provide
1949 any, the device tree bootargs property will be used.
1951 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1952 bool "Extend with bootloader kernel arguments"
1954 The command-line arguments provided by the boot loader will be
1955 appended to the the device tree bootargs property.
1960 string "Default kernel command string"
1963 On some architectures (EBSA110 and CATS), there is currently no way
1964 for the boot loader to pass arguments to the kernel. For these
1965 architectures, you should supply some command-line options at build
1966 time by entering them here. As a minimum, you should specify the
1967 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1970 prompt "Kernel command line type" if CMDLINE != ""
1971 default CMDLINE_FROM_BOOTLOADER
1974 config CMDLINE_FROM_BOOTLOADER
1975 bool "Use bootloader kernel arguments if available"
1977 Uses the command-line options passed by the boot loader. If
1978 the boot loader doesn't provide any, the default kernel command
1979 string provided in CMDLINE will be used.
1981 config CMDLINE_EXTEND
1982 bool "Extend bootloader kernel arguments"
1984 The command-line arguments provided by the boot loader will be
1985 appended to the default kernel command string.
1987 config CMDLINE_FORCE
1988 bool "Always use the default kernel command string"
1990 Always use the default kernel command string, even if the boot
1991 loader passes other arguments to the kernel.
1992 This is useful if you cannot or don't want to change the
1993 command-line options your boot loader passes to the kernel.
1997 bool "Kernel Execute-In-Place from ROM"
1998 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2000 Execute-In-Place allows the kernel to run from non-volatile storage
2001 directly addressable by the CPU, such as NOR flash. This saves RAM
2002 space since the text section of the kernel is not loaded from flash
2003 to RAM. Read-write sections, such as the data section and stack,
2004 are still copied to RAM. The XIP kernel is not compressed since
2005 it has to run directly from flash, so it will take more space to
2006 store it. The flash address used to link the kernel object files,
2007 and for storing it, is configuration dependent. Therefore, if you
2008 say Y here, you must know the proper physical address where to
2009 store the kernel image depending on your own flash memory usage.
2011 Also note that the make target becomes "make xipImage" rather than
2012 "make zImage" or "make Image". The final kernel binary to put in
2013 ROM memory will be arch/arm/boot/xipImage.
2017 config XIP_PHYS_ADDR
2018 hex "XIP Kernel Physical Location"
2019 depends on XIP_KERNEL
2020 default "0x00080000"
2022 This is the physical address in your flash memory the kernel will
2023 be linked for and stored to. This address is dependent on your
2027 bool "Kexec system call (EXPERIMENTAL)"
2028 depends on (!SMP || PM_SLEEP_SMP)
2032 kexec is a system call that implements the ability to shutdown your
2033 current kernel, and to start another kernel. It is like a reboot
2034 but it is independent of the system firmware. And like a reboot
2035 you can start any kernel with it, not just Linux.
2037 It is an ongoing process to be certain the hardware in a machine
2038 is properly shutdown, so do not be surprised if this code does not
2039 initially work for you.
2042 bool "Export atags in procfs"
2043 depends on ATAGS && KEXEC
2046 Should the atags used to boot the kernel be exported in an "atags"
2047 file in procfs. Useful with kexec.
2050 bool "Build kdump crash kernel (EXPERIMENTAL)"
2052 Generate crash dump after being started by kexec. This should
2053 be normally only set in special crash dump kernels which are
2054 loaded in the main kernel with kexec-tools into a specially
2055 reserved region and then later executed after a crash by
2056 kdump/kexec. The crash dump kernel must be compiled to a
2057 memory address not used by the main kernel
2059 For more details see Documentation/kdump/kdump.txt
2061 config AUTO_ZRELADDR
2062 bool "Auto calculation of the decompressed kernel image address"
2064 ZRELADDR is the physical address where the decompressed kernel
2065 image will be placed. If AUTO_ZRELADDR is selected, the address
2066 will be determined at run-time by masking the current IP with
2067 0xf8000000. This assumes the zImage being placed in the first 128MB
2068 from start of memory.
2074 bool "UEFI runtime support"
2075 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2077 select EFI_PARAMS_FROM_FDT
2080 select EFI_RUNTIME_WRAPPERS
2082 This option provides support for runtime services provided
2083 by UEFI firmware (such as non-volatile variables, realtime
2084 clock, and platform reset). A UEFI stub is also provided to
2085 allow the kernel to be booted as an EFI application. This
2086 is only useful for kernels that may run on systems that have
2091 menu "CPU Power Management"
2093 source "drivers/cpufreq/Kconfig"
2095 source "drivers/cpuidle/Kconfig"
2099 menu "Floating point emulation"
2101 comment "At least one emulation must be selected"
2104 bool "NWFPE math emulation"
2105 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2107 Say Y to include the NWFPE floating point emulator in the kernel.
2108 This is necessary to run most binaries. Linux does not currently
2109 support floating point hardware so you need to say Y here even if
2110 your machine has an FPA or floating point co-processor podule.
2112 You may say N here if you are going to load the Acorn FPEmulator
2113 early in the bootup.
2116 bool "Support extended precision"
2117 depends on FPE_NWFPE
2119 Say Y to include 80-bit support in the kernel floating-point
2120 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2121 Note that gcc does not generate 80-bit operations by default,
2122 so in most cases this option only enlarges the size of the
2123 floating point emulator without any good reason.
2125 You almost surely want to say N here.
2128 bool "FastFPE math emulation (EXPERIMENTAL)"
2129 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2131 Say Y here to include the FAST floating point emulator in the kernel.
2132 This is an experimental much faster emulator which now also has full
2133 precision for the mantissa. It does not support any exceptions.
2134 It is very simple, and approximately 3-6 times faster than NWFPE.
2136 It should be sufficient for most programs. It may be not suitable
2137 for scientific calculations, but you have to check this for yourself.
2138 If you do not feel you need a faster FP emulation you should better
2142 bool "VFP-format floating point maths"
2143 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2145 Say Y to include VFP support code in the kernel. This is needed
2146 if your hardware includes a VFP unit.
2148 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2149 release notes and additional status information.
2151 Say N if your target does not have VFP hardware.
2159 bool "Advanced SIMD (NEON) Extension support"
2160 depends on VFPv3 && CPU_V7
2162 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2165 config KERNEL_MODE_NEON
2166 bool "Support for NEON in kernel mode"
2167 depends on NEON && AEABI
2169 Say Y to include support for NEON in kernel mode.
2173 menu "Userspace binary formats"
2175 source "fs/Kconfig.binfmt"
2179 menu "Power management options"
2181 source "kernel/power/Kconfig"
2183 config ARCH_SUSPEND_POSSIBLE
2184 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2185 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2188 config ARM_CPU_SUSPEND
2189 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2190 depends on ARCH_SUSPEND_POSSIBLE
2192 config ARCH_HIBERNATION_POSSIBLE
2195 default y if ARCH_SUSPEND_POSSIBLE
2199 source "net/Kconfig"
2201 source "drivers/Kconfig"
2203 source "drivers/firmware/Kconfig"
2207 source "arch/arm/Kconfig.debug"
2209 source "security/Kconfig"
2211 source "crypto/Kconfig"
2213 source "arch/arm/crypto/Kconfig"
2216 source "lib/Kconfig"
2218 source "arch/arm/kvm/Kconfig"