4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_GPIO_H
208 Select this when mach/gpio.h is required to provide special
209 definitions for this platform. The need for mach/gpio.h should
210 be avoided when possible.
212 config NEED_MACH_IO_H
215 Select this when mach/io.h is required to provide special
216 definitions for this platform. The need for mach/io.h should
217 be avoided when possible.
219 config NEED_MACH_MEMORY_H
222 Select this when mach/memory.h is required to provide special
223 definitions for this platform. The need for mach/memory.h should
224 be avoided when possible.
227 hex "Physical address of main memory" if MMU
228 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
229 default DRAM_BASE if !MMU
231 Please provide the physical address corresponding to the
232 location of main memory in your system.
238 source "init/Kconfig"
240 source "kernel/Kconfig.freezer"
245 bool "MMU-based Paged Memory Management Support"
248 Select if you want MMU-based virtualised addressing space
249 support by paged memory management. If unsure, say 'Y'.
252 # The "ARM system type" choice list is ordered alphabetically by option
253 # text. Please add new entries in the option alphabetic order.
256 prompt "ARM system type"
257 default ARCH_MULTIPLATFORM
259 config ARCH_MULTIPLATFORM
260 bool "Allow multiple platforms to be selected"
261 select ARM_PATCH_PHYS_VIRT
264 select MULTI_IRQ_HANDLER
269 config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
272 select ARCH_HAS_CPUFREQ
274 select COMMON_CLK_VERSATILE
277 select GENERIC_CLOCKEVENTS
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_FPGA_IRQ
280 select NEED_MACH_MEMORY_H
282 select MULTI_IRQ_HANDLER
284 Support for ARM's Integrator platform.
287 bool "ARM Ltd. RealView family"
290 select COMMON_CLK_VERSATILE
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select ARM_TIMER_SP804
297 select GPIO_PL061 if GPIOLIB
298 select NEED_MACH_MEMORY_H
300 This enables support for ARM Ltd RealView boards.
302 config ARCH_VERSATILE
303 bool "ARM Ltd. Versatile family"
307 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLOCK
313 select PLAT_VERSATILE_CLCD
314 select PLAT_VERSATILE_FPGA_IRQ
315 select ARM_TIMER_SP804
317 This enables support for ARM Ltd Versatile board.
321 select ARCH_REQUIRE_GPIOLIB
325 select NEED_MACH_GPIO_H
326 select NEED_MACH_IO_H if PCCARD
328 This enables support for systems based on Atmel
329 AT91RM9200 and AT91SAM9* processors.
332 bool "Broadcom BCM2835 family"
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 select ARM_ERRATA_411920
336 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select MULTI_IRQ_HANDLER
345 This enables support for the Broadcom BCM2835 SoC. This SoC is
346 use in the Raspberry Pi, and Roku 2 devices.
349 bool "Broadcom BCMRING"
353 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
356 select ARCH_WANT_OPTIONAL_GPIOLIB
358 Support for Broadcom's BCMRing platform.
361 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
363 select ARCH_USES_GETTIMEOFFSET
364 select NEED_MACH_MEMORY_H
366 Support for Cirrus Logic 711x/721x/731x based boards.
369 bool "Cavium Networks CNS3XXX family"
371 select GENERIC_CLOCKEVENTS
373 select MIGHT_HAVE_CACHE_L2X0
374 select MIGHT_HAVE_PCI
375 select PCI_DOMAINS if PCI
377 Support for Cavium Networks CNS3XXX platform.
380 bool "Cortina Systems Gemini"
382 select ARCH_REQUIRE_GPIOLIB
383 select ARCH_USES_GETTIMEOFFSET
385 Support for the Cortina Systems Gemini family SoCs
390 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
393 select GENERIC_IRQ_CHIP
394 select MIGHT_HAVE_CACHE_L2X0
399 Support for CSR SiRFprimaII/Marco/Polo platforms
406 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
421 select ARCH_REQUIRE_GPIOLIB
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXC/iMX-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_IRQ_CHIP
447 select MULTI_IRQ_HANDLER
451 Support for Freescale MXC/iMX-based family of processors
454 bool "Freescale MXS-based"
455 select GENERIC_CLOCKEVENTS
456 select ARCH_REQUIRE_GPIOLIB
460 select HAVE_CLK_PREPARE
464 Support for Freescale MXS-based family of processors
467 bool "Hilscher NetX based"
471 select GENERIC_CLOCKEVENTS
473 This enables support for systems based on the Hilscher NetX Soc
476 bool "Hynix HMS720x-based"
479 select ARCH_USES_GETTIMEOFFSET
481 This enables support for systems based on the Hynix HMS720x
489 select ARCH_SUPPORTS_MSI
491 select NEED_MACH_MEMORY_H
492 select NEED_RET_TO_USER
494 Support for Intel's IOP13XX (XScale) family of processors.
500 select NEED_MACH_GPIO_H
501 select NEED_MACH_IO_H
502 select NEED_RET_TO_USER
505 select ARCH_REQUIRE_GPIOLIB
507 Support for Intel's 80219 and IOP32X (XScale) family of
514 select NEED_MACH_GPIO_H
515 select NEED_MACH_IO_H
516 select NEED_RET_TO_USER
519 select ARCH_REQUIRE_GPIOLIB
521 Support for Intel's IOP33X (XScale) family of processors.
526 select ARCH_HAS_DMA_SET_COHERENT_MASK
529 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
531 select MIGHT_HAVE_PCI
532 select NEED_MACH_IO_H
533 select DMABOUNCE if PCI
535 Support for Intel's IXP4XX (XScale) family of processors.
540 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
542 select MIGHT_HAVE_PCI
544 select USB_ARCH_HAS_EHCI
546 Support for the Marvell Dove SoC 88AP510
549 bool "Marvell Kirkwood"
552 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281.
563 select ARCH_REQUIRE_GPIOLIB
566 select USB_ARCH_HAS_OHCI
568 select GENERIC_CLOCKEVENTS
572 Support for the NXP LPC32XX family of processors
575 bool "Marvell MV78xx0"
578 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
582 Support for the following Marvell MV78xx0 series SoCs:
590 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
594 Support for the following Marvell Orion 5x series SoCs:
595 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
596 Orion-2 (5281), Orion-1-90 (6183).
599 bool "Marvell PXA168/910/MMP2"
601 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
608 select GENERIC_ALLOCATOR
609 select NEED_MACH_GPIO_H
611 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
614 bool "Micrel/Kendin KS8695"
616 select ARCH_REQUIRE_GPIOLIB
617 select NEED_MACH_MEMORY_H
619 select GENERIC_CLOCKEVENTS
621 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
622 System-on-Chip devices.
625 bool "Nuvoton W90X900 CPU"
627 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
632 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
633 At present, the w90x900 has been renamed nuc900, regarding
634 the ARM series product line, you can login the following
635 link address to know more.
637 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
638 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
644 select GENERIC_CLOCKEVENTS
648 select MIGHT_HAVE_CACHE_L2X0
649 select ARCH_HAS_CPUFREQ
653 This enables support for NVIDIA Tegra based systems (Tegra APX,
654 Tegra 6xx and Tegra 2 series).
657 bool "PXA2xx/PXA3xx-based"
660 select ARCH_HAS_CPUFREQ
663 select ARCH_REQUIRE_GPIOLIB
664 select GENERIC_CLOCKEVENTS
669 select MULTI_IRQ_HANDLER
670 select ARM_CPU_SUSPEND if PM
672 select NEED_MACH_GPIO_H
674 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
679 select GENERIC_CLOCKEVENTS
680 select ARCH_REQUIRE_GPIOLIB
683 Support for Qualcomm MSM/QSD based systems. This runs on the
684 apps processor of the MSM/QSD and depends on a shared memory
685 interface to the modem processor which runs the baseband
686 stack and controls some vital subsystems
687 (clock and power control, etc).
690 bool "Renesas SH-Mobile / R-Mobile"
693 select HAVE_MACH_CLKDEV
695 select GENERIC_CLOCKEVENTS
696 select MIGHT_HAVE_CACHE_L2X0
699 select MULTI_IRQ_HANDLER
700 select PM_GENERIC_DOMAINS if PM
701 select NEED_MACH_MEMORY_H
703 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
709 select ARCH_MAY_HAVE_PC_FDC
710 select HAVE_PATA_PLATFORM
713 select ARCH_SPARSEMEM_ENABLE
714 select ARCH_USES_GETTIMEOFFSET
716 select NEED_MACH_IO_H
717 select NEED_MACH_MEMORY_H
719 On the Acorn Risc-PC, Linux can support the internal IDE disk and
720 CD-ROM interface, serial and parallel port, and the floppy drive.
727 select ARCH_SPARSEMEM_ENABLE
729 select ARCH_HAS_CPUFREQ
731 select GENERIC_CLOCKEVENTS
733 select ARCH_REQUIRE_GPIOLIB
735 select NEED_MACH_GPIO_H
736 select NEED_MACH_MEMORY_H
739 Support for StrongARM 11x0 based boards.
742 bool "Samsung S3C24XX SoCs"
744 select ARCH_HAS_CPUFREQ
747 select ARCH_USES_GETTIMEOFFSET
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C_RTC if RTC_CLASS
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select NEED_MACH_GPIO_H
752 select NEED_MACH_IO_H
754 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
755 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
756 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
757 Samsung SMDK2410 development board (and derivatives).
760 bool "Samsung S3C64XX"
768 select ARCH_USES_GETTIMEOFFSET
769 select ARCH_HAS_CPUFREQ
770 select ARCH_REQUIRE_GPIOLIB
771 select SAMSUNG_CLKSRC
772 select SAMSUNG_IRQ_VIC_TIMER
773 select S3C_GPIO_TRACK
775 select USB_ARCH_HAS_OHCI
776 select SAMSUNG_GPIOLIB_4BIT
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select NEED_MACH_GPIO_H
781 Samsung S3C64XX series based systems
784 bool "Samsung S5P6440 S5P6450"
790 select HAVE_S3C2410_WATCHDOG if WATCHDOG
791 select GENERIC_CLOCKEVENTS
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C_RTC if RTC_CLASS
794 select NEED_MACH_GPIO_H
796 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
800 bool "Samsung S5PC100"
805 select ARCH_USES_GETTIMEOFFSET
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C_RTC if RTC_CLASS
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select NEED_MACH_GPIO_H
811 Samsung S5PC100 series based systems
814 bool "Samsung S5PV210/S5PC110"
816 select ARCH_SPARSEMEM_ENABLE
817 select ARCH_HAS_HOLES_MEMORYMODEL
822 select ARCH_HAS_CPUFREQ
823 select GENERIC_CLOCKEVENTS
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C_RTC if RTC_CLASS
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select NEED_MACH_GPIO_H
828 select NEED_MACH_MEMORY_H
830 Samsung S5PV210/S5PC110 series based systems
833 bool "SAMSUNG EXYNOS"
835 select ARCH_SPARSEMEM_ENABLE
836 select ARCH_HAS_HOLES_MEMORYMODEL
840 select ARCH_HAS_CPUFREQ
841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C_RTC if RTC_CLASS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select NEED_MACH_GPIO_H
846 select NEED_MACH_MEMORY_H
848 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
857 select ARCH_USES_GETTIMEOFFSET
858 select NEED_MACH_MEMORY_H
860 Support for the StrongARM based Digital DNARD machine, also known
861 as "Shark" (<http://www.shark-linux.de/shark.html>).
864 bool "ST-Ericsson U300 Series"
870 select ARM_PATCH_PHYS_VIRT
872 select GENERIC_CLOCKEVENTS
876 select ARCH_REQUIRE_GPIOLIB
879 Support for ST-Ericsson U300 series mobile platforms.
882 bool "ST-Ericsson U8500 Series"
886 select GENERIC_CLOCKEVENTS
888 select ARCH_REQUIRE_GPIOLIB
889 select ARCH_HAS_CPUFREQ
891 select MIGHT_HAVE_CACHE_L2X0
893 Support for ST-Ericsson's Ux500 architecture
896 bool "STMicroelectronics Nomadik"
901 select GENERIC_CLOCKEVENTS
903 select MIGHT_HAVE_CACHE_L2X0
904 select ARCH_REQUIRE_GPIOLIB
906 Support for the Nomadik platform by ST-Ericsson
910 select GENERIC_CLOCKEVENTS
911 select ARCH_REQUIRE_GPIOLIB
915 select GENERIC_ALLOCATOR
916 select GENERIC_IRQ_CHIP
917 select ARCH_HAS_HOLES_MEMORYMODEL
918 select NEED_MACH_GPIO_H
920 Support for TI's DaVinci platform.
926 select ARCH_REQUIRE_GPIOLIB
927 select ARCH_HAS_CPUFREQ
929 select GENERIC_CLOCKEVENTS
930 select ARCH_HAS_HOLES_MEMORYMODEL
931 select NEED_MACH_GPIO_H
933 Support for TI's OMAP platform (OMAP1/2/3/4).
938 select ARCH_REQUIRE_GPIOLIB
942 select GENERIC_CLOCKEVENTS
945 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
948 bool "VIA/WonderMedia 85xx"
951 select ARCH_HAS_CPUFREQ
952 select GENERIC_CLOCKEVENTS
953 select ARCH_REQUIRE_GPIOLIB
955 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
958 bool "Xilinx Zynq ARM Cortex A9 Platform"
960 select GENERIC_CLOCKEVENTS
965 select MIGHT_HAVE_CACHE_L2X0
968 Support for Xilinx Zynq ARM Cortex A9 Platform
971 menu "Multiple platform selection"
972 depends on ARCH_MULTIPLATFORM
974 comment "CPU Core family selection"
977 bool "ARMv4 based platforms (FA526, StrongARM)"
978 select ARCH_MULTI_V4_V5
979 depends on !ARCH_MULTI_V6_V7
981 config ARCH_MULTI_V4T
982 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
983 select ARCH_MULTI_V4_V5
984 depends on !ARCH_MULTI_V6_V7
987 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
988 select ARCH_MULTI_V4_V5
989 depends on !ARCH_MULTI_V6_V7
991 config ARCH_MULTI_V4_V5
995 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
997 select ARCH_MULTI_V6_V7
1000 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1002 select ARCH_VEXPRESS
1004 select ARCH_MULTI_V6_V7
1006 config ARCH_MULTI_V6_V7
1009 config ARCH_MULTI_CPU_AUTO
1010 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1011 select ARCH_MULTI_V5
1016 # This is sorted alphabetically by mach-* pathname. However, plat-*
1017 # Kconfigs may be included either alphabetically (according to the
1018 # plat- suffix) or along side the corresponding mach-* source.
1020 source "arch/arm/mach-mvebu/Kconfig"
1022 source "arch/arm/mach-at91/Kconfig"
1024 source "arch/arm/mach-bcmring/Kconfig"
1026 source "arch/arm/mach-clps711x/Kconfig"
1028 source "arch/arm/mach-cns3xxx/Kconfig"
1030 source "arch/arm/mach-davinci/Kconfig"
1032 source "arch/arm/mach-dove/Kconfig"
1034 source "arch/arm/mach-ep93xx/Kconfig"
1036 source "arch/arm/mach-footbridge/Kconfig"
1038 source "arch/arm/mach-gemini/Kconfig"
1040 source "arch/arm/mach-h720x/Kconfig"
1042 source "arch/arm/mach-highbank/Kconfig"
1044 source "arch/arm/mach-integrator/Kconfig"
1046 source "arch/arm/mach-iop32x/Kconfig"
1048 source "arch/arm/mach-iop33x/Kconfig"
1050 source "arch/arm/mach-iop13xx/Kconfig"
1052 source "arch/arm/mach-ixp4xx/Kconfig"
1054 source "arch/arm/mach-kirkwood/Kconfig"
1056 source "arch/arm/mach-ks8695/Kconfig"
1058 source "arch/arm/mach-msm/Kconfig"
1060 source "arch/arm/mach-mv78xx0/Kconfig"
1062 source "arch/arm/plat-mxc/Kconfig"
1064 source "arch/arm/mach-mxs/Kconfig"
1066 source "arch/arm/mach-netx/Kconfig"
1068 source "arch/arm/mach-nomadik/Kconfig"
1069 source "arch/arm/plat-nomadik/Kconfig"
1071 source "arch/arm/plat-omap/Kconfig"
1073 source "arch/arm/mach-omap1/Kconfig"
1075 source "arch/arm/mach-omap2/Kconfig"
1077 source "arch/arm/mach-orion5x/Kconfig"
1079 source "arch/arm/mach-picoxcell/Kconfig"
1081 source "arch/arm/mach-pxa/Kconfig"
1082 source "arch/arm/plat-pxa/Kconfig"
1084 source "arch/arm/mach-mmp/Kconfig"
1086 source "arch/arm/mach-realview/Kconfig"
1088 source "arch/arm/mach-sa1100/Kconfig"
1090 source "arch/arm/plat-samsung/Kconfig"
1091 source "arch/arm/plat-s3c24xx/Kconfig"
1093 source "arch/arm/mach-socfpga/Kconfig"
1095 source "arch/arm/plat-spear/Kconfig"
1097 source "arch/arm/mach-s3c24xx/Kconfig"
1099 source "arch/arm/mach-s3c2412/Kconfig"
1100 source "arch/arm/mach-s3c2440/Kconfig"
1104 source "arch/arm/mach-s3c64xx/Kconfig"
1107 source "arch/arm/mach-s5p64x0/Kconfig"
1109 source "arch/arm/mach-s5pc100/Kconfig"
1111 source "arch/arm/mach-s5pv210/Kconfig"
1113 source "arch/arm/mach-exynos/Kconfig"
1115 source "arch/arm/mach-shmobile/Kconfig"
1117 source "arch/arm/mach-prima2/Kconfig"
1119 source "arch/arm/mach-tegra/Kconfig"
1121 source "arch/arm/mach-u300/Kconfig"
1123 source "arch/arm/mach-ux500/Kconfig"
1125 source "arch/arm/mach-versatile/Kconfig"
1127 source "arch/arm/mach-vexpress/Kconfig"
1128 source "arch/arm/plat-versatile/Kconfig"
1130 source "arch/arm/mach-vt8500/Kconfig"
1132 source "arch/arm/mach-w90x900/Kconfig"
1134 # Definitions to make life easier
1140 select GENERIC_CLOCKEVENTS
1145 select GENERIC_IRQ_CHIP
1152 config PLAT_VERSATILE
1155 config ARM_TIMER_SP804
1158 select HAVE_SCHED_CLOCK
1160 source arch/arm/mm/Kconfig
1164 default 16 if ARCH_EP93XX
1168 bool "Enable iWMMXt support"
1169 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1170 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1172 Enable support for iWMMXt context switching at run time if
1173 running on a CPU that supports it.
1177 depends on CPU_XSCALE
1180 config MULTI_IRQ_HANDLER
1183 Allow each machine to specify it's own IRQ handler at run time.
1186 source "arch/arm/Kconfig-nommu"
1189 config ARM_ERRATA_326103
1190 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1193 Executing a SWP instruction to read-only memory does not set bit 11
1194 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1195 treat the access as a read, preventing a COW from occurring and
1196 causing the faulting task to livelock.
1198 config ARM_ERRATA_411920
1199 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1200 depends on CPU_V6 || CPU_V6K
1202 Invalidation of the Instruction Cache operation can
1203 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1204 It does not affect the MPCore. This option enables the ARM Ltd.
1205 recommended workaround.
1207 config ARM_ERRATA_430973
1208 bool "ARM errata: Stale prediction on replaced interworking branch"
1211 This option enables the workaround for the 430973 Cortex-A8
1212 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1213 interworking branch is replaced with another code sequence at the
1214 same virtual address, whether due to self-modifying code or virtual
1215 to physical address re-mapping, Cortex-A8 does not recover from the
1216 stale interworking branch prediction. This results in Cortex-A8
1217 executing the new code sequence in the incorrect ARM or Thumb state.
1218 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1219 and also flushes the branch target cache at every context switch.
1220 Note that setting specific bits in the ACTLR register may not be
1221 available in non-secure mode.
1223 config ARM_ERRATA_458693
1224 bool "ARM errata: Processor deadlock when a false hazard is created"
1227 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1228 erratum. For very specific sequences of memory operations, it is
1229 possible for a hazard condition intended for a cache line to instead
1230 be incorrectly associated with a different cache line. This false
1231 hazard might then cause a processor deadlock. The workaround enables
1232 the L1 caching of the NEON accesses and disables the PLD instruction
1233 in the ACTLR register. Note that setting specific bits in the ACTLR
1234 register may not be available in non-secure mode.
1236 config ARM_ERRATA_460075
1237 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1240 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1241 erratum. Any asynchronous access to the L2 cache may encounter a
1242 situation in which recent store transactions to the L2 cache are lost
1243 and overwritten with stale memory contents from external memory. The
1244 workaround disables the write-allocate mode for the L2 cache via the
1245 ACTLR register. Note that setting specific bits in the ACTLR register
1246 may not be available in non-secure mode.
1248 config ARM_ERRATA_742230
1249 bool "ARM errata: DMB operation may be faulty"
1250 depends on CPU_V7 && SMP
1252 This option enables the workaround for the 742230 Cortex-A9
1253 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1254 between two write operations may not ensure the correct visibility
1255 ordering of the two writes. This workaround sets a specific bit in
1256 the diagnostic register of the Cortex-A9 which causes the DMB
1257 instruction to behave as a DSB, ensuring the correct behaviour of
1260 config ARM_ERRATA_742231
1261 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1262 depends on CPU_V7 && SMP
1264 This option enables the workaround for the 742231 Cortex-A9
1265 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1266 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1267 accessing some data located in the same cache line, may get corrupted
1268 data due to bad handling of the address hazard when the line gets
1269 replaced from one of the CPUs at the same time as another CPU is
1270 accessing it. This workaround sets specific bits in the diagnostic
1271 register of the Cortex-A9 which reduces the linefill issuing
1272 capabilities of the processor.
1274 config PL310_ERRATA_588369
1275 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1276 depends on CACHE_L2X0
1278 The PL310 L2 cache controller implements three types of Clean &
1279 Invalidate maintenance operations: by Physical Address
1280 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1281 They are architecturally defined to behave as the execution of a
1282 clean operation followed immediately by an invalidate operation,
1283 both performing to the same memory location. This functionality
1284 is not correctly implemented in PL310 as clean lines are not
1285 invalidated as a result of these operations.
1287 config ARM_ERRATA_720789
1288 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1291 This option enables the workaround for the 720789 Cortex-A9 (prior to
1292 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1293 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1294 As a consequence of this erratum, some TLB entries which should be
1295 invalidated are not, resulting in an incoherency in the system page
1296 tables. The workaround changes the TLB flushing routines to invalidate
1297 entries regardless of the ASID.
1299 config PL310_ERRATA_727915
1300 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1301 depends on CACHE_L2X0
1303 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1304 operation (offset 0x7FC). This operation runs in background so that
1305 PL310 can handle normal accesses while it is in progress. Under very
1306 rare circumstances, due to this erratum, write data can be lost when
1307 PL310 treats a cacheable write transaction during a Clean &
1308 Invalidate by Way operation.
1310 config ARM_ERRATA_743622
1311 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1314 This option enables the workaround for the 743622 Cortex-A9
1315 (r2p*) erratum. Under very rare conditions, a faulty
1316 optimisation in the Cortex-A9 Store Buffer may lead to data
1317 corruption. This workaround sets a specific bit in the diagnostic
1318 register of the Cortex-A9 which disables the Store Buffer
1319 optimisation, preventing the defect from occurring. This has no
1320 visible impact on the overall performance or power consumption of the
1323 config ARM_ERRATA_751472
1324 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1327 This option enables the workaround for the 751472 Cortex-A9 (prior
1328 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1329 completion of a following broadcasted operation if the second
1330 operation is received by a CPU before the ICIALLUIS has completed,
1331 potentially leading to corrupted entries in the cache or TLB.
1333 config PL310_ERRATA_753970
1334 bool "PL310 errata: cache sync operation may be faulty"
1335 depends on CACHE_PL310
1337 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1339 Under some condition the effect of cache sync operation on
1340 the store buffer still remains when the operation completes.
1341 This means that the store buffer is always asked to drain and
1342 this prevents it from merging any further writes. The workaround
1343 is to replace the normal offset of cache sync operation (0x730)
1344 by another offset targeting an unmapped PL310 register 0x740.
1345 This has the same effect as the cache sync operation: store buffer
1346 drain and waiting for all buffers empty.
1348 config ARM_ERRATA_754322
1349 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1352 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1353 r3p*) erratum. A speculative memory access may cause a page table walk
1354 which starts prior to an ASID switch but completes afterwards. This
1355 can populate the micro-TLB with a stale entry which may be hit with
1356 the new ASID. This workaround places two dsb instructions in the mm
1357 switching code so that no page table walks can cross the ASID switch.
1359 config ARM_ERRATA_754327
1360 bool "ARM errata: no automatic Store Buffer drain"
1361 depends on CPU_V7 && SMP
1363 This option enables the workaround for the 754327 Cortex-A9 (prior to
1364 r2p0) erratum. The Store Buffer does not have any automatic draining
1365 mechanism and therefore a livelock may occur if an external agent
1366 continuously polls a memory location waiting to observe an update.
1367 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1368 written polling loops from denying visibility of updates to memory.
1370 config ARM_ERRATA_364296
1371 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1372 depends on CPU_V6 && !SMP
1374 This options enables the workaround for the 364296 ARM1136
1375 r0p2 erratum (possible cache data corruption with
1376 hit-under-miss enabled). It sets the undocumented bit 31 in
1377 the auxiliary control register and the FI bit in the control
1378 register, thus disabling hit-under-miss without putting the
1379 processor into full low interrupt latency mode. ARM11MPCore
1382 config ARM_ERRATA_764369
1383 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1384 depends on CPU_V7 && SMP
1386 This option enables the workaround for erratum 764369
1387 affecting Cortex-A9 MPCore with two or more processors (all
1388 current revisions). Under certain timing circumstances, a data
1389 cache line maintenance operation by MVA targeting an Inner
1390 Shareable memory region may fail to proceed up to either the
1391 Point of Coherency or to the Point of Unification of the
1392 system. This workaround adds a DSB instruction before the
1393 relevant cache maintenance functions and sets a specific bit
1394 in the diagnostic control register of the SCU.
1396 config PL310_ERRATA_769419
1397 bool "PL310 errata: no automatic Store Buffer drain"
1398 depends on CACHE_L2X0
1400 On revisions of the PL310 prior to r3p2, the Store Buffer does
1401 not automatically drain. This can cause normal, non-cacheable
1402 writes to be retained when the memory system is idle, leading
1403 to suboptimal I/O performance for drivers using coherent DMA.
1404 This option adds a write barrier to the cpu_idle loop so that,
1405 on systems with an outer cache, the store buffer is drained
1410 source "arch/arm/common/Kconfig"
1420 Find out whether you have ISA slots on your motherboard. ISA is the
1421 name of a bus system, i.e. the way the CPU talks to the other stuff
1422 inside your box. Other bus systems are PCI, EISA, MicroChannel
1423 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1424 newer boards don't support it. If you have ISA, say Y, otherwise N.
1426 # Select ISA DMA controller support
1431 # Select ISA DMA interface
1436 bool "PCI support" if MIGHT_HAVE_PCI
1438 Find out whether you have a PCI motherboard. PCI is the name of a
1439 bus system, i.e. the way the CPU talks to the other stuff inside
1440 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1441 VESA. If you have PCI, say Y, otherwise N.
1447 config PCI_NANOENGINE
1448 bool "BSE nanoEngine PCI support"
1449 depends on SA1100_NANOENGINE
1451 Enable PCI on the BSE nanoEngine board.
1456 # Select the host bridge type
1457 config PCI_HOST_VIA82C505
1459 depends on PCI && ARCH_SHARK
1462 config PCI_HOST_ITE8152
1464 depends on PCI && MACH_ARMCORE
1468 source "drivers/pci/Kconfig"
1470 source "drivers/pcmcia/Kconfig"
1474 menu "Kernel Features"
1479 This option should be selected by machines which have an SMP-
1482 The only effect of this option is to make the SMP-related
1483 options available to the user for configuration.
1486 bool "Symmetric Multi-Processing"
1487 depends on CPU_V6K || CPU_V7
1488 depends on GENERIC_CLOCKEVENTS
1491 select USE_GENERIC_SMP_HELPERS
1492 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1494 This enables support for systems with more than one CPU. If you have
1495 a system with only one CPU, like most personal computers, say N. If
1496 you have a system with more than one CPU, say Y.
1498 If you say N here, the kernel will run on single and multiprocessor
1499 machines, but will use only one CPU of a multiprocessor machine. If
1500 you say Y here, the kernel will run on many, but not all, single
1501 processor machines. On a single processor machine, the kernel will
1502 run faster if you say N here.
1504 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1505 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1506 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1508 If you don't know what to do here, say N.
1511 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1512 depends on EXPERIMENTAL
1513 depends on SMP && !XIP_KERNEL
1516 SMP kernels contain instructions which fail on non-SMP processors.
1517 Enabling this option allows the kernel to modify itself to make
1518 these instructions safe. Disabling it allows about 1K of space
1521 If you don't know what to do here, say Y.
1523 config ARM_CPU_TOPOLOGY
1524 bool "Support cpu topology definition"
1525 depends on SMP && CPU_V7
1528 Support ARM cpu topology definition. The MPIDR register defines
1529 affinity between processors which is then used to describe the cpu
1530 topology of an ARM System.
1533 bool "Multi-core scheduler support"
1534 depends on ARM_CPU_TOPOLOGY
1536 Multi-core scheduler support improves the CPU scheduler's decision
1537 making when dealing with multi-core CPU chips at a cost of slightly
1538 increased overhead in some places. If unsure say N here.
1541 bool "SMT scheduler support"
1542 depends on ARM_CPU_TOPOLOGY
1544 Improves the CPU scheduler's decision making when dealing with
1545 MultiThreading at a cost of slightly increased overhead in some
1546 places. If unsure say N here.
1551 This option enables support for the ARM system coherency unit
1553 config ARM_ARCH_TIMER
1554 bool "Architected timer support"
1557 This option enables support for the ARM architected timer
1563 This options enables support for the ARM timer and watchdog unit
1566 prompt "Memory split"
1569 Select the desired split between kernel and user memory.
1571 If you are not absolutely sure what you are doing, leave this
1575 bool "3G/1G user/kernel split"
1577 bool "2G/2G user/kernel split"
1579 bool "1G/3G user/kernel split"
1584 default 0x40000000 if VMSPLIT_1G
1585 default 0x80000000 if VMSPLIT_2G
1589 int "Maximum number of CPUs (2-32)"
1595 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1596 depends on SMP && HOTPLUG && EXPERIMENTAL
1598 Say Y here to experiment with turning CPUs off and on. CPUs
1599 can be controlled through /sys/devices/system/cpu.
1602 bool "Use local timer interrupts"
1605 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1607 Enable support for local timers on SMP platforms, rather then the
1608 legacy IPI broadcast method. Local timers allows the system
1609 accounting to be spread across the timer interval, preventing a
1610 "thundering herd" at every timer tick.
1614 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1615 default 355 if ARCH_U8500
1616 default 264 if MACH_H4700
1617 default 512 if SOC_OMAP5
1620 Maximum number of GPIOs in the system.
1622 If unsure, leave the default value.
1624 source kernel/Kconfig.preempt
1628 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1629 ARCH_S5PV210 || ARCH_EXYNOS4
1630 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1631 default AT91_TIMER_HZ if ARCH_AT91
1632 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1635 config THUMB2_KERNEL
1636 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1637 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1639 select ARM_ASM_UNIFIED
1642 By enabling this option, the kernel will be compiled in
1643 Thumb-2 mode. A compiler/assembler that understand the unified
1644 ARM-Thumb syntax is needed.
1648 config THUMB2_AVOID_R_ARM_THM_JUMP11
1649 bool "Work around buggy Thumb-2 short branch relocations in gas"
1650 depends on THUMB2_KERNEL && MODULES
1653 Various binutils versions can resolve Thumb-2 branches to
1654 locally-defined, preemptible global symbols as short-range "b.n"
1655 branch instructions.
1657 This is a problem, because there's no guarantee the final
1658 destination of the symbol, or any candidate locations for a
1659 trampoline, are within range of the branch. For this reason, the
1660 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1661 relocation in modules at all, and it makes little sense to add
1664 The symptom is that the kernel fails with an "unsupported
1665 relocation" error when loading some modules.
1667 Until fixed tools are available, passing
1668 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1669 code which hits this problem, at the cost of a bit of extra runtime
1670 stack usage in some cases.
1672 The problem is described in more detail at:
1673 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1675 Only Thumb-2 kernels are affected.
1677 Unless you are sure your tools don't have this problem, say Y.
1679 config ARM_ASM_UNIFIED
1683 bool "Use the ARM EABI to compile the kernel"
1685 This option allows for the kernel to be compiled using the latest
1686 ARM ABI (aka EABI). This is only useful if you are using a user
1687 space environment that is also compiled with EABI.
1689 Since there are major incompatibilities between the legacy ABI and
1690 EABI, especially with regard to structure member alignment, this
1691 option also changes the kernel syscall calling convention to
1692 disambiguate both ABIs and allow for backward compatibility support
1693 (selected with CONFIG_OABI_COMPAT).
1695 To use this you need GCC version 4.0.0 or later.
1698 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1699 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1702 This option preserves the old syscall interface along with the
1703 new (ARM EABI) one. It also provides a compatibility layer to
1704 intercept syscalls that have structure arguments which layout
1705 in memory differs between the legacy ABI and the new ARM EABI
1706 (only for non "thumb" binaries). This option adds a tiny
1707 overhead to all syscalls and produces a slightly larger kernel.
1708 If you know you'll be using only pure EABI user space then you
1709 can say N here. If this option is not selected and you attempt
1710 to execute a legacy ABI binary then the result will be
1711 UNPREDICTABLE (in fact it can be predicted that it won't work
1712 at all). If in doubt say Y.
1714 config ARCH_HAS_HOLES_MEMORYMODEL
1717 config ARCH_SPARSEMEM_ENABLE
1720 config ARCH_SPARSEMEM_DEFAULT
1721 def_bool ARCH_SPARSEMEM_ENABLE
1723 config ARCH_SELECT_MEMORY_MODEL
1724 def_bool ARCH_SPARSEMEM_ENABLE
1726 config HAVE_ARCH_PFN_VALID
1727 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1730 bool "High Memory Support"
1733 The address space of ARM processors is only 4 Gigabytes large
1734 and it has to accommodate user address space, kernel address
1735 space as well as some memory mapped IO. That means that, if you
1736 have a large amount of physical memory and/or IO, not all of the
1737 memory can be "permanently mapped" by the kernel. The physical
1738 memory that is not permanently mapped is called "high memory".
1740 Depending on the selected kernel/user memory split, minimum
1741 vmalloc space and actual amount of RAM, you may not need this
1742 option which should result in a slightly faster kernel.
1747 bool "Allocate 2nd-level pagetables from highmem"
1750 config HW_PERF_EVENTS
1751 bool "Enable hardware performance counter support for perf events"
1752 depends on PERF_EVENTS
1755 Enable hardware performance counter support for perf events. If
1756 disabled, perf events will use software events only.
1760 config FORCE_MAX_ZONEORDER
1761 int "Maximum zone order" if ARCH_SHMOBILE
1762 range 11 64 if ARCH_SHMOBILE
1763 default "9" if SA1111
1766 The kernel memory allocator divides physically contiguous memory
1767 blocks into "zones", where each zone is a power of two number of
1768 pages. This option selects the largest power of two that the kernel
1769 keeps in the memory allocator. If you need to allocate very large
1770 blocks of physically contiguous memory, then you may need to
1771 increase this value.
1773 This config option is actually maximum order plus one. For example,
1774 a value of 11 means that the largest free memory block is 2^10 pages.
1777 bool "Timer and CPU usage LEDs"
1778 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1779 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1780 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1781 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1782 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1783 ARCH_AT91 || ARCH_DAVINCI || \
1784 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1786 If you say Y here, the LEDs on your machine will be used
1787 to provide useful information about your current system status.
1789 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1790 be able to select which LEDs are active using the options below. If
1791 you are compiling a kernel for the EBSA-110 or the LART however, the
1792 red LED will simply flash regularly to indicate that the system is
1793 still functional. It is safe to say Y here if you have a CATS
1794 system, but the driver will do nothing.
1797 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1798 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1799 || MACH_OMAP_PERSEUS2
1801 depends on !GENERIC_CLOCKEVENTS
1802 default y if ARCH_EBSA110
1804 If you say Y here, one of the system LEDs (the green one on the
1805 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1806 will flash regularly to indicate that the system is still
1807 operational. This is mainly useful to kernel hackers who are
1808 debugging unstable kernels.
1810 The LART uses the same LED for both Timer LED and CPU usage LED
1811 functions. You may choose to use both, but the Timer LED function
1812 will overrule the CPU usage LED.
1815 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1817 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1818 || MACH_OMAP_PERSEUS2
1821 If you say Y here, the red LED will be used to give a good real
1822 time indication of CPU usage, by lighting whenever the idle task
1823 is not currently executing.
1825 The LART uses the same LED for both Timer LED and CPU usage LED
1826 functions. You may choose to use both, but the Timer LED function
1827 will overrule the CPU usage LED.
1829 config ALIGNMENT_TRAP
1831 depends on CPU_CP15_MMU
1832 default y if !ARCH_EBSA110
1833 select HAVE_PROC_CPU if PROC_FS
1835 ARM processors cannot fetch/store information which is not
1836 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1837 address divisible by 4. On 32-bit ARM processors, these non-aligned
1838 fetch/store instructions will be emulated in software if you say
1839 here, which has a severe performance impact. This is necessary for
1840 correct operation of some network protocols. With an IP-only
1841 configuration it is safe to say N, otherwise say Y.
1843 config UACCESS_WITH_MEMCPY
1844 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1845 depends on MMU && EXPERIMENTAL
1846 default y if CPU_FEROCEON
1848 Implement faster copy_to_user and clear_user methods for CPU
1849 cores where a 8-word STM instruction give significantly higher
1850 memory write throughput than a sequence of individual 32bit stores.
1852 A possible side effect is a slight increase in scheduling latency
1853 between threads sharing the same address space if they invoke
1854 such copy operations with large buffers.
1856 However, if the CPU data cache is using a write-allocate mode,
1857 this option is unlikely to provide any performance gain.
1861 prompt "Enable seccomp to safely compute untrusted bytecode"
1863 This kernel feature is useful for number crunching applications
1864 that may need to compute untrusted bytecode during their
1865 execution. By using pipes or other transports made available to
1866 the process as file descriptors supporting the read/write
1867 syscalls, it's possible to isolate those applications in
1868 their own address space using seccomp. Once seccomp is
1869 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1870 and the task is only allowed to execute a few safe syscalls
1871 defined by each seccomp mode.
1873 config CC_STACKPROTECTOR
1874 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1875 depends on EXPERIMENTAL
1877 This option turns on the -fstack-protector GCC feature. This
1878 feature puts, at the beginning of functions, a canary value on
1879 the stack just before the return address, and validates
1880 the value just before actually returning. Stack based buffer
1881 overflows (that need to overwrite this return address) now also
1882 overwrite the canary, which gets detected and the attack is then
1883 neutralized via a kernel panic.
1884 This feature requires gcc version 4.2 or above.
1886 config DEPRECATED_PARAM_STRUCT
1887 bool "Provide old way to pass kernel parameters"
1889 This was deprecated in 2001 and announced to live on for 5 years.
1890 Some old boot loaders still use this way.
1897 bool "Flattened Device Tree support"
1899 select OF_EARLY_FLATTREE
1902 Include support for flattened device tree machine descriptions.
1904 # Compressed boot loader in ROM. Yes, we really want to ask about
1905 # TEXT and BSS so we preserve their values in the config files.
1906 config ZBOOT_ROM_TEXT
1907 hex "Compressed ROM boot loader base address"
1910 The physical address at which the ROM-able zImage is to be
1911 placed in the target. Platforms which normally make use of
1912 ROM-able zImage formats normally set this to a suitable
1913 value in their defconfig file.
1915 If ZBOOT_ROM is not enabled, this has no effect.
1917 config ZBOOT_ROM_BSS
1918 hex "Compressed ROM boot loader BSS address"
1921 The base address of an area of read/write memory in the target
1922 for the ROM-able zImage which must be available while the
1923 decompressor is running. It must be large enough to hold the
1924 entire decompressed kernel plus an additional 128 KiB.
1925 Platforms which normally make use of ROM-able zImage formats
1926 normally set this to a suitable value in their defconfig file.
1928 If ZBOOT_ROM is not enabled, this has no effect.
1931 bool "Compressed boot loader in ROM/flash"
1932 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1934 Say Y here if you intend to execute your compressed kernel image
1935 (zImage) directly from ROM or flash. If unsure, say N.
1938 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1939 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1940 default ZBOOT_ROM_NONE
1942 Include experimental SD/MMC loading code in the ROM-able zImage.
1943 With this enabled it is possible to write the ROM-able zImage
1944 kernel image to an MMC or SD card and boot the kernel straight
1945 from the reset vector. At reset the processor Mask ROM will load
1946 the first part of the ROM-able zImage which in turn loads the
1947 rest the kernel image to RAM.
1949 config ZBOOT_ROM_NONE
1950 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1952 Do not load image from SD or MMC
1954 config ZBOOT_ROM_MMCIF
1955 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1957 Load image from MMCIF hardware block.
1959 config ZBOOT_ROM_SH_MOBILE_SDHI
1960 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1962 Load image from SDHI hardware block
1966 config ARM_APPENDED_DTB
1967 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1968 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1970 With this option, the boot code will look for a device tree binary
1971 (DTB) appended to zImage
1972 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1974 This is meant as a backward compatibility convenience for those
1975 systems with a bootloader that can't be upgraded to accommodate
1976 the documented boot protocol using a device tree.
1978 Beware that there is very little in terms of protection against
1979 this option being confused by leftover garbage in memory that might
1980 look like a DTB header after a reboot if no actual DTB is appended
1981 to zImage. Do not leave this option active in a production kernel
1982 if you don't intend to always append a DTB. Proper passing of the
1983 location into r2 of a bootloader provided DTB is always preferable
1986 config ARM_ATAG_DTB_COMPAT
1987 bool "Supplement the appended DTB with traditional ATAG information"
1988 depends on ARM_APPENDED_DTB
1990 Some old bootloaders can't be updated to a DTB capable one, yet
1991 they provide ATAGs with memory configuration, the ramdisk address,
1992 the kernel cmdline string, etc. Such information is dynamically
1993 provided by the bootloader and can't always be stored in a static
1994 DTB. To allow a device tree enabled kernel to be used with such
1995 bootloaders, this option allows zImage to extract the information
1996 from the ATAG list and store it at run time into the appended DTB.
1999 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2000 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2002 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2003 bool "Use bootloader kernel arguments if available"
2005 Uses the command-line options passed by the boot loader instead of
2006 the device tree bootargs property. If the boot loader doesn't provide
2007 any, the device tree bootargs property will be used.
2009 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2010 bool "Extend with bootloader kernel arguments"
2012 The command-line arguments provided by the boot loader will be
2013 appended to the the device tree bootargs property.
2018 string "Default kernel command string"
2021 On some architectures (EBSA110 and CATS), there is currently no way
2022 for the boot loader to pass arguments to the kernel. For these
2023 architectures, you should supply some command-line options at build
2024 time by entering them here. As a minimum, you should specify the
2025 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2028 prompt "Kernel command line type" if CMDLINE != ""
2029 default CMDLINE_FROM_BOOTLOADER
2031 config CMDLINE_FROM_BOOTLOADER
2032 bool "Use bootloader kernel arguments if available"
2034 Uses the command-line options passed by the boot loader. If
2035 the boot loader doesn't provide any, the default kernel command
2036 string provided in CMDLINE will be used.
2038 config CMDLINE_EXTEND
2039 bool "Extend bootloader kernel arguments"
2041 The command-line arguments provided by the boot loader will be
2042 appended to the default kernel command string.
2044 config CMDLINE_FORCE
2045 bool "Always use the default kernel command string"
2047 Always use the default kernel command string, even if the boot
2048 loader passes other arguments to the kernel.
2049 This is useful if you cannot or don't want to change the
2050 command-line options your boot loader passes to the kernel.
2054 bool "Kernel Execute-In-Place from ROM"
2055 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2057 Execute-In-Place allows the kernel to run from non-volatile storage
2058 directly addressable by the CPU, such as NOR flash. This saves RAM
2059 space since the text section of the kernel is not loaded from flash
2060 to RAM. Read-write sections, such as the data section and stack,
2061 are still copied to RAM. The XIP kernel is not compressed since
2062 it has to run directly from flash, so it will take more space to
2063 store it. The flash address used to link the kernel object files,
2064 and for storing it, is configuration dependent. Therefore, if you
2065 say Y here, you must know the proper physical address where to
2066 store the kernel image depending on your own flash memory usage.
2068 Also note that the make target becomes "make xipImage" rather than
2069 "make zImage" or "make Image". The final kernel binary to put in
2070 ROM memory will be arch/arm/boot/xipImage.
2074 config XIP_PHYS_ADDR
2075 hex "XIP Kernel Physical Location"
2076 depends on XIP_KERNEL
2077 default "0x00080000"
2079 This is the physical address in your flash memory the kernel will
2080 be linked for and stored to. This address is dependent on your
2084 bool "Kexec system call (EXPERIMENTAL)"
2085 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2087 kexec is a system call that implements the ability to shutdown your
2088 current kernel, and to start another kernel. It is like a reboot
2089 but it is independent of the system firmware. And like a reboot
2090 you can start any kernel with it, not just Linux.
2092 It is an ongoing process to be certain the hardware in a machine
2093 is properly shutdown, so do not be surprised if this code does not
2094 initially work for you. It may help to enable device hotplugging
2098 bool "Export atags in procfs"
2102 Should the atags used to boot the kernel be exported in an "atags"
2103 file in procfs. Useful with kexec.
2106 bool "Build kdump crash kernel (EXPERIMENTAL)"
2107 depends on EXPERIMENTAL
2109 Generate crash dump after being started by kexec. This should
2110 be normally only set in special crash dump kernels which are
2111 loaded in the main kernel with kexec-tools into a specially
2112 reserved region and then later executed after a crash by
2113 kdump/kexec. The crash dump kernel must be compiled to a
2114 memory address not used by the main kernel
2116 For more details see Documentation/kdump/kdump.txt
2118 config AUTO_ZRELADDR
2119 bool "Auto calculation of the decompressed kernel image address"
2120 depends on !ZBOOT_ROM && !ARCH_U300
2122 ZRELADDR is the physical address where the decompressed kernel
2123 image will be placed. If AUTO_ZRELADDR is selected, the address
2124 will be determined at run-time by masking the current IP with
2125 0xf8000000. This assumes the zImage being placed in the first 128MB
2126 from start of memory.
2130 menu "CPU Power Management"
2134 source "drivers/cpufreq/Kconfig"
2137 tristate "CPUfreq driver for i.MX CPUs"
2138 depends on ARCH_MXC && CPU_FREQ
2139 select CPU_FREQ_TABLE
2141 This enables the CPUfreq driver for i.MX CPUs.
2143 config CPU_FREQ_SA1100
2146 config CPU_FREQ_SA1110
2149 config CPU_FREQ_INTEGRATOR
2150 tristate "CPUfreq driver for ARM Integrator CPUs"
2151 depends on ARCH_INTEGRATOR && CPU_FREQ
2154 This enables the CPUfreq driver for ARM Integrator CPUs.
2156 For details, take a look at <file:Documentation/cpu-freq>.
2162 depends on CPU_FREQ && ARCH_PXA && PXA25x
2164 select CPU_FREQ_TABLE
2165 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2170 Internal configuration node for common cpufreq on Samsung SoC
2172 config CPU_FREQ_S3C24XX
2173 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2174 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2177 This enables the CPUfreq driver for the Samsung S3C24XX family
2180 For details, take a look at <file:Documentation/cpu-freq>.
2184 config CPU_FREQ_S3C24XX_PLL
2185 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2186 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2188 Compile in support for changing the PLL frequency from the
2189 S3C24XX series CPUfreq driver. The PLL takes time to settle
2190 after a frequency change, so by default it is not enabled.
2192 This also means that the PLL tables for the selected CPU(s) will
2193 be built which may increase the size of the kernel image.
2195 config CPU_FREQ_S3C24XX_DEBUG
2196 bool "Debug CPUfreq Samsung driver core"
2197 depends on CPU_FREQ_S3C24XX
2199 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2201 config CPU_FREQ_S3C24XX_IODEBUG
2202 bool "Debug CPUfreq Samsung driver IO timing"
2203 depends on CPU_FREQ_S3C24XX
2205 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2207 config CPU_FREQ_S3C24XX_DEBUGFS
2208 bool "Export debugfs for CPUFreq"
2209 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2211 Export status information via debugfs.
2215 source "drivers/cpuidle/Kconfig"
2219 menu "Floating point emulation"
2221 comment "At least one emulation must be selected"
2224 bool "NWFPE math emulation"
2225 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2227 Say Y to include the NWFPE floating point emulator in the kernel.
2228 This is necessary to run most binaries. Linux does not currently
2229 support floating point hardware so you need to say Y here even if
2230 your machine has an FPA or floating point co-processor podule.
2232 You may say N here if you are going to load the Acorn FPEmulator
2233 early in the bootup.
2236 bool "Support extended precision"
2237 depends on FPE_NWFPE
2239 Say Y to include 80-bit support in the kernel floating-point
2240 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2241 Note that gcc does not generate 80-bit operations by default,
2242 so in most cases this option only enlarges the size of the
2243 floating point emulator without any good reason.
2245 You almost surely want to say N here.
2248 bool "FastFPE math emulation (EXPERIMENTAL)"
2249 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2251 Say Y here to include the FAST floating point emulator in the kernel.
2252 This is an experimental much faster emulator which now also has full
2253 precision for the mantissa. It does not support any exceptions.
2254 It is very simple, and approximately 3-6 times faster than NWFPE.
2256 It should be sufficient for most programs. It may be not suitable
2257 for scientific calculations, but you have to check this for yourself.
2258 If you do not feel you need a faster FP emulation you should better
2262 bool "VFP-format floating point maths"
2263 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2265 Say Y to include VFP support code in the kernel. This is needed
2266 if your hardware includes a VFP unit.
2268 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2269 release notes and additional status information.
2271 Say N if your target does not have VFP hardware.
2279 bool "Advanced SIMD (NEON) Extension support"
2280 depends on VFPv3 && CPU_V7
2282 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2287 menu "Userspace binary formats"
2289 source "fs/Kconfig.binfmt"
2292 tristate "RISC OS personality"
2295 Say Y here to include the kernel code necessary if you want to run
2296 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2297 experimental; if this sounds frightening, say N and sleep in peace.
2298 You can also say M here to compile this support as a module (which
2299 will be called arthur).
2303 menu "Power management options"
2305 source "kernel/power/Kconfig"
2307 config ARCH_SUSPEND_POSSIBLE
2308 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2309 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2310 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2313 config ARM_CPU_SUSPEND
2318 source "net/Kconfig"
2320 source "drivers/Kconfig"
2324 source "arch/arm/Kconfig.debug"
2326 source "security/Kconfig"
2328 source "crypto/Kconfig"
2330 source "lib/Kconfig"