4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_DEBUG_KMEMLEAK
36 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_CONTIGUOUS if MMU
39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
46 select HAVE_IDE if PCI || ISA || PCMCIA
47 select HAVE_IRQ_TIME_ACCOUNTING
48 select HAVE_KERNEL_GZIP
49 select HAVE_KERNEL_LZ4
50 select HAVE_KERNEL_LZMA
51 select HAVE_KERNEL_LZO
53 select HAVE_KPROBES if !XIP_KERNEL
54 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
58 select HAVE_PERF_EVENTS
60 select HAVE_PERF_USER_STACK_DUMP
61 select HAVE_REGS_AND_STACK_ACCESS_API
62 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_VIRT_CPU_ACCOUNTING_GEN
65 select IRQ_FORCED_THREADING
67 select MODULES_USE_ELF_REL
70 select OLD_SIGSUSPEND3
71 select PERF_USE_VMALLOC
73 select SYS_SUPPORTS_APM_EMULATION
74 # Above selects are sorted alphabetically; please add new ones
75 # according to that. Thanks.
77 The ARM series is a line of low-power-consumption RISC chip designs
78 licensed by ARM Ltd and targeted at embedded applications and
79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
80 manufactured, but legacy ARM-based PC hardware remains popular in
81 Europe. There is an ARM Linux project with a web page at
82 <http://www.arm.linux.org.uk/>.
84 config ARM_HAS_SG_CHAIN
87 config NEED_SG_DMA_LENGTH
90 config ARM_DMA_USE_IOMMU
92 select ARM_HAS_SG_CHAIN
93 select NEED_SG_DMA_LENGTH
97 config ARM_DMA_IOMMU_ALIGNMENT
98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
102 DMA mapping framework by default aligns all buffers to the smallest
103 PAGE_SIZE order which is greater than or equal to the requested buffer
104 size. This works well for buffers up to a few hundreds kilobytes, but
105 for larger buffers it just a waste of address space. Drivers which has
106 relatively small addressing window (like 64Mib) might run out of
107 virtual space with just a few allocations.
109 With this parameter you can specify the maximum PAGE_SIZE order for
110 DMA IOMMU buffers. Larger buffers will be aligned only to this
111 specified order. The order is expressed as a power of two multiplied
116 config MIGHT_HAVE_PCI
119 config SYS_SUPPORTS_APM_EMULATION
124 select GENERIC_ALLOCATOR
135 The Extended Industry Standard Architecture (EISA) bus was
136 developed as an open alternative to the IBM MicroChannel bus.
138 The EISA bus provided some of the features of the IBM MicroChannel
139 bus while maintaining backward compatibility with cards made for
140 the older ISA bus. The EISA bus saw limited use between 1988 and
141 1995 when it was made obsolete by the PCI bus.
143 Say Y here if you are building a kernel for an EISA-based machine.
150 config STACKTRACE_SUPPORT
154 config HAVE_LATENCYTOP_SUPPORT
159 config LOCKDEP_SUPPORT
163 config TRACE_IRQFLAGS_SUPPORT
167 config RWSEM_GENERIC_SPINLOCK
171 config RWSEM_XCHGADD_ALGORITHM
174 config ARCH_HAS_ILOG2_U32
177 config ARCH_HAS_ILOG2_U64
180 config ARCH_HAS_CPUFREQ
183 Internal node to signify that the ARCH has CPUFREQ support
184 and that the relevant menu configurations are displayed for
187 config ARCH_HAS_BANDGAP
190 config GENERIC_HWEIGHT
194 config GENERIC_CALIBRATE_DELAY
198 config ARCH_MAY_HAVE_PC_FDC
204 config NEED_DMA_MAP_STATE
207 config ARCH_SUPPORTS_UPROBES
210 config ARCH_HAS_DMA_SET_COHERENT_MASK
213 config GENERIC_ISA_DMA
219 config NEED_RET_TO_USER
227 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
228 default DRAM_BASE if REMAP_VECTORS_TO_RAM
231 The base address of exception vectors. This must be two pages
234 config ARM_PATCH_PHYS_VIRT
235 bool "Patch physical to virtual translations at runtime" if EMBEDDED
237 depends on !XIP_KERNEL && MMU
238 depends on !ARCH_REALVIEW || !SPARSEMEM
240 Patch phys-to-virt and virt-to-phys translation functions at
241 boot and module load time according to the position of the
242 kernel in system memory.
244 This can only be used with non-XIP MMU kernels where the base
245 of physical memory is at a 16MB boundary.
247 Only disable this option if you know that you do not require
248 this feature (eg, building a kernel for a single machine) and
249 you need to shrink the kernel to the minimal size.
251 config NEED_MACH_GPIO_H
254 Select this when mach/gpio.h is required to provide special
255 definitions for this platform. The need for mach/gpio.h should
256 be avoided when possible.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
275 default DRAM_BASE if !MMU
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 source "init/Kconfig"
286 source "kernel/Kconfig.freezer"
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
298 # The "ARM system type" choice list is ordered alphabetically by option
299 # text. Please add new entries in the option alphabetic order.
302 prompt "ARM system type"
303 default ARCH_VERSATILE if !MMU
304 default ARCH_MULTIPLATFORM if MMU
306 config ARCH_MULTIPLATFORM
307 bool "Allow multiple platforms to be selected"
309 select ARCH_WANT_OPTIONAL_GPIOLIB
310 select ARM_HAS_SG_CHAIN
311 select ARM_PATCH_PHYS_VIRT
314 select GENERIC_CLOCKEVENTS
315 select MULTI_IRQ_HANDLER
319 config ARCH_INTEGRATOR
320 bool "ARM Ltd. Integrator family"
321 select ARCH_HAS_CPUFREQ
323 select ARM_PATCH_PHYS_VIRT
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
330 select MULTI_IRQ_HANDLER
331 select NEED_MACH_MEMORY_H
332 select PLAT_VERSATILE
335 select VERSATILE_FPGA_IRQ
337 Support for ARM's Integrator platform.
340 bool "ARM Ltd. RealView family"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
345 select COMMON_CLK_VERSATILE
346 select GENERIC_CLOCKEVENTS
347 select GPIO_PL061 if GPIOLIB
349 select NEED_MACH_MEMORY_H
350 select PLAT_VERSATILE
351 select PLAT_VERSATILE_CLCD
353 This enables support for ARM Ltd RealView boards.
355 config ARCH_VERSATILE
356 bool "ARM Ltd. Versatile family"
357 select ARCH_WANT_OPTIONAL_GPIOLIB
359 select ARM_TIMER_SP804
362 select GENERIC_CLOCKEVENTS
363 select HAVE_MACH_CLKDEV
365 select PLAT_VERSATILE
366 select PLAT_VERSATILE_CLCD
367 select PLAT_VERSATILE_CLOCK
368 select VERSATILE_FPGA_IRQ
370 This enables support for ARM Ltd Versatile board.
374 select ARCH_REQUIRE_GPIOLIB
377 select NEED_MACH_GPIO_H
378 select NEED_MACH_IO_H if PCCARD
380 select PINCTRL_AT91 if USE_OF
382 This enables support for systems based on Atmel
383 AT91RM9200 and AT91SAM9* processors.
386 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
387 select ARCH_REQUIRE_GPIOLIB
392 select GENERIC_CLOCKEVENTS
395 Support for Cirrus Logic 711x/721x/731x based boards.
398 bool "Cortina Systems Gemini"
399 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
404 Support for the Cortina Systems Gemini family SoCs
408 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_IO_H
412 select NEED_MACH_MEMORY_H
415 This is an evaluation board for the StrongARM processor available
416 from Digital. It has limited hardware on-board, including an
417 Ethernet interface, two PCMCIA sockets, two serial ports and a
421 bool "Energy Micro efm32"
423 select ARCH_REQUIRE_GPIOLIB
429 select GENERIC_CLOCKEVENTS
435 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
440 select ARCH_HAS_HOLES_MEMORYMODEL
441 select ARCH_REQUIRE_GPIOLIB
442 select ARCH_USES_GETTIMEOFFSET
447 select NEED_MACH_MEMORY_H
449 This enables support for the Cirrus EP93xx series of CPUs.
451 config ARCH_FOOTBRIDGE
455 select GENERIC_CLOCKEVENTS
457 select NEED_MACH_IO_H if !MMU
458 select NEED_MACH_MEMORY_H
460 Support for systems based on the DC21285 companion chip
461 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
464 bool "Hilscher NetX based"
468 select GENERIC_CLOCKEVENTS
470 This enables support for systems based on the Hilscher NetX Soc
476 select NEED_MACH_MEMORY_H
477 select NEED_RET_TO_USER
482 Support for Intel's IOP13XX (XScale) family of processors.
487 select ARCH_REQUIRE_GPIOLIB
490 select NEED_RET_TO_USER
494 Support for Intel's 80219 and IOP32X (XScale) family of
500 select ARCH_REQUIRE_GPIOLIB
503 select NEED_RET_TO_USER
507 Support for Intel's IOP33X (XScale) family of processors.
512 select ARCH_HAS_DMA_SET_COHERENT_MASK
513 select ARCH_SUPPORTS_BIG_ENDIAN
514 select ARCH_REQUIRE_GPIOLIB
517 select DMABOUNCE if PCI
518 select GENERIC_CLOCKEVENTS
519 select MIGHT_HAVE_PCI
520 select NEED_MACH_IO_H
521 select USB_EHCI_BIG_ENDIAN_DESC
522 select USB_EHCI_BIG_ENDIAN_MMIO
524 Support for Intel's IXP4XX (XScale) family of processors.
528 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
531 select MIGHT_HAVE_PCI
535 select PLAT_ORION_LEGACY
537 Support for the Marvell Dove SoC 88AP510
540 bool "Marvell Kirkwood"
541 select ARCH_HAS_CPUFREQ
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
549 select PINCTRL_KIRKWOOD
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
556 bool "Marvell MV78xx0"
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
562 select PLAT_ORION_LEGACY
564 Support for the following Marvell MV78xx0 series SoCs:
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
575 select PLAT_ORION_LEGACY
577 Support for the following Marvell Orion 5x series SoCs:
578 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
579 Orion-2 (5281), Orion-1-90 (6183).
582 bool "Marvell PXA168/910/MMP2"
584 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_ALLOCATOR
587 select GENERIC_CLOCKEVENTS
590 select MULTI_IRQ_HANDLER
595 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 bool "Micrel/Kendin KS8695"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NEED_MACH_MEMORY_H
605 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
606 System-on-Chip devices.
609 bool "Nuvoton W90X900 CPU"
610 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
616 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
617 At present, the w90x900 has been renamed nuc900, regarding
618 the ARM series product line, you can login the following
619 link address to know more.
621 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
622 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
626 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
635 Support for the NXP LPC32XX family of processors
638 bool "PXA2xx/PXA3xx-based"
640 select ARCH_HAS_CPUFREQ
642 select ARCH_REQUIRE_GPIOLIB
643 select ARM_CPU_SUSPEND if PM
647 select GENERIC_CLOCKEVENTS
650 select MULTI_IRQ_HANDLER
654 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
657 bool "Qualcomm MSM (non-multiplatform)"
658 select ARCH_REQUIRE_GPIOLIB
660 select GENERIC_CLOCKEVENTS
662 Support for Qualcomm MSM/QSD based systems. This runs on the
663 apps processor of the MSM/QSD and depends on a shared memory
664 interface to the modem processor which runs the baseband
665 stack and controls some vital subsystems
666 (clock and power control, etc).
668 config ARCH_SHMOBILE_LEGACY
669 bool "Renesas ARM SoCs (non-multiplatform)"
671 select ARM_PATCH_PHYS_VIRT
673 select GENERIC_CLOCKEVENTS
674 select HAVE_ARM_SCU if SMP
675 select HAVE_ARM_TWD if SMP
676 select HAVE_MACH_CLKDEV
678 select MIGHT_HAVE_CACHE_L2X0
679 select MULTI_IRQ_HANDLER
682 select PM_GENERIC_DOMAINS if PM
685 Support for Renesas ARM SoC platforms using a non-multiplatform
686 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
692 select ARCH_MAY_HAVE_PC_FDC
693 select ARCH_SPARSEMEM_ENABLE
694 select ARCH_USES_GETTIMEOFFSET
698 select HAVE_PATA_PLATFORM
700 select NEED_MACH_IO_H
701 select NEED_MACH_MEMORY_H
705 On the Acorn Risc-PC, Linux can support the internal IDE disk and
706 CD-ROM interface, serial and parallel port, and the floppy drive.
710 select ARCH_HAS_CPUFREQ
712 select ARCH_REQUIRE_GPIOLIB
713 select ARCH_SPARSEMEM_ENABLE
718 select GENERIC_CLOCKEVENTS
721 select NEED_MACH_MEMORY_H
724 Support for StrongARM 11x0 based boards.
727 bool "Samsung S3C24XX SoCs"
728 select ARCH_HAS_CPUFREQ
729 select ARCH_REQUIRE_GPIOLIB
732 select CLKSRC_SAMSUNG_PWM
733 select GENERIC_CLOCKEVENTS
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select HAVE_S3C_RTC if RTC_CLASS
738 select MULTI_IRQ_HANDLER
739 select NEED_MACH_IO_H
742 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
743 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
744 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
745 Samsung SMDK2410 development board (and derivatives).
748 bool "Samsung S3C64XX"
749 select ARCH_HAS_CPUFREQ
750 select ARCH_REQUIRE_GPIOLIB
755 select CLKSRC_SAMSUNG_PWM
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select PM_GENERIC_DOMAINS if PM
767 select S3C_GPIO_TRACK
769 select SAMSUNG_WAKEMASK
770 select SAMSUNG_WDT_RESET
772 Samsung S3C64XX series based systems
775 bool "Samsung S5P6440 S5P6450"
778 select CLKSRC_SAMSUNG_PWM
780 select GENERIC_CLOCKEVENTS
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 select HAVE_S3C_RTC if RTC_CLASS
785 select NEED_MACH_GPIO_H
787 select SAMSUNG_WDT_RESET
789 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
793 bool "Samsung S5PC100"
794 select ARCH_REQUIRE_GPIOLIB
797 select CLKSRC_SAMSUNG_PWM
799 select GENERIC_CLOCKEVENTS
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select HAVE_S3C_RTC if RTC_CLASS
804 select NEED_MACH_GPIO_H
806 select SAMSUNG_WDT_RESET
808 Samsung S5PC100 series based systems
811 bool "Samsung S5PV210/S5PC110"
812 select ARCH_HAS_CPUFREQ
813 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARCH_SPARSEMEM_ENABLE
817 select CLKSRC_SAMSUNG_PWM
819 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select HAVE_S3C_RTC if RTC_CLASS
824 select NEED_MACH_GPIO_H
825 select NEED_MACH_MEMORY_H
828 Samsung S5PV210/S5PC110 series based systems
831 bool "Samsung EXYNOS"
832 select ARCH_HAS_CPUFREQ
833 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARCH_REQUIRE_GPIOLIB
835 select ARCH_SPARSEMEM_ENABLE
839 select GENERIC_CLOCKEVENTS
840 select HAVE_S3C2410_I2C if I2C
841 select HAVE_S3C2410_WATCHDOG if WATCHDOG
842 select HAVE_S3C_RTC if RTC_CLASS
843 select NEED_MACH_MEMORY_H
847 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
851 select ARCH_HAS_HOLES_MEMORYMODEL
852 select ARCH_REQUIRE_GPIOLIB
854 select GENERIC_ALLOCATOR
855 select GENERIC_CLOCKEVENTS
856 select GENERIC_IRQ_CHIP
862 Support for TI's DaVinci platform.
867 select ARCH_HAS_CPUFREQ
868 select ARCH_HAS_HOLES_MEMORYMODEL
870 select ARCH_REQUIRE_GPIOLIB
873 select GENERIC_CLOCKEVENTS
874 select GENERIC_IRQ_CHIP
877 select NEED_MACH_IO_H if PCCARD
878 select NEED_MACH_MEMORY_H
880 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
884 menu "Multiple platform selection"
885 depends on ARCH_MULTIPLATFORM
887 comment "CPU Core family selection"
890 bool "ARMv4 based platforms (FA526)"
891 depends on !ARCH_MULTI_V6_V7
892 select ARCH_MULTI_V4_V5
895 config ARCH_MULTI_V4T
896 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
897 depends on !ARCH_MULTI_V6_V7
898 select ARCH_MULTI_V4_V5
899 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
900 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
901 CPU_ARM925T || CPU_ARM940T)
904 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
905 depends on !ARCH_MULTI_V6_V7
906 select ARCH_MULTI_V4_V5
907 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
908 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
909 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
911 config ARCH_MULTI_V4_V5
915 bool "ARMv6 based platforms (ARM11)"
916 select ARCH_MULTI_V6_V7
920 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
922 select ARCH_MULTI_V6_V7
926 config ARCH_MULTI_V6_V7
928 select MIGHT_HAVE_CACHE_L2X0
930 config ARCH_MULTI_CPU_AUTO
931 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
937 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
941 select HAVE_ARM_ARCH_TIMER
944 # This is sorted alphabetically by mach-* pathname. However, plat-*
945 # Kconfigs may be included either alphabetically (according to the
946 # plat- suffix) or along side the corresponding mach-* source.
948 source "arch/arm/mach-mvebu/Kconfig"
950 source "arch/arm/mach-at91/Kconfig"
952 source "arch/arm/mach-bcm/Kconfig"
954 source "arch/arm/mach-berlin/Kconfig"
956 source "arch/arm/mach-clps711x/Kconfig"
958 source "arch/arm/mach-cns3xxx/Kconfig"
960 source "arch/arm/mach-davinci/Kconfig"
962 source "arch/arm/mach-dove/Kconfig"
964 source "arch/arm/mach-ep93xx/Kconfig"
966 source "arch/arm/mach-footbridge/Kconfig"
968 source "arch/arm/mach-gemini/Kconfig"
970 source "arch/arm/mach-highbank/Kconfig"
972 source "arch/arm/mach-hisi/Kconfig"
974 source "arch/arm/mach-integrator/Kconfig"
976 source "arch/arm/mach-iop32x/Kconfig"
978 source "arch/arm/mach-iop33x/Kconfig"
980 source "arch/arm/mach-iop13xx/Kconfig"
982 source "arch/arm/mach-ixp4xx/Kconfig"
984 source "arch/arm/mach-keystone/Kconfig"
986 source "arch/arm/mach-kirkwood/Kconfig"
988 source "arch/arm/mach-ks8695/Kconfig"
990 source "arch/arm/mach-msm/Kconfig"
992 source "arch/arm/mach-moxart/Kconfig"
994 source "arch/arm/mach-mv78xx0/Kconfig"
996 source "arch/arm/mach-imx/Kconfig"
998 source "arch/arm/mach-mxs/Kconfig"
1000 source "arch/arm/mach-netx/Kconfig"
1002 source "arch/arm/mach-nomadik/Kconfig"
1004 source "arch/arm/mach-nspire/Kconfig"
1006 source "arch/arm/plat-omap/Kconfig"
1008 source "arch/arm/mach-omap1/Kconfig"
1010 source "arch/arm/mach-omap2/Kconfig"
1012 source "arch/arm/mach-orion5x/Kconfig"
1014 source "arch/arm/mach-picoxcell/Kconfig"
1016 source "arch/arm/mach-pxa/Kconfig"
1017 source "arch/arm/plat-pxa/Kconfig"
1019 source "arch/arm/mach-mmp/Kconfig"
1021 source "arch/arm/mach-qcom/Kconfig"
1023 source "arch/arm/mach-realview/Kconfig"
1025 source "arch/arm/mach-rockchip/Kconfig"
1027 source "arch/arm/mach-sa1100/Kconfig"
1029 source "arch/arm/plat-samsung/Kconfig"
1031 source "arch/arm/mach-socfpga/Kconfig"
1033 source "arch/arm/mach-spear/Kconfig"
1035 source "arch/arm/mach-sti/Kconfig"
1037 source "arch/arm/mach-s3c24xx/Kconfig"
1039 source "arch/arm/mach-s3c64xx/Kconfig"
1041 source "arch/arm/mach-s5p64x0/Kconfig"
1043 source "arch/arm/mach-s5pc100/Kconfig"
1045 source "arch/arm/mach-s5pv210/Kconfig"
1047 source "arch/arm/mach-exynos/Kconfig"
1049 source "arch/arm/mach-shmobile/Kconfig"
1051 source "arch/arm/mach-sunxi/Kconfig"
1053 source "arch/arm/mach-prima2/Kconfig"
1055 source "arch/arm/mach-tegra/Kconfig"
1057 source "arch/arm/mach-u300/Kconfig"
1059 source "arch/arm/mach-ux500/Kconfig"
1061 source "arch/arm/mach-versatile/Kconfig"
1063 source "arch/arm/mach-vexpress/Kconfig"
1064 source "arch/arm/plat-versatile/Kconfig"
1066 source "arch/arm/mach-vt8500/Kconfig"
1068 source "arch/arm/mach-w90x900/Kconfig"
1070 source "arch/arm/mach-zynq/Kconfig"
1072 # Definitions to make life easier
1078 select GENERIC_CLOCKEVENTS
1084 select GENERIC_IRQ_CHIP
1087 config PLAT_ORION_LEGACY
1094 config PLAT_VERSATILE
1097 config ARM_TIMER_SP804
1100 select CLKSRC_OF if OF
1102 source "arch/arm/firmware/Kconfig"
1104 source arch/arm/mm/Kconfig
1108 default 16 if ARCH_EP93XX
1112 bool "Enable iWMMXt support" if !CPU_PJ4
1113 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1114 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1116 Enable support for iWMMXt context switching at run time if
1117 running on a CPU that supports it.
1119 config MULTI_IRQ_HANDLER
1122 Allow each machine to specify it's own IRQ handler at run time.
1125 source "arch/arm/Kconfig-nommu"
1128 config PJ4B_ERRATA_4742
1129 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1130 depends on CPU_PJ4B && MACH_ARMADA_370
1133 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1134 Event (WFE) IDLE states, a specific timing sensitivity exists between
1135 the retiring WFI/WFE instructions and the newly issued subsequent
1136 instructions. This sensitivity can result in a CPU hang scenario.
1138 The software must insert either a Data Synchronization Barrier (DSB)
1139 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1142 config ARM_ERRATA_326103
1143 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1146 Executing a SWP instruction to read-only memory does not set bit 11
1147 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1148 treat the access as a read, preventing a COW from occurring and
1149 causing the faulting task to livelock.
1151 config ARM_ERRATA_411920
1152 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1153 depends on CPU_V6 || CPU_V6K
1155 Invalidation of the Instruction Cache operation can
1156 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1157 It does not affect the MPCore. This option enables the ARM Ltd.
1158 recommended workaround.
1160 config ARM_ERRATA_430973
1161 bool "ARM errata: Stale prediction on replaced interworking branch"
1164 This option enables the workaround for the 430973 Cortex-A8
1165 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1166 interworking branch is replaced with another code sequence at the
1167 same virtual address, whether due to self-modifying code or virtual
1168 to physical address re-mapping, Cortex-A8 does not recover from the
1169 stale interworking branch prediction. This results in Cortex-A8
1170 executing the new code sequence in the incorrect ARM or Thumb state.
1171 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1172 and also flushes the branch target cache at every context switch.
1173 Note that setting specific bits in the ACTLR register may not be
1174 available in non-secure mode.
1176 config ARM_ERRATA_458693
1177 bool "ARM errata: Processor deadlock when a false hazard is created"
1179 depends on !ARCH_MULTIPLATFORM
1181 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1182 erratum. For very specific sequences of memory operations, it is
1183 possible for a hazard condition intended for a cache line to instead
1184 be incorrectly associated with a different cache line. This false
1185 hazard might then cause a processor deadlock. The workaround enables
1186 the L1 caching of the NEON accesses and disables the PLD instruction
1187 in the ACTLR register. Note that setting specific bits in the ACTLR
1188 register may not be available in non-secure mode.
1190 config ARM_ERRATA_460075
1191 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1193 depends on !ARCH_MULTIPLATFORM
1195 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1196 erratum. Any asynchronous access to the L2 cache may encounter a
1197 situation in which recent store transactions to the L2 cache are lost
1198 and overwritten with stale memory contents from external memory. The
1199 workaround disables the write-allocate mode for the L2 cache via the
1200 ACTLR register. Note that setting specific bits in the ACTLR register
1201 may not be available in non-secure mode.
1203 config ARM_ERRATA_742230
1204 bool "ARM errata: DMB operation may be faulty"
1205 depends on CPU_V7 && SMP
1206 depends on !ARCH_MULTIPLATFORM
1208 This option enables the workaround for the 742230 Cortex-A9
1209 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1210 between two write operations may not ensure the correct visibility
1211 ordering of the two writes. This workaround sets a specific bit in
1212 the diagnostic register of the Cortex-A9 which causes the DMB
1213 instruction to behave as a DSB, ensuring the correct behaviour of
1216 config ARM_ERRATA_742231
1217 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1218 depends on CPU_V7 && SMP
1219 depends on !ARCH_MULTIPLATFORM
1221 This option enables the workaround for the 742231 Cortex-A9
1222 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1223 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1224 accessing some data located in the same cache line, may get corrupted
1225 data due to bad handling of the address hazard when the line gets
1226 replaced from one of the CPUs at the same time as another CPU is
1227 accessing it. This workaround sets specific bits in the diagnostic
1228 register of the Cortex-A9 which reduces the linefill issuing
1229 capabilities of the processor.
1231 config PL310_ERRATA_588369
1232 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1233 depends on CACHE_L2X0
1235 The PL310 L2 cache controller implements three types of Clean &
1236 Invalidate maintenance operations: by Physical Address
1237 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1238 They are architecturally defined to behave as the execution of a
1239 clean operation followed immediately by an invalidate operation,
1240 both performing to the same memory location. This functionality
1241 is not correctly implemented in PL310 as clean lines are not
1242 invalidated as a result of these operations.
1244 config ARM_ERRATA_643719
1245 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1246 depends on CPU_V7 && SMP
1248 This option enables the workaround for the 643719 Cortex-A9 (prior to
1249 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1250 register returns zero when it should return one. The workaround
1251 corrects this value, ensuring cache maintenance operations which use
1252 it behave as intended and avoiding data corruption.
1254 config ARM_ERRATA_720789
1255 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1258 This option enables the workaround for the 720789 Cortex-A9 (prior to
1259 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1260 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1261 As a consequence of this erratum, some TLB entries which should be
1262 invalidated are not, resulting in an incoherency in the system page
1263 tables. The workaround changes the TLB flushing routines to invalidate
1264 entries regardless of the ASID.
1266 config PL310_ERRATA_727915
1267 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1268 depends on CACHE_L2X0
1270 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1271 operation (offset 0x7FC). This operation runs in background so that
1272 PL310 can handle normal accesses while it is in progress. Under very
1273 rare circumstances, due to this erratum, write data can be lost when
1274 PL310 treats a cacheable write transaction during a Clean &
1275 Invalidate by Way operation.
1277 config ARM_ERRATA_743622
1278 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1280 depends on !ARCH_MULTIPLATFORM
1282 This option enables the workaround for the 743622 Cortex-A9
1283 (r2p*) erratum. Under very rare conditions, a faulty
1284 optimisation in the Cortex-A9 Store Buffer may lead to data
1285 corruption. This workaround sets a specific bit in the diagnostic
1286 register of the Cortex-A9 which disables the Store Buffer
1287 optimisation, preventing the defect from occurring. This has no
1288 visible impact on the overall performance or power consumption of the
1291 config ARM_ERRATA_751472
1292 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1294 depends on !ARCH_MULTIPLATFORM
1296 This option enables the workaround for the 751472 Cortex-A9 (prior
1297 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1298 completion of a following broadcasted operation if the second
1299 operation is received by a CPU before the ICIALLUIS has completed,
1300 potentially leading to corrupted entries in the cache or TLB.
1302 config PL310_ERRATA_753970
1303 bool "PL310 errata: cache sync operation may be faulty"
1304 depends on CACHE_PL310
1306 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1308 Under some condition the effect of cache sync operation on
1309 the store buffer still remains when the operation completes.
1310 This means that the store buffer is always asked to drain and
1311 this prevents it from merging any further writes. The workaround
1312 is to replace the normal offset of cache sync operation (0x730)
1313 by another offset targeting an unmapped PL310 register 0x740.
1314 This has the same effect as the cache sync operation: store buffer
1315 drain and waiting for all buffers empty.
1317 config ARM_ERRATA_754322
1318 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1321 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1322 r3p*) erratum. A speculative memory access may cause a page table walk
1323 which starts prior to an ASID switch but completes afterwards. This
1324 can populate the micro-TLB with a stale entry which may be hit with
1325 the new ASID. This workaround places two dsb instructions in the mm
1326 switching code so that no page table walks can cross the ASID switch.
1328 config ARM_ERRATA_754327
1329 bool "ARM errata: no automatic Store Buffer drain"
1330 depends on CPU_V7 && SMP
1332 This option enables the workaround for the 754327 Cortex-A9 (prior to
1333 r2p0) erratum. The Store Buffer does not have any automatic draining
1334 mechanism and therefore a livelock may occur if an external agent
1335 continuously polls a memory location waiting to observe an update.
1336 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1337 written polling loops from denying visibility of updates to memory.
1339 config ARM_ERRATA_364296
1340 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1343 This options enables the workaround for the 364296 ARM1136
1344 r0p2 erratum (possible cache data corruption with
1345 hit-under-miss enabled). It sets the undocumented bit 31 in
1346 the auxiliary control register and the FI bit in the control
1347 register, thus disabling hit-under-miss without putting the
1348 processor into full low interrupt latency mode. ARM11MPCore
1351 config ARM_ERRATA_764369
1352 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1353 depends on CPU_V7 && SMP
1355 This option enables the workaround for erratum 764369
1356 affecting Cortex-A9 MPCore with two or more processors (all
1357 current revisions). Under certain timing circumstances, a data
1358 cache line maintenance operation by MVA targeting an Inner
1359 Shareable memory region may fail to proceed up to either the
1360 Point of Coherency or to the Point of Unification of the
1361 system. This workaround adds a DSB instruction before the
1362 relevant cache maintenance functions and sets a specific bit
1363 in the diagnostic control register of the SCU.
1365 config PL310_ERRATA_769419
1366 bool "PL310 errata: no automatic Store Buffer drain"
1367 depends on CACHE_L2X0
1369 On revisions of the PL310 prior to r3p2, the Store Buffer does
1370 not automatically drain. This can cause normal, non-cacheable
1371 writes to be retained when the memory system is idle, leading
1372 to suboptimal I/O performance for drivers using coherent DMA.
1373 This option adds a write barrier to the cpu_idle loop so that,
1374 on systems with an outer cache, the store buffer is drained
1377 config ARM_ERRATA_775420
1378 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1381 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1382 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1383 operation aborts with MMU exception, it might cause the processor
1384 to deadlock. This workaround puts DSB before executing ISB if
1385 an abort may occur on cache maintenance.
1387 config ARM_ERRATA_798181
1388 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1389 depends on CPU_V7 && SMP
1391 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1392 adequately shooting down all use of the old entries. This
1393 option enables the Linux kernel workaround for this erratum
1394 which sends an IPI to the CPUs that are running the same ASID
1395 as the one being invalidated.
1397 config ARM_ERRATA_773022
1398 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1401 This option enables the workaround for the 773022 Cortex-A15
1402 (up to r0p4) erratum. In certain rare sequences of code, the
1403 loop buffer may deliver incorrect instructions. This
1404 workaround disables the loop buffer to avoid the erratum.
1408 source "arch/arm/common/Kconfig"
1418 Find out whether you have ISA slots on your motherboard. ISA is the
1419 name of a bus system, i.e. the way the CPU talks to the other stuff
1420 inside your box. Other bus systems are PCI, EISA, MicroChannel
1421 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1422 newer boards don't support it. If you have ISA, say Y, otherwise N.
1424 # Select ISA DMA controller support
1429 # Select ISA DMA interface
1434 bool "PCI support" if MIGHT_HAVE_PCI
1436 Find out whether you have a PCI motherboard. PCI is the name of a
1437 bus system, i.e. the way the CPU talks to the other stuff inside
1438 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1439 VESA. If you have PCI, say Y, otherwise N.
1445 config PCI_NANOENGINE
1446 bool "BSE nanoEngine PCI support"
1447 depends on SA1100_NANOENGINE
1449 Enable PCI on the BSE nanoEngine board.
1454 config PCI_HOST_ITE8152
1456 depends on PCI && MACH_ARMCORE
1460 source "drivers/pci/Kconfig"
1461 source "drivers/pci/pcie/Kconfig"
1463 source "drivers/pcmcia/Kconfig"
1467 menu "Kernel Features"
1472 This option should be selected by machines which have an SMP-
1475 The only effect of this option is to make the SMP-related
1476 options available to the user for configuration.
1479 bool "Symmetric Multi-Processing"
1480 depends on CPU_V6K || CPU_V7
1481 depends on GENERIC_CLOCKEVENTS
1483 depends on MMU || ARM_MPU
1485 This enables support for systems with more than one CPU. If you have
1486 a system with only one CPU, say N. If you have a system with more
1487 than one CPU, say Y.
1489 If you say N here, the kernel will run on uni- and multiprocessor
1490 machines, but will use only one CPU of a multiprocessor machine. If
1491 you say Y here, the kernel will run on many, but not all,
1492 uniprocessor machines. On a uniprocessor machine, the kernel
1493 will run faster if you say N here.
1495 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1496 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1497 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1499 If you don't know what to do here, say N.
1502 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1503 depends on SMP && !XIP_KERNEL && MMU
1506 SMP kernels contain instructions which fail on non-SMP processors.
1507 Enabling this option allows the kernel to modify itself to make
1508 these instructions safe. Disabling it allows about 1K of space
1511 If you don't know what to do here, say Y.
1513 config ARM_CPU_TOPOLOGY
1514 bool "Support cpu topology definition"
1515 depends on SMP && CPU_V7
1518 Support ARM cpu topology definition. The MPIDR register defines
1519 affinity between processors which is then used to describe the cpu
1520 topology of an ARM System.
1523 bool "Multi-core scheduler support"
1524 depends on ARM_CPU_TOPOLOGY
1526 Multi-core scheduler support improves the CPU scheduler's decision
1527 making when dealing with multi-core CPU chips at a cost of slightly
1528 increased overhead in some places. If unsure say N here.
1531 bool "SMT scheduler support"
1532 depends on ARM_CPU_TOPOLOGY
1534 Improves the CPU scheduler's decision making when dealing with
1535 MultiThreading at a cost of slightly increased overhead in some
1536 places. If unsure say N here.
1541 This option enables support for the ARM system coherency unit
1543 config HAVE_ARM_ARCH_TIMER
1544 bool "Architected timer support"
1546 select ARM_ARCH_TIMER
1547 select GENERIC_CLOCKEVENTS
1549 This option enables support for the ARM architected timer
1554 select CLKSRC_OF if OF
1556 This options enables support for the ARM timer and watchdog unit
1559 bool "Multi-Cluster Power Management"
1560 depends on CPU_V7 && SMP
1562 This option provides the common power management infrastructure
1563 for (multi-)cluster based systems, such as big.LITTLE based
1567 bool "big.LITTLE support (Experimental)"
1568 depends on CPU_V7 && SMP
1571 This option enables support selections for the big.LITTLE
1572 system architecture.
1575 bool "big.LITTLE switcher support"
1576 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1578 select ARM_CPU_SUSPEND
1580 The big.LITTLE "switcher" provides the core functionality to
1581 transparently handle transition between a cluster of A15's
1582 and a cluster of A7's in a big.LITTLE system.
1584 config BL_SWITCHER_DUMMY_IF
1585 tristate "Simple big.LITTLE switcher user interface"
1586 depends on BL_SWITCHER && DEBUG_KERNEL
1588 This is a simple and dummy char dev interface to control
1589 the big.LITTLE switcher core code. It is meant for
1590 debugging purposes only.
1593 prompt "Memory split"
1597 Select the desired split between kernel and user memory.
1599 If you are not absolutely sure what you are doing, leave this
1603 bool "3G/1G user/kernel split"
1605 bool "2G/2G user/kernel split"
1607 bool "1G/3G user/kernel split"
1612 default PHYS_OFFSET if !MMU
1613 default 0x40000000 if VMSPLIT_1G
1614 default 0x80000000 if VMSPLIT_2G
1618 int "Maximum number of CPUs (2-32)"
1624 bool "Support for hot-pluggable CPUs"
1627 Say Y here to experiment with turning CPUs off and on. CPUs
1628 can be controlled through /sys/devices/system/cpu.
1631 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1634 Say Y here if you want Linux to communicate with system firmware
1635 implementing the PSCI specification for CPU-centric power
1636 management operations described in ARM document number ARM DEN
1637 0022A ("Power State Coordination Interface System Software on
1640 # The GPIO number here must be sorted by descending number. In case of
1641 # a multiplatform kernel, we just want the highest value required by the
1642 # selected platforms.
1645 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1646 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1647 default 392 if ARCH_U8500
1648 default 352 if ARCH_VT8500
1649 default 288 if ARCH_SUNXI
1650 default 264 if MACH_H4700
1653 Maximum number of GPIOs in the system.
1655 If unsure, leave the default value.
1657 source kernel/Kconfig.preempt
1661 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1662 ARCH_S5PV210 || ARCH_EXYNOS4
1663 default AT91_TIMER_HZ if ARCH_AT91
1664 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1668 depends on HZ_FIXED = 0
1669 prompt "Timer frequency"
1693 default HZ_FIXED if HZ_FIXED != 0
1694 default 100 if HZ_100
1695 default 200 if HZ_200
1696 default 250 if HZ_250
1697 default 300 if HZ_300
1698 default 500 if HZ_500
1702 def_bool HIGH_RES_TIMERS
1704 config THUMB2_KERNEL
1705 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1706 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1707 default y if CPU_THUMBONLY
1709 select ARM_ASM_UNIFIED
1712 By enabling this option, the kernel will be compiled in
1713 Thumb-2 mode. A compiler/assembler that understand the unified
1714 ARM-Thumb syntax is needed.
1718 config THUMB2_AVOID_R_ARM_THM_JUMP11
1719 bool "Work around buggy Thumb-2 short branch relocations in gas"
1720 depends on THUMB2_KERNEL && MODULES
1723 Various binutils versions can resolve Thumb-2 branches to
1724 locally-defined, preemptible global symbols as short-range "b.n"
1725 branch instructions.
1727 This is a problem, because there's no guarantee the final
1728 destination of the symbol, or any candidate locations for a
1729 trampoline, are within range of the branch. For this reason, the
1730 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1731 relocation in modules at all, and it makes little sense to add
1734 The symptom is that the kernel fails with an "unsupported
1735 relocation" error when loading some modules.
1737 Until fixed tools are available, passing
1738 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1739 code which hits this problem, at the cost of a bit of extra runtime
1740 stack usage in some cases.
1742 The problem is described in more detail at:
1743 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1745 Only Thumb-2 kernels are affected.
1747 Unless you are sure your tools don't have this problem, say Y.
1749 config ARM_ASM_UNIFIED
1753 bool "Use the ARM EABI to compile the kernel"
1755 This option allows for the kernel to be compiled using the latest
1756 ARM ABI (aka EABI). This is only useful if you are using a user
1757 space environment that is also compiled with EABI.
1759 Since there are major incompatibilities between the legacy ABI and
1760 EABI, especially with regard to structure member alignment, this
1761 option also changes the kernel syscall calling convention to
1762 disambiguate both ABIs and allow for backward compatibility support
1763 (selected with CONFIG_OABI_COMPAT).
1765 To use this you need GCC version 4.0.0 or later.
1768 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1769 depends on AEABI && !THUMB2_KERNEL
1771 This option preserves the old syscall interface along with the
1772 new (ARM EABI) one. It also provides a compatibility layer to
1773 intercept syscalls that have structure arguments which layout
1774 in memory differs between the legacy ABI and the new ARM EABI
1775 (only for non "thumb" binaries). This option adds a tiny
1776 overhead to all syscalls and produces a slightly larger kernel.
1778 The seccomp filter system will not be available when this is
1779 selected, since there is no way yet to sensibly distinguish
1780 between calling conventions during filtering.
1782 If you know you'll be using only pure EABI user space then you
1783 can say N here. If this option is not selected and you attempt
1784 to execute a legacy ABI binary then the result will be
1785 UNPREDICTABLE (in fact it can be predicted that it won't work
1786 at all). If in doubt say N.
1788 config ARCH_HAS_HOLES_MEMORYMODEL
1791 config ARCH_SPARSEMEM_ENABLE
1794 config ARCH_SPARSEMEM_DEFAULT
1795 def_bool ARCH_SPARSEMEM_ENABLE
1797 config ARCH_SELECT_MEMORY_MODEL
1798 def_bool ARCH_SPARSEMEM_ENABLE
1800 config HAVE_ARCH_PFN_VALID
1801 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1804 bool "High Memory Support"
1807 The address space of ARM processors is only 4 Gigabytes large
1808 and it has to accommodate user address space, kernel address
1809 space as well as some memory mapped IO. That means that, if you
1810 have a large amount of physical memory and/or IO, not all of the
1811 memory can be "permanently mapped" by the kernel. The physical
1812 memory that is not permanently mapped is called "high memory".
1814 Depending on the selected kernel/user memory split, minimum
1815 vmalloc space and actual amount of RAM, you may not need this
1816 option which should result in a slightly faster kernel.
1821 bool "Allocate 2nd-level pagetables from highmem"
1824 config HW_PERF_EVENTS
1825 bool "Enable hardware performance counter support for perf events"
1826 depends on PERF_EVENTS
1829 Enable hardware performance counter support for perf events. If
1830 disabled, perf events will use software events only.
1832 config SYS_SUPPORTS_HUGETLBFS
1836 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1840 config ARCH_WANT_GENERAL_HUGETLB
1845 config FORCE_MAX_ZONEORDER
1846 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1847 range 11 64 if ARCH_SHMOBILE_LEGACY
1848 default "12" if SOC_AM33XX
1849 default "9" if SA1111 || ARCH_EFM32
1852 The kernel memory allocator divides physically contiguous memory
1853 blocks into "zones", where each zone is a power of two number of
1854 pages. This option selects the largest power of two that the kernel
1855 keeps in the memory allocator. If you need to allocate very large
1856 blocks of physically contiguous memory, then you may need to
1857 increase this value.
1859 This config option is actually maximum order plus one. For example,
1860 a value of 11 means that the largest free memory block is 2^10 pages.
1862 config ALIGNMENT_TRAP
1864 depends on CPU_CP15_MMU
1865 default y if !ARCH_EBSA110
1866 select HAVE_PROC_CPU if PROC_FS
1868 ARM processors cannot fetch/store information which is not
1869 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1870 address divisible by 4. On 32-bit ARM processors, these non-aligned
1871 fetch/store instructions will be emulated in software if you say
1872 here, which has a severe performance impact. This is necessary for
1873 correct operation of some network protocols. With an IP-only
1874 configuration it is safe to say N, otherwise say Y.
1876 config UACCESS_WITH_MEMCPY
1877 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1879 default y if CPU_FEROCEON
1881 Implement faster copy_to_user and clear_user methods for CPU
1882 cores where a 8-word STM instruction give significantly higher
1883 memory write throughput than a sequence of individual 32bit stores.
1885 A possible side effect is a slight increase in scheduling latency
1886 between threads sharing the same address space if they invoke
1887 such copy operations with large buffers.
1889 However, if the CPU data cache is using a write-allocate mode,
1890 this option is unlikely to provide any performance gain.
1894 prompt "Enable seccomp to safely compute untrusted bytecode"
1896 This kernel feature is useful for number crunching applications
1897 that may need to compute untrusted bytecode during their
1898 execution. By using pipes or other transports made available to
1899 the process as file descriptors supporting the read/write
1900 syscalls, it's possible to isolate those applications in
1901 their own address space using seccomp. Once seccomp is
1902 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1903 and the task is only allowed to execute a few safe syscalls
1904 defined by each seccomp mode.
1917 bool "Xen guest support on ARM (EXPERIMENTAL)"
1918 depends on ARM && AEABI && OF
1919 depends on CPU_V7 && !CPU_V6
1920 depends on !GENERIC_ATOMIC64
1924 select ARCH_DMA_ADDR_T_64BIT
1926 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1933 bool "Flattened Device Tree support"
1936 select OF_EARLY_FLATTREE
1937 select OF_RESERVED_MEM
1939 Include support for flattened device tree machine descriptions.
1942 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1945 This is the traditional way of passing data to the kernel at boot
1946 time. If you are solely relying on the flattened device tree (or
1947 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1948 to remove ATAGS support from your kernel binary. If unsure,
1951 config DEPRECATED_PARAM_STRUCT
1952 bool "Provide old way to pass kernel parameters"
1955 This was deprecated in 2001 and announced to live on for 5 years.
1956 Some old boot loaders still use this way.
1958 # Compressed boot loader in ROM. Yes, we really want to ask about
1959 # TEXT and BSS so we preserve their values in the config files.
1960 config ZBOOT_ROM_TEXT
1961 hex "Compressed ROM boot loader base address"
1964 The physical address at which the ROM-able zImage is to be
1965 placed in the target. Platforms which normally make use of
1966 ROM-able zImage formats normally set this to a suitable
1967 value in their defconfig file.
1969 If ZBOOT_ROM is not enabled, this has no effect.
1971 config ZBOOT_ROM_BSS
1972 hex "Compressed ROM boot loader BSS address"
1975 The base address of an area of read/write memory in the target
1976 for the ROM-able zImage which must be available while the
1977 decompressor is running. It must be large enough to hold the
1978 entire decompressed kernel plus an additional 128 KiB.
1979 Platforms which normally make use of ROM-able zImage formats
1980 normally set this to a suitable value in their defconfig file.
1982 If ZBOOT_ROM is not enabled, this has no effect.
1985 bool "Compressed boot loader in ROM/flash"
1986 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1987 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1989 Say Y here if you intend to execute your compressed kernel image
1990 (zImage) directly from ROM or flash. If unsure, say N.
1993 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1994 depends on ZBOOT_ROM && ARCH_SH7372
1995 default ZBOOT_ROM_NONE
1997 Include experimental SD/MMC loading code in the ROM-able zImage.
1998 With this enabled it is possible to write the ROM-able zImage
1999 kernel image to an MMC or SD card and boot the kernel straight
2000 from the reset vector. At reset the processor Mask ROM will load
2001 the first part of the ROM-able zImage which in turn loads the
2002 rest the kernel image to RAM.
2004 config ZBOOT_ROM_NONE
2005 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2007 Do not load image from SD or MMC
2009 config ZBOOT_ROM_MMCIF
2010 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2012 Load image from MMCIF hardware block.
2014 config ZBOOT_ROM_SH_MOBILE_SDHI
2015 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2017 Load image from SDHI hardware block
2021 config ARM_APPENDED_DTB
2022 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2025 With this option, the boot code will look for a device tree binary
2026 (DTB) appended to zImage
2027 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2029 This is meant as a backward compatibility convenience for those
2030 systems with a bootloader that can't be upgraded to accommodate
2031 the documented boot protocol using a device tree.
2033 Beware that there is very little in terms of protection against
2034 this option being confused by leftover garbage in memory that might
2035 look like a DTB header after a reboot if no actual DTB is appended
2036 to zImage. Do not leave this option active in a production kernel
2037 if you don't intend to always append a DTB. Proper passing of the
2038 location into r2 of a bootloader provided DTB is always preferable
2041 config ARM_ATAG_DTB_COMPAT
2042 bool "Supplement the appended DTB with traditional ATAG information"
2043 depends on ARM_APPENDED_DTB
2045 Some old bootloaders can't be updated to a DTB capable one, yet
2046 they provide ATAGs with memory configuration, the ramdisk address,
2047 the kernel cmdline string, etc. Such information is dynamically
2048 provided by the bootloader and can't always be stored in a static
2049 DTB. To allow a device tree enabled kernel to be used with such
2050 bootloaders, this option allows zImage to extract the information
2051 from the ATAG list and store it at run time into the appended DTB.
2054 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2055 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2057 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2058 bool "Use bootloader kernel arguments if available"
2060 Uses the command-line options passed by the boot loader instead of
2061 the device tree bootargs property. If the boot loader doesn't provide
2062 any, the device tree bootargs property will be used.
2064 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2065 bool "Extend with bootloader kernel arguments"
2067 The command-line arguments provided by the boot loader will be
2068 appended to the the device tree bootargs property.
2073 string "Default kernel command string"
2076 On some architectures (EBSA110 and CATS), there is currently no way
2077 for the boot loader to pass arguments to the kernel. For these
2078 architectures, you should supply some command-line options at build
2079 time by entering them here. As a minimum, you should specify the
2080 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2083 prompt "Kernel command line type" if CMDLINE != ""
2084 default CMDLINE_FROM_BOOTLOADER
2087 config CMDLINE_FROM_BOOTLOADER
2088 bool "Use bootloader kernel arguments if available"
2090 Uses the command-line options passed by the boot loader. If
2091 the boot loader doesn't provide any, the default kernel command
2092 string provided in CMDLINE will be used.
2094 config CMDLINE_EXTEND
2095 bool "Extend bootloader kernel arguments"
2097 The command-line arguments provided by the boot loader will be
2098 appended to the default kernel command string.
2100 config CMDLINE_FORCE
2101 bool "Always use the default kernel command string"
2103 Always use the default kernel command string, even if the boot
2104 loader passes other arguments to the kernel.
2105 This is useful if you cannot or don't want to change the
2106 command-line options your boot loader passes to the kernel.
2110 bool "Kernel Execute-In-Place from ROM"
2111 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2113 Execute-In-Place allows the kernel to run from non-volatile storage
2114 directly addressable by the CPU, such as NOR flash. This saves RAM
2115 space since the text section of the kernel is not loaded from flash
2116 to RAM. Read-write sections, such as the data section and stack,
2117 are still copied to RAM. The XIP kernel is not compressed since
2118 it has to run directly from flash, so it will take more space to
2119 store it. The flash address used to link the kernel object files,
2120 and for storing it, is configuration dependent. Therefore, if you
2121 say Y here, you must know the proper physical address where to
2122 store the kernel image depending on your own flash memory usage.
2124 Also note that the make target becomes "make xipImage" rather than
2125 "make zImage" or "make Image". The final kernel binary to put in
2126 ROM memory will be arch/arm/boot/xipImage.
2130 config XIP_PHYS_ADDR
2131 hex "XIP Kernel Physical Location"
2132 depends on XIP_KERNEL
2133 default "0x00080000"
2135 This is the physical address in your flash memory the kernel will
2136 be linked for and stored to. This address is dependent on your
2140 bool "Kexec system call (EXPERIMENTAL)"
2141 depends on (!SMP || PM_SLEEP_SMP)
2143 kexec is a system call that implements the ability to shutdown your
2144 current kernel, and to start another kernel. It is like a reboot
2145 but it is independent of the system firmware. And like a reboot
2146 you can start any kernel with it, not just Linux.
2148 It is an ongoing process to be certain the hardware in a machine
2149 is properly shutdown, so do not be surprised if this code does not
2150 initially work for you.
2153 bool "Export atags in procfs"
2154 depends on ATAGS && KEXEC
2157 Should the atags used to boot the kernel be exported in an "atags"
2158 file in procfs. Useful with kexec.
2161 bool "Build kdump crash kernel (EXPERIMENTAL)"
2163 Generate crash dump after being started by kexec. This should
2164 be normally only set in special crash dump kernels which are
2165 loaded in the main kernel with kexec-tools into a specially
2166 reserved region and then later executed after a crash by
2167 kdump/kexec. The crash dump kernel must be compiled to a
2168 memory address not used by the main kernel
2170 For more details see Documentation/kdump/kdump.txt
2172 config AUTO_ZRELADDR
2173 bool "Auto calculation of the decompressed kernel image address"
2175 ZRELADDR is the physical address where the decompressed kernel
2176 image will be placed. If AUTO_ZRELADDR is selected, the address
2177 will be determined at run-time by masking the current IP with
2178 0xf8000000. This assumes the zImage being placed in the first 128MB
2179 from start of memory.
2183 menu "CPU Power Management"
2186 source "drivers/cpufreq/Kconfig"
2189 source "drivers/cpuidle/Kconfig"
2193 menu "Floating point emulation"
2195 comment "At least one emulation must be selected"
2198 bool "NWFPE math emulation"
2199 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2201 Say Y to include the NWFPE floating point emulator in the kernel.
2202 This is necessary to run most binaries. Linux does not currently
2203 support floating point hardware so you need to say Y here even if
2204 your machine has an FPA or floating point co-processor podule.
2206 You may say N here if you are going to load the Acorn FPEmulator
2207 early in the bootup.
2210 bool "Support extended precision"
2211 depends on FPE_NWFPE
2213 Say Y to include 80-bit support in the kernel floating-point
2214 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2215 Note that gcc does not generate 80-bit operations by default,
2216 so in most cases this option only enlarges the size of the
2217 floating point emulator without any good reason.
2219 You almost surely want to say N here.
2222 bool "FastFPE math emulation (EXPERIMENTAL)"
2223 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2225 Say Y here to include the FAST floating point emulator in the kernel.
2226 This is an experimental much faster emulator which now also has full
2227 precision for the mantissa. It does not support any exceptions.
2228 It is very simple, and approximately 3-6 times faster than NWFPE.
2230 It should be sufficient for most programs. It may be not suitable
2231 for scientific calculations, but you have to check this for yourself.
2232 If you do not feel you need a faster FP emulation you should better
2236 bool "VFP-format floating point maths"
2237 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2239 Say Y to include VFP support code in the kernel. This is needed
2240 if your hardware includes a VFP unit.
2242 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2243 release notes and additional status information.
2245 Say N if your target does not have VFP hardware.
2253 bool "Advanced SIMD (NEON) Extension support"
2254 depends on VFPv3 && CPU_V7
2256 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2259 config KERNEL_MODE_NEON
2260 bool "Support for NEON in kernel mode"
2261 depends on NEON && AEABI
2263 Say Y to include support for NEON in kernel mode.
2267 menu "Userspace binary formats"
2269 source "fs/Kconfig.binfmt"
2272 tristate "RISC OS personality"
2275 Say Y here to include the kernel code necessary if you want to run
2276 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2277 experimental; if this sounds frightening, say N and sleep in peace.
2278 You can also say M here to compile this support as a module (which
2279 will be called arthur).
2283 menu "Power management options"
2285 source "kernel/power/Kconfig"
2287 config ARCH_SUSPEND_POSSIBLE
2288 depends on !ARCH_S5PC100
2289 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2290 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2293 config ARM_CPU_SUSPEND
2298 source "net/Kconfig"
2300 source "drivers/Kconfig"
2304 source "arch/arm/Kconfig.debug"
2306 source "security/Kconfig"
2308 source "crypto/Kconfig"
2310 source "lib/Kconfig"
2312 source "arch/arm/kvm/Kconfig"