4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
86 select ARCH_HAS_SG_CHAIN
89 config NEED_SG_DMA_LENGTH
92 config ARM_DMA_USE_IOMMU
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_SUPPORTS_UPROBES
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_GPIO_H
253 Select this when mach/gpio.h is required to provide special
254 definitions for this platform. The need for mach/gpio.h should
255 be avoided when possible.
257 config NEED_MACH_IO_H
260 Select this when mach/io.h is required to provide special
261 definitions for this platform. The need for mach/io.h should
262 be avoided when possible.
264 config NEED_MACH_MEMORY_H
267 Select this when mach/memory.h is required to provide special
268 definitions for this platform. The need for mach/memory.h should
269 be avoided when possible.
272 hex "Physical address of main memory" if MMU
273 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
274 default DRAM_BASE if !MMU
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 source "init/Kconfig"
285 source "kernel/Kconfig.freezer"
290 bool "MMU-based Paged Memory Management Support"
293 Select if you want MMU-based virtualised addressing space
294 support by paged memory management. If unsure, say 'Y'.
297 # The "ARM system type" choice list is ordered alphabetically by option
298 # text. Please add new entries in the option alphabetic order.
301 prompt "ARM system type"
302 default ARCH_VERSATILE if !MMU
303 default ARCH_MULTIPLATFORM if MMU
305 config ARCH_MULTIPLATFORM
306 bool "Allow multiple platforms to be selected"
308 select ARCH_WANT_OPTIONAL_GPIOLIB
309 select ARM_HAS_SG_CHAIN
310 select ARM_PATCH_PHYS_VIRT
314 select GENERIC_CLOCKEVENTS
315 select MIGHT_HAVE_PCI
316 select MULTI_IRQ_HANDLER
320 config ARCH_INTEGRATOR
321 bool "ARM Ltd. Integrator family"
322 select ARCH_HAS_CPUFREQ
324 select ARM_PATCH_PHYS_VIRT
327 select COMMON_CLK_VERSATILE
328 select GENERIC_CLOCKEVENTS
331 select MULTI_IRQ_HANDLER
332 select NEED_MACH_MEMORY_H
333 select PLAT_VERSATILE
336 select VERSATILE_FPGA_IRQ
338 Support for ARM's Integrator platform.
341 bool "ARM Ltd. RealView family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
346 select COMMON_CLK_VERSATILE
347 select GENERIC_CLOCKEVENTS
348 select GPIO_PL061 if GPIOLIB
350 select NEED_MACH_MEMORY_H
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_CLCD
354 This enables support for ARM Ltd RealView boards.
356 config ARCH_VERSATILE
357 bool "ARM Ltd. Versatile family"
358 select ARCH_WANT_OPTIONAL_GPIOLIB
360 select ARM_TIMER_SP804
363 select GENERIC_CLOCKEVENTS
364 select HAVE_MACH_CLKDEV
366 select PLAT_VERSATILE
367 select PLAT_VERSATILE_CLCD
368 select PLAT_VERSATILE_CLOCK
369 select VERSATILE_FPGA_IRQ
371 This enables support for ARM Ltd Versatile board.
375 select ARCH_REQUIRE_GPIOLIB
378 select NEED_MACH_IO_H if PCCARD
380 select PINCTRL_AT91 if USE_OF
382 This enables support for systems based on Atmel
383 AT91RM9200 and AT91SAM9* processors.
386 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
387 select ARCH_REQUIRE_GPIOLIB
392 select GENERIC_CLOCKEVENTS
395 Support for Cirrus Logic 711x/721x/731x based boards.
398 bool "Cortina Systems Gemini"
399 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
404 Support for the Cortina Systems Gemini family SoCs
408 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_IO_H
412 select NEED_MACH_MEMORY_H
415 This is an evaluation board for the StrongARM processor available
416 from Digital. It has limited hardware on-board, including an
417 Ethernet interface, two PCMCIA sockets, two serial ports and a
421 bool "Energy Micro efm32"
423 select ARCH_REQUIRE_GPIOLIB
429 select GENERIC_CLOCKEVENTS
435 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
440 select ARCH_HAS_HOLES_MEMORYMODEL
441 select ARCH_REQUIRE_GPIOLIB
442 select ARCH_USES_GETTIMEOFFSET
447 select NEED_MACH_MEMORY_H
449 This enables support for the Cirrus EP93xx series of CPUs.
451 config ARCH_FOOTBRIDGE
455 select GENERIC_CLOCKEVENTS
457 select NEED_MACH_IO_H if !MMU
458 select NEED_MACH_MEMORY_H
460 Support for systems based on the DC21285 companion chip
461 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
464 bool "Hilscher NetX based"
468 select GENERIC_CLOCKEVENTS
470 This enables support for systems based on the Hilscher NetX Soc
476 select NEED_MACH_MEMORY_H
477 select NEED_RET_TO_USER
483 Support for Intel's IOP13XX (XScale) family of processors.
488 select ARCH_REQUIRE_GPIOLIB
491 select NEED_RET_TO_USER
495 Support for Intel's 80219 and IOP32X (XScale) family of
501 select ARCH_REQUIRE_GPIOLIB
504 select NEED_RET_TO_USER
508 Support for Intel's IOP33X (XScale) family of processors.
513 select ARCH_HAS_DMA_SET_COHERENT_MASK
514 select ARCH_REQUIRE_GPIOLIB
515 select ARCH_SUPPORTS_BIG_ENDIAN
518 select DMABOUNCE if PCI
519 select GENERIC_CLOCKEVENTS
520 select MIGHT_HAVE_PCI
521 select NEED_MACH_IO_H
522 select USB_EHCI_BIG_ENDIAN_DESC
523 select USB_EHCI_BIG_ENDIAN_MMIO
525 Support for Intel's IXP4XX (XScale) family of processors.
529 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
532 select MIGHT_HAVE_PCI
536 select PLAT_ORION_LEGACY
538 Support for the Marvell Dove SoC 88AP510
541 bool "Marvell Kirkwood"
542 select ARCH_HAS_CPUFREQ
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
550 select PINCTRL_KIRKWOOD
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Kirkwood series SoCs:
554 88F6180, 88F6192 and 88F6281.
557 bool "Marvell MV78xx0"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
563 select PLAT_ORION_LEGACY
565 Support for the following Marvell MV78xx0 series SoCs:
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
576 select PLAT_ORION_LEGACY
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
583 bool "Marvell PXA168/910/MMP2"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
591 select MULTI_IRQ_HANDLER
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
636 Support for the NXP LPC32XX family of processors
639 bool "PXA2xx/PXA3xx-based"
641 select ARCH_HAS_CPUFREQ
643 select ARCH_REQUIRE_GPIOLIB
644 select ARM_CPU_SUSPEND if PM
648 select GENERIC_CLOCKEVENTS
651 select MULTI_IRQ_HANDLER
655 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
658 bool "Qualcomm MSM (non-multiplatform)"
659 select ARCH_REQUIRE_GPIOLIB
661 select GENERIC_CLOCKEVENTS
663 Support for Qualcomm MSM/QSD based systems. This runs on the
664 apps processor of the MSM/QSD and depends on a shared memory
665 interface to the modem processor which runs the baseband
666 stack and controls some vital subsystems
667 (clock and power control, etc).
669 config ARCH_SHMOBILE_LEGACY
670 bool "Renesas ARM SoCs (non-multiplatform)"
672 select ARM_PATCH_PHYS_VIRT
674 select GENERIC_CLOCKEVENTS
675 select HAVE_ARM_SCU if SMP
676 select HAVE_ARM_TWD if SMP
677 select HAVE_MACH_CLKDEV
679 select MIGHT_HAVE_CACHE_L2X0
680 select MULTI_IRQ_HANDLER
683 select PM_GENERIC_DOMAINS if PM
686 Support for Renesas ARM SoC platforms using a non-multiplatform
687 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
693 select ARCH_MAY_HAVE_PC_FDC
694 select ARCH_SPARSEMEM_ENABLE
695 select ARCH_USES_GETTIMEOFFSET
699 select HAVE_PATA_PLATFORM
701 select NEED_MACH_IO_H
702 select NEED_MACH_MEMORY_H
706 On the Acorn Risc-PC, Linux can support the internal IDE disk and
707 CD-ROM interface, serial and parallel port, and the floppy drive.
711 select ARCH_HAS_CPUFREQ
713 select ARCH_REQUIRE_GPIOLIB
714 select ARCH_SPARSEMEM_ENABLE
719 select GENERIC_CLOCKEVENTS
722 select NEED_MACH_MEMORY_H
725 Support for StrongARM 11x0 based boards.
728 bool "Samsung S3C24XX SoCs"
729 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
734 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select HAVE_S3C_RTC if RTC_CLASS
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H
743 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
744 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
745 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
746 Samsung SMDK2410 development board (and derivatives).
749 bool "Samsung S3C64XX"
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
756 select CLKSRC_SAMSUNG_PWM
757 select COMMON_CLK_SAMSUNG
759 select GENERIC_CLOCKEVENTS
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 select PM_GENERIC_DOMAINS if PM
768 select S3C_GPIO_TRACK
770 select SAMSUNG_WAKEMASK
771 select SAMSUNG_WDT_RESET
773 Samsung S3C64XX series based systems
776 bool "Samsung S5P6440 S5P6450"
779 select CLKSRC_SAMSUNG_PWM
781 select GENERIC_CLOCKEVENTS
783 select HAVE_S3C2410_I2C if I2C
784 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 select HAVE_S3C_RTC if RTC_CLASS
786 select NEED_MACH_GPIO_H
788 select SAMSUNG_WDT_RESET
790 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
794 bool "Samsung S5PC100"
795 select ARCH_REQUIRE_GPIOLIB
798 select CLKSRC_SAMSUNG_PWM
800 select GENERIC_CLOCKEVENTS
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select HAVE_S3C_RTC if RTC_CLASS
805 select NEED_MACH_GPIO_H
807 select SAMSUNG_WDT_RESET
809 Samsung S5PC100 series based systems
812 bool "Samsung S5PV210/S5PC110"
813 select ARCH_HAS_CPUFREQ
814 select ARCH_HAS_HOLES_MEMORYMODEL
815 select ARCH_SPARSEMEM_ENABLE
818 select CLKSRC_SAMSUNG_PWM
820 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_GPIO_H
826 select NEED_MACH_MEMORY_H
829 Samsung S5PV210/S5PC110 series based systems
833 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARCH_REQUIRE_GPIOLIB
836 select GENERIC_ALLOCATOR
837 select GENERIC_CLOCKEVENTS
838 select GENERIC_IRQ_CHIP
844 Support for TI's DaVinci platform.
849 select ARCH_HAS_CPUFREQ
850 select ARCH_HAS_HOLES_MEMORYMODEL
852 select ARCH_REQUIRE_GPIOLIB
855 select GENERIC_CLOCKEVENTS
856 select GENERIC_IRQ_CHIP
859 select NEED_MACH_IO_H if PCCARD
860 select NEED_MACH_MEMORY_H
862 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
866 menu "Multiple platform selection"
867 depends on ARCH_MULTIPLATFORM
869 comment "CPU Core family selection"
872 bool "ARMv4 based platforms (FA526)"
873 depends on !ARCH_MULTI_V6_V7
874 select ARCH_MULTI_V4_V5
877 config ARCH_MULTI_V4T
878 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
879 depends on !ARCH_MULTI_V6_V7
880 select ARCH_MULTI_V4_V5
881 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
882 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
883 CPU_ARM925T || CPU_ARM940T)
886 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
887 depends on !ARCH_MULTI_V6_V7
888 select ARCH_MULTI_V4_V5
889 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
890 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
891 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
893 config ARCH_MULTI_V4_V5
897 bool "ARMv6 based platforms (ARM11)"
898 select ARCH_MULTI_V6_V7
902 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
904 select ARCH_MULTI_V6_V7
908 config ARCH_MULTI_V6_V7
910 select MIGHT_HAVE_CACHE_L2X0
912 config ARCH_MULTI_CPU_AUTO
913 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
919 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
923 select HAVE_ARM_ARCH_TIMER
926 # This is sorted alphabetically by mach-* pathname. However, plat-*
927 # Kconfigs may be included either alphabetically (according to the
928 # plat- suffix) or along side the corresponding mach-* source.
930 source "arch/arm/mach-mvebu/Kconfig"
932 source "arch/arm/mach-at91/Kconfig"
934 source "arch/arm/mach-axxia/Kconfig"
936 source "arch/arm/mach-bcm/Kconfig"
938 source "arch/arm/mach-berlin/Kconfig"
940 source "arch/arm/mach-clps711x/Kconfig"
942 source "arch/arm/mach-cns3xxx/Kconfig"
944 source "arch/arm/mach-davinci/Kconfig"
946 source "arch/arm/mach-dove/Kconfig"
948 source "arch/arm/mach-ep93xx/Kconfig"
950 source "arch/arm/mach-footbridge/Kconfig"
952 source "arch/arm/mach-gemini/Kconfig"
954 source "arch/arm/mach-highbank/Kconfig"
956 source "arch/arm/mach-hisi/Kconfig"
958 source "arch/arm/mach-integrator/Kconfig"
960 source "arch/arm/mach-iop32x/Kconfig"
962 source "arch/arm/mach-iop33x/Kconfig"
964 source "arch/arm/mach-iop13xx/Kconfig"
966 source "arch/arm/mach-ixp4xx/Kconfig"
968 source "arch/arm/mach-keystone/Kconfig"
970 source "arch/arm/mach-kirkwood/Kconfig"
972 source "arch/arm/mach-ks8695/Kconfig"
974 source "arch/arm/mach-msm/Kconfig"
976 source "arch/arm/mach-moxart/Kconfig"
978 source "arch/arm/mach-mv78xx0/Kconfig"
980 source "arch/arm/mach-imx/Kconfig"
982 source "arch/arm/mach-mxs/Kconfig"
984 source "arch/arm/mach-netx/Kconfig"
986 source "arch/arm/mach-nomadik/Kconfig"
988 source "arch/arm/mach-nspire/Kconfig"
990 source "arch/arm/plat-omap/Kconfig"
992 source "arch/arm/mach-omap1/Kconfig"
994 source "arch/arm/mach-omap2/Kconfig"
996 source "arch/arm/mach-orion5x/Kconfig"
998 source "arch/arm/mach-picoxcell/Kconfig"
1000 source "arch/arm/mach-pxa/Kconfig"
1001 source "arch/arm/plat-pxa/Kconfig"
1003 source "arch/arm/mach-mmp/Kconfig"
1005 source "arch/arm/mach-qcom/Kconfig"
1007 source "arch/arm/mach-realview/Kconfig"
1009 source "arch/arm/mach-rockchip/Kconfig"
1011 source "arch/arm/mach-sa1100/Kconfig"
1013 source "arch/arm/plat-samsung/Kconfig"
1015 source "arch/arm/mach-socfpga/Kconfig"
1017 source "arch/arm/mach-spear/Kconfig"
1019 source "arch/arm/mach-sti/Kconfig"
1021 source "arch/arm/mach-s3c24xx/Kconfig"
1023 source "arch/arm/mach-s3c64xx/Kconfig"
1025 source "arch/arm/mach-s5p64x0/Kconfig"
1027 source "arch/arm/mach-s5pc100/Kconfig"
1029 source "arch/arm/mach-s5pv210/Kconfig"
1031 source "arch/arm/mach-exynos/Kconfig"
1033 source "arch/arm/mach-shmobile/Kconfig"
1035 source "arch/arm/mach-sunxi/Kconfig"
1037 source "arch/arm/mach-prima2/Kconfig"
1039 source "arch/arm/mach-tegra/Kconfig"
1041 source "arch/arm/mach-u300/Kconfig"
1043 source "arch/arm/mach-ux500/Kconfig"
1045 source "arch/arm/mach-versatile/Kconfig"
1047 source "arch/arm/mach-vexpress/Kconfig"
1048 source "arch/arm/plat-versatile/Kconfig"
1050 source "arch/arm/mach-vt8500/Kconfig"
1052 source "arch/arm/mach-w90x900/Kconfig"
1054 source "arch/arm/mach-zynq/Kconfig"
1056 # Definitions to make life easier
1062 select GENERIC_CLOCKEVENTS
1068 select GENERIC_IRQ_CHIP
1071 config PLAT_ORION_LEGACY
1078 config PLAT_VERSATILE
1081 config ARM_TIMER_SP804
1084 select CLKSRC_OF if OF
1086 source "arch/arm/firmware/Kconfig"
1088 source arch/arm/mm/Kconfig
1092 default 16 if ARCH_EP93XX
1096 bool "Enable iWMMXt support"
1097 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1098 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1100 Enable support for iWMMXt context switching at run time if
1101 running on a CPU that supports it.
1103 config MULTI_IRQ_HANDLER
1106 Allow each machine to specify it's own IRQ handler at run time.
1109 source "arch/arm/Kconfig-nommu"
1112 config PJ4B_ERRATA_4742
1113 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1114 depends on CPU_PJ4B && MACH_ARMADA_370
1117 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1118 Event (WFE) IDLE states, a specific timing sensitivity exists between
1119 the retiring WFI/WFE instructions and the newly issued subsequent
1120 instructions. This sensitivity can result in a CPU hang scenario.
1122 The software must insert either a Data Synchronization Barrier (DSB)
1123 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1126 config ARM_ERRATA_326103
1127 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1130 Executing a SWP instruction to read-only memory does not set bit 11
1131 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1132 treat the access as a read, preventing a COW from occurring and
1133 causing the faulting task to livelock.
1135 config ARM_ERRATA_411920
1136 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1137 depends on CPU_V6 || CPU_V6K
1139 Invalidation of the Instruction Cache operation can
1140 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1141 It does not affect the MPCore. This option enables the ARM Ltd.
1142 recommended workaround.
1144 config ARM_ERRATA_430973
1145 bool "ARM errata: Stale prediction on replaced interworking branch"
1148 This option enables the workaround for the 430973 Cortex-A8
1149 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1150 interworking branch is replaced with another code sequence at the
1151 same virtual address, whether due to self-modifying code or virtual
1152 to physical address re-mapping, Cortex-A8 does not recover from the
1153 stale interworking branch prediction. This results in Cortex-A8
1154 executing the new code sequence in the incorrect ARM or Thumb state.
1155 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1156 and also flushes the branch target cache at every context switch.
1157 Note that setting specific bits in the ACTLR register may not be
1158 available in non-secure mode.
1160 config ARM_ERRATA_458693
1161 bool "ARM errata: Processor deadlock when a false hazard is created"
1163 depends on !ARCH_MULTIPLATFORM
1165 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1166 erratum. For very specific sequences of memory operations, it is
1167 possible for a hazard condition intended for a cache line to instead
1168 be incorrectly associated with a different cache line. This false
1169 hazard might then cause a processor deadlock. The workaround enables
1170 the L1 caching of the NEON accesses and disables the PLD instruction
1171 in the ACTLR register. Note that setting specific bits in the ACTLR
1172 register may not be available in non-secure mode.
1174 config ARM_ERRATA_460075
1175 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1177 depends on !ARCH_MULTIPLATFORM
1179 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1180 erratum. Any asynchronous access to the L2 cache may encounter a
1181 situation in which recent store transactions to the L2 cache are lost
1182 and overwritten with stale memory contents from external memory. The
1183 workaround disables the write-allocate mode for the L2 cache via the
1184 ACTLR register. Note that setting specific bits in the ACTLR register
1185 may not be available in non-secure mode.
1187 config ARM_ERRATA_742230
1188 bool "ARM errata: DMB operation may be faulty"
1189 depends on CPU_V7 && SMP
1190 depends on !ARCH_MULTIPLATFORM
1192 This option enables the workaround for the 742230 Cortex-A9
1193 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1194 between two write operations may not ensure the correct visibility
1195 ordering of the two writes. This workaround sets a specific bit in
1196 the diagnostic register of the Cortex-A9 which causes the DMB
1197 instruction to behave as a DSB, ensuring the correct behaviour of
1200 config ARM_ERRATA_742231
1201 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1202 depends on CPU_V7 && SMP
1203 depends on !ARCH_MULTIPLATFORM
1205 This option enables the workaround for the 742231 Cortex-A9
1206 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1207 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1208 accessing some data located in the same cache line, may get corrupted
1209 data due to bad handling of the address hazard when the line gets
1210 replaced from one of the CPUs at the same time as another CPU is
1211 accessing it. This workaround sets specific bits in the diagnostic
1212 register of the Cortex-A9 which reduces the linefill issuing
1213 capabilities of the processor.
1215 config ARM_ERRATA_643719
1216 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1217 depends on CPU_V7 && SMP
1219 This option enables the workaround for the 643719 Cortex-A9 (prior to
1220 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1221 register returns zero when it should return one. The workaround
1222 corrects this value, ensuring cache maintenance operations which use
1223 it behave as intended and avoiding data corruption.
1225 config ARM_ERRATA_720789
1226 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1229 This option enables the workaround for the 720789 Cortex-A9 (prior to
1230 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1231 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1232 As a consequence of this erratum, some TLB entries which should be
1233 invalidated are not, resulting in an incoherency in the system page
1234 tables. The workaround changes the TLB flushing routines to invalidate
1235 entries regardless of the ASID.
1237 config ARM_ERRATA_743622
1238 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1240 depends on !ARCH_MULTIPLATFORM
1242 This option enables the workaround for the 743622 Cortex-A9
1243 (r2p*) erratum. Under very rare conditions, a faulty
1244 optimisation in the Cortex-A9 Store Buffer may lead to data
1245 corruption. This workaround sets a specific bit in the diagnostic
1246 register of the Cortex-A9 which disables the Store Buffer
1247 optimisation, preventing the defect from occurring. This has no
1248 visible impact on the overall performance or power consumption of the
1251 config ARM_ERRATA_751472
1252 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1254 depends on !ARCH_MULTIPLATFORM
1256 This option enables the workaround for the 751472 Cortex-A9 (prior
1257 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1258 completion of a following broadcasted operation if the second
1259 operation is received by a CPU before the ICIALLUIS has completed,
1260 potentially leading to corrupted entries in the cache or TLB.
1262 config ARM_ERRATA_754322
1263 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1266 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1267 r3p*) erratum. A speculative memory access may cause a page table walk
1268 which starts prior to an ASID switch but completes afterwards. This
1269 can populate the micro-TLB with a stale entry which may be hit with
1270 the new ASID. This workaround places two dsb instructions in the mm
1271 switching code so that no page table walks can cross the ASID switch.
1273 config ARM_ERRATA_754327
1274 bool "ARM errata: no automatic Store Buffer drain"
1275 depends on CPU_V7 && SMP
1277 This option enables the workaround for the 754327 Cortex-A9 (prior to
1278 r2p0) erratum. The Store Buffer does not have any automatic draining
1279 mechanism and therefore a livelock may occur if an external agent
1280 continuously polls a memory location waiting to observe an update.
1281 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1282 written polling loops from denying visibility of updates to memory.
1284 config ARM_ERRATA_364296
1285 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1288 This options enables the workaround for the 364296 ARM1136
1289 r0p2 erratum (possible cache data corruption with
1290 hit-under-miss enabled). It sets the undocumented bit 31 in
1291 the auxiliary control register and the FI bit in the control
1292 register, thus disabling hit-under-miss without putting the
1293 processor into full low interrupt latency mode. ARM11MPCore
1296 config ARM_ERRATA_764369
1297 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1298 depends on CPU_V7 && SMP
1300 This option enables the workaround for erratum 764369
1301 affecting Cortex-A9 MPCore with two or more processors (all
1302 current revisions). Under certain timing circumstances, a data
1303 cache line maintenance operation by MVA targeting an Inner
1304 Shareable memory region may fail to proceed up to either the
1305 Point of Coherency or to the Point of Unification of the
1306 system. This workaround adds a DSB instruction before the
1307 relevant cache maintenance functions and sets a specific bit
1308 in the diagnostic control register of the SCU.
1310 config ARM_ERRATA_775420
1311 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1314 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1315 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1316 operation aborts with MMU exception, it might cause the processor
1317 to deadlock. This workaround puts DSB before executing ISB if
1318 an abort may occur on cache maintenance.
1320 config ARM_ERRATA_798181
1321 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1322 depends on CPU_V7 && SMP
1324 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1325 adequately shooting down all use of the old entries. This
1326 option enables the Linux kernel workaround for this erratum
1327 which sends an IPI to the CPUs that are running the same ASID
1328 as the one being invalidated.
1330 config ARM_ERRATA_773022
1331 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1334 This option enables the workaround for the 773022 Cortex-A15
1335 (up to r0p4) erratum. In certain rare sequences of code, the
1336 loop buffer may deliver incorrect instructions. This
1337 workaround disables the loop buffer to avoid the erratum.
1341 source "arch/arm/common/Kconfig"
1351 Find out whether you have ISA slots on your motherboard. ISA is the
1352 name of a bus system, i.e. the way the CPU talks to the other stuff
1353 inside your box. Other bus systems are PCI, EISA, MicroChannel
1354 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1355 newer boards don't support it. If you have ISA, say Y, otherwise N.
1357 # Select ISA DMA controller support
1362 # Select ISA DMA interface
1367 bool "PCI support" if MIGHT_HAVE_PCI
1369 Find out whether you have a PCI motherboard. PCI is the name of a
1370 bus system, i.e. the way the CPU talks to the other stuff inside
1371 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1372 VESA. If you have PCI, say Y, otherwise N.
1378 config PCI_NANOENGINE
1379 bool "BSE nanoEngine PCI support"
1380 depends on SA1100_NANOENGINE
1382 Enable PCI on the BSE nanoEngine board.
1387 config PCI_HOST_ITE8152
1389 depends on PCI && MACH_ARMCORE
1393 source "drivers/pci/Kconfig"
1394 source "drivers/pci/pcie/Kconfig"
1396 source "drivers/pcmcia/Kconfig"
1400 menu "Kernel Features"
1405 This option should be selected by machines which have an SMP-
1408 The only effect of this option is to make the SMP-related
1409 options available to the user for configuration.
1412 bool "Symmetric Multi-Processing"
1413 depends on CPU_V6K || CPU_V7
1414 depends on GENERIC_CLOCKEVENTS
1416 depends on MMU || ARM_MPU
1418 This enables support for systems with more than one CPU. If you have
1419 a system with only one CPU, say N. If you have a system with more
1420 than one CPU, say Y.
1422 If you say N here, the kernel will run on uni- and multiprocessor
1423 machines, but will use only one CPU of a multiprocessor machine. If
1424 you say Y here, the kernel will run on many, but not all,
1425 uniprocessor machines. On a uniprocessor machine, the kernel
1426 will run faster if you say N here.
1428 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1429 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1430 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1432 If you don't know what to do here, say N.
1435 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1436 depends on SMP && !XIP_KERNEL && MMU
1439 SMP kernels contain instructions which fail on non-SMP processors.
1440 Enabling this option allows the kernel to modify itself to make
1441 these instructions safe. Disabling it allows about 1K of space
1444 If you don't know what to do here, say Y.
1446 config ARM_CPU_TOPOLOGY
1447 bool "Support cpu topology definition"
1448 depends on SMP && CPU_V7
1451 Support ARM cpu topology definition. The MPIDR register defines
1452 affinity between processors which is then used to describe the cpu
1453 topology of an ARM System.
1456 bool "Multi-core scheduler support"
1457 depends on ARM_CPU_TOPOLOGY
1459 Multi-core scheduler support improves the CPU scheduler's decision
1460 making when dealing with multi-core CPU chips at a cost of slightly
1461 increased overhead in some places. If unsure say N here.
1464 bool "SMT scheduler support"
1465 depends on ARM_CPU_TOPOLOGY
1467 Improves the CPU scheduler's decision making when dealing with
1468 MultiThreading at a cost of slightly increased overhead in some
1469 places. If unsure say N here.
1474 This option enables support for the ARM system coherency unit
1476 config HAVE_ARM_ARCH_TIMER
1477 bool "Architected timer support"
1479 select ARM_ARCH_TIMER
1480 select GENERIC_CLOCKEVENTS
1482 This option enables support for the ARM architected timer
1487 select CLKSRC_OF if OF
1489 This options enables support for the ARM timer and watchdog unit
1492 bool "Multi-Cluster Power Management"
1493 depends on CPU_V7 && SMP
1495 This option provides the common power management infrastructure
1496 for (multi-)cluster based systems, such as big.LITTLE based
1500 bool "big.LITTLE support (Experimental)"
1501 depends on CPU_V7 && SMP
1504 This option enables support selections for the big.LITTLE
1505 system architecture.
1508 bool "big.LITTLE switcher support"
1509 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1510 select ARM_CPU_SUSPEND
1513 The big.LITTLE "switcher" provides the core functionality to
1514 transparently handle transition between a cluster of A15's
1515 and a cluster of A7's in a big.LITTLE system.
1517 config BL_SWITCHER_DUMMY_IF
1518 tristate "Simple big.LITTLE switcher user interface"
1519 depends on BL_SWITCHER && DEBUG_KERNEL
1521 This is a simple and dummy char dev interface to control
1522 the big.LITTLE switcher core code. It is meant for
1523 debugging purposes only.
1526 prompt "Memory split"
1530 Select the desired split between kernel and user memory.
1532 If you are not absolutely sure what you are doing, leave this
1536 bool "3G/1G user/kernel split"
1538 bool "2G/2G user/kernel split"
1540 bool "1G/3G user/kernel split"
1545 default PHYS_OFFSET if !MMU
1546 default 0x40000000 if VMSPLIT_1G
1547 default 0x80000000 if VMSPLIT_2G
1551 int "Maximum number of CPUs (2-32)"
1557 bool "Support for hot-pluggable CPUs"
1560 Say Y here to experiment with turning CPUs off and on. CPUs
1561 can be controlled through /sys/devices/system/cpu.
1564 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1567 Say Y here if you want Linux to communicate with system firmware
1568 implementing the PSCI specification for CPU-centric power
1569 management operations described in ARM document number ARM DEN
1570 0022A ("Power State Coordination Interface System Software on
1573 # The GPIO number here must be sorted by descending number. In case of
1574 # a multiplatform kernel, we just want the highest value required by the
1575 # selected platforms.
1578 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1579 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1580 default 416 if ARCH_SUNXI
1581 default 392 if ARCH_U8500
1582 default 352 if ARCH_VT8500
1583 default 264 if MACH_H4700
1586 Maximum number of GPIOs in the system.
1588 If unsure, leave the default value.
1590 source kernel/Kconfig.preempt
1594 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1595 ARCH_S5PV210 || ARCH_EXYNOS4
1596 default AT91_TIMER_HZ if ARCH_AT91
1597 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1601 depends on HZ_FIXED = 0
1602 prompt "Timer frequency"
1626 default HZ_FIXED if HZ_FIXED != 0
1627 default 100 if HZ_100
1628 default 200 if HZ_200
1629 default 250 if HZ_250
1630 default 300 if HZ_300
1631 default 500 if HZ_500
1635 def_bool HIGH_RES_TIMERS
1637 config THUMB2_KERNEL
1638 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1639 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1640 default y if CPU_THUMBONLY
1642 select ARM_ASM_UNIFIED
1645 By enabling this option, the kernel will be compiled in
1646 Thumb-2 mode. A compiler/assembler that understand the unified
1647 ARM-Thumb syntax is needed.
1651 config THUMB2_AVOID_R_ARM_THM_JUMP11
1652 bool "Work around buggy Thumb-2 short branch relocations in gas"
1653 depends on THUMB2_KERNEL && MODULES
1656 Various binutils versions can resolve Thumb-2 branches to
1657 locally-defined, preemptible global symbols as short-range "b.n"
1658 branch instructions.
1660 This is a problem, because there's no guarantee the final
1661 destination of the symbol, or any candidate locations for a
1662 trampoline, are within range of the branch. For this reason, the
1663 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1664 relocation in modules at all, and it makes little sense to add
1667 The symptom is that the kernel fails with an "unsupported
1668 relocation" error when loading some modules.
1670 Until fixed tools are available, passing
1671 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1672 code which hits this problem, at the cost of a bit of extra runtime
1673 stack usage in some cases.
1675 The problem is described in more detail at:
1676 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1678 Only Thumb-2 kernels are affected.
1680 Unless you are sure your tools don't have this problem, say Y.
1682 config ARM_ASM_UNIFIED
1686 bool "Use the ARM EABI to compile the kernel"
1688 This option allows for the kernel to be compiled using the latest
1689 ARM ABI (aka EABI). This is only useful if you are using a user
1690 space environment that is also compiled with EABI.
1692 Since there are major incompatibilities between the legacy ABI and
1693 EABI, especially with regard to structure member alignment, this
1694 option also changes the kernel syscall calling convention to
1695 disambiguate both ABIs and allow for backward compatibility support
1696 (selected with CONFIG_OABI_COMPAT).
1698 To use this you need GCC version 4.0.0 or later.
1701 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1702 depends on AEABI && !THUMB2_KERNEL
1704 This option preserves the old syscall interface along with the
1705 new (ARM EABI) one. It also provides a compatibility layer to
1706 intercept syscalls that have structure arguments which layout
1707 in memory differs between the legacy ABI and the new ARM EABI
1708 (only for non "thumb" binaries). This option adds a tiny
1709 overhead to all syscalls and produces a slightly larger kernel.
1711 The seccomp filter system will not be available when this is
1712 selected, since there is no way yet to sensibly distinguish
1713 between calling conventions during filtering.
1715 If you know you'll be using only pure EABI user space then you
1716 can say N here. If this option is not selected and you attempt
1717 to execute a legacy ABI binary then the result will be
1718 UNPREDICTABLE (in fact it can be predicted that it won't work
1719 at all). If in doubt say N.
1721 config ARCH_HAS_HOLES_MEMORYMODEL
1724 config ARCH_SPARSEMEM_ENABLE
1727 config ARCH_SPARSEMEM_DEFAULT
1728 def_bool ARCH_SPARSEMEM_ENABLE
1730 config ARCH_SELECT_MEMORY_MODEL
1731 def_bool ARCH_SPARSEMEM_ENABLE
1733 config HAVE_ARCH_PFN_VALID
1734 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1737 bool "High Memory Support"
1740 The address space of ARM processors is only 4 Gigabytes large
1741 and it has to accommodate user address space, kernel address
1742 space as well as some memory mapped IO. That means that, if you
1743 have a large amount of physical memory and/or IO, not all of the
1744 memory can be "permanently mapped" by the kernel. The physical
1745 memory that is not permanently mapped is called "high memory".
1747 Depending on the selected kernel/user memory split, minimum
1748 vmalloc space and actual amount of RAM, you may not need this
1749 option which should result in a slightly faster kernel.
1754 bool "Allocate 2nd-level pagetables from highmem"
1757 config HW_PERF_EVENTS
1758 bool "Enable hardware performance counter support for perf events"
1759 depends on PERF_EVENTS
1762 Enable hardware performance counter support for perf events. If
1763 disabled, perf events will use software events only.
1765 config SYS_SUPPORTS_HUGETLBFS
1769 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1773 config ARCH_WANT_GENERAL_HUGETLB
1778 config FORCE_MAX_ZONEORDER
1779 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1780 range 11 64 if ARCH_SHMOBILE_LEGACY
1781 default "12" if SOC_AM33XX
1782 default "9" if SA1111 || ARCH_EFM32
1785 The kernel memory allocator divides physically contiguous memory
1786 blocks into "zones", where each zone is a power of two number of
1787 pages. This option selects the largest power of two that the kernel
1788 keeps in the memory allocator. If you need to allocate very large
1789 blocks of physically contiguous memory, then you may need to
1790 increase this value.
1792 This config option is actually maximum order plus one. For example,
1793 a value of 11 means that the largest free memory block is 2^10 pages.
1795 config ALIGNMENT_TRAP
1797 depends on CPU_CP15_MMU
1798 default y if !ARCH_EBSA110
1799 select HAVE_PROC_CPU if PROC_FS
1801 ARM processors cannot fetch/store information which is not
1802 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1803 address divisible by 4. On 32-bit ARM processors, these non-aligned
1804 fetch/store instructions will be emulated in software if you say
1805 here, which has a severe performance impact. This is necessary for
1806 correct operation of some network protocols. With an IP-only
1807 configuration it is safe to say N, otherwise say Y.
1809 config UACCESS_WITH_MEMCPY
1810 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1812 default y if CPU_FEROCEON
1814 Implement faster copy_to_user and clear_user methods for CPU
1815 cores where a 8-word STM instruction give significantly higher
1816 memory write throughput than a sequence of individual 32bit stores.
1818 A possible side effect is a slight increase in scheduling latency
1819 between threads sharing the same address space if they invoke
1820 such copy operations with large buffers.
1822 However, if the CPU data cache is using a write-allocate mode,
1823 this option is unlikely to provide any performance gain.
1827 prompt "Enable seccomp to safely compute untrusted bytecode"
1829 This kernel feature is useful for number crunching applications
1830 that may need to compute untrusted bytecode during their
1831 execution. By using pipes or other transports made available to
1832 the process as file descriptors supporting the read/write
1833 syscalls, it's possible to isolate those applications in
1834 their own address space using seccomp. Once seccomp is
1835 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1836 and the task is only allowed to execute a few safe syscalls
1837 defined by each seccomp mode.
1850 bool "Xen guest support on ARM (EXPERIMENTAL)"
1851 depends on ARM && AEABI && OF
1852 depends on CPU_V7 && !CPU_V6
1853 depends on !GENERIC_ATOMIC64
1855 select ARCH_DMA_ADDR_T_64BIT
1859 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1866 bool "Flattened Device Tree support"
1869 select OF_EARLY_FLATTREE
1870 select OF_RESERVED_MEM
1872 Include support for flattened device tree machine descriptions.
1875 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1878 This is the traditional way of passing data to the kernel at boot
1879 time. If you are solely relying on the flattened device tree (or
1880 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1881 to remove ATAGS support from your kernel binary. If unsure,
1884 config DEPRECATED_PARAM_STRUCT
1885 bool "Provide old way to pass kernel parameters"
1888 This was deprecated in 2001 and announced to live on for 5 years.
1889 Some old boot loaders still use this way.
1891 # Compressed boot loader in ROM. Yes, we really want to ask about
1892 # TEXT and BSS so we preserve their values in the config files.
1893 config ZBOOT_ROM_TEXT
1894 hex "Compressed ROM boot loader base address"
1897 The physical address at which the ROM-able zImage is to be
1898 placed in the target. Platforms which normally make use of
1899 ROM-able zImage formats normally set this to a suitable
1900 value in their defconfig file.
1902 If ZBOOT_ROM is not enabled, this has no effect.
1904 config ZBOOT_ROM_BSS
1905 hex "Compressed ROM boot loader BSS address"
1908 The base address of an area of read/write memory in the target
1909 for the ROM-able zImage which must be available while the
1910 decompressor is running. It must be large enough to hold the
1911 entire decompressed kernel plus an additional 128 KiB.
1912 Platforms which normally make use of ROM-able zImage formats
1913 normally set this to a suitable value in their defconfig file.
1915 If ZBOOT_ROM is not enabled, this has no effect.
1918 bool "Compressed boot loader in ROM/flash"
1919 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1920 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1922 Say Y here if you intend to execute your compressed kernel image
1923 (zImage) directly from ROM or flash. If unsure, say N.
1926 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1927 depends on ZBOOT_ROM && ARCH_SH7372
1928 default ZBOOT_ROM_NONE
1930 Include experimental SD/MMC loading code in the ROM-able zImage.
1931 With this enabled it is possible to write the ROM-able zImage
1932 kernel image to an MMC or SD card and boot the kernel straight
1933 from the reset vector. At reset the processor Mask ROM will load
1934 the first part of the ROM-able zImage which in turn loads the
1935 rest the kernel image to RAM.
1937 config ZBOOT_ROM_NONE
1938 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1940 Do not load image from SD or MMC
1942 config ZBOOT_ROM_MMCIF
1943 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1945 Load image from MMCIF hardware block.
1947 config ZBOOT_ROM_SH_MOBILE_SDHI
1948 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1950 Load image from SDHI hardware block
1954 config ARM_APPENDED_DTB
1955 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1958 With this option, the boot code will look for a device tree binary
1959 (DTB) appended to zImage
1960 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1962 This is meant as a backward compatibility convenience for those
1963 systems with a bootloader that can't be upgraded to accommodate
1964 the documented boot protocol using a device tree.
1966 Beware that there is very little in terms of protection against
1967 this option being confused by leftover garbage in memory that might
1968 look like a DTB header after a reboot if no actual DTB is appended
1969 to zImage. Do not leave this option active in a production kernel
1970 if you don't intend to always append a DTB. Proper passing of the
1971 location into r2 of a bootloader provided DTB is always preferable
1974 config ARM_ATAG_DTB_COMPAT
1975 bool "Supplement the appended DTB with traditional ATAG information"
1976 depends on ARM_APPENDED_DTB
1978 Some old bootloaders can't be updated to a DTB capable one, yet
1979 they provide ATAGs with memory configuration, the ramdisk address,
1980 the kernel cmdline string, etc. Such information is dynamically
1981 provided by the bootloader and can't always be stored in a static
1982 DTB. To allow a device tree enabled kernel to be used with such
1983 bootloaders, this option allows zImage to extract the information
1984 from the ATAG list and store it at run time into the appended DTB.
1987 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1988 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1990 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1991 bool "Use bootloader kernel arguments if available"
1993 Uses the command-line options passed by the boot loader instead of
1994 the device tree bootargs property. If the boot loader doesn't provide
1995 any, the device tree bootargs property will be used.
1997 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1998 bool "Extend with bootloader kernel arguments"
2000 The command-line arguments provided by the boot loader will be
2001 appended to the the device tree bootargs property.
2006 string "Default kernel command string"
2009 On some architectures (EBSA110 and CATS), there is currently no way
2010 for the boot loader to pass arguments to the kernel. For these
2011 architectures, you should supply some command-line options at build
2012 time by entering them here. As a minimum, you should specify the
2013 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2016 prompt "Kernel command line type" if CMDLINE != ""
2017 default CMDLINE_FROM_BOOTLOADER
2020 config CMDLINE_FROM_BOOTLOADER
2021 bool "Use bootloader kernel arguments if available"
2023 Uses the command-line options passed by the boot loader. If
2024 the boot loader doesn't provide any, the default kernel command
2025 string provided in CMDLINE will be used.
2027 config CMDLINE_EXTEND
2028 bool "Extend bootloader kernel arguments"
2030 The command-line arguments provided by the boot loader will be
2031 appended to the default kernel command string.
2033 config CMDLINE_FORCE
2034 bool "Always use the default kernel command string"
2036 Always use the default kernel command string, even if the boot
2037 loader passes other arguments to the kernel.
2038 This is useful if you cannot or don't want to change the
2039 command-line options your boot loader passes to the kernel.
2043 bool "Kernel Execute-In-Place from ROM"
2044 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2046 Execute-In-Place allows the kernel to run from non-volatile storage
2047 directly addressable by the CPU, such as NOR flash. This saves RAM
2048 space since the text section of the kernel is not loaded from flash
2049 to RAM. Read-write sections, such as the data section and stack,
2050 are still copied to RAM. The XIP kernel is not compressed since
2051 it has to run directly from flash, so it will take more space to
2052 store it. The flash address used to link the kernel object files,
2053 and for storing it, is configuration dependent. Therefore, if you
2054 say Y here, you must know the proper physical address where to
2055 store the kernel image depending on your own flash memory usage.
2057 Also note that the make target becomes "make xipImage" rather than
2058 "make zImage" or "make Image". The final kernel binary to put in
2059 ROM memory will be arch/arm/boot/xipImage.
2063 config XIP_PHYS_ADDR
2064 hex "XIP Kernel Physical Location"
2065 depends on XIP_KERNEL
2066 default "0x00080000"
2068 This is the physical address in your flash memory the kernel will
2069 be linked for and stored to. This address is dependent on your
2073 bool "Kexec system call (EXPERIMENTAL)"
2074 depends on (!SMP || PM_SLEEP_SMP)
2076 kexec is a system call that implements the ability to shutdown your
2077 current kernel, and to start another kernel. It is like a reboot
2078 but it is independent of the system firmware. And like a reboot
2079 you can start any kernel with it, not just Linux.
2081 It is an ongoing process to be certain the hardware in a machine
2082 is properly shutdown, so do not be surprised if this code does not
2083 initially work for you.
2086 bool "Export atags in procfs"
2087 depends on ATAGS && KEXEC
2090 Should the atags used to boot the kernel be exported in an "atags"
2091 file in procfs. Useful with kexec.
2094 bool "Build kdump crash kernel (EXPERIMENTAL)"
2096 Generate crash dump after being started by kexec. This should
2097 be normally only set in special crash dump kernels which are
2098 loaded in the main kernel with kexec-tools into a specially
2099 reserved region and then later executed after a crash by
2100 kdump/kexec. The crash dump kernel must be compiled to a
2101 memory address not used by the main kernel
2103 For more details see Documentation/kdump/kdump.txt
2105 config AUTO_ZRELADDR
2106 bool "Auto calculation of the decompressed kernel image address"
2108 ZRELADDR is the physical address where the decompressed kernel
2109 image will be placed. If AUTO_ZRELADDR is selected, the address
2110 will be determined at run-time by masking the current IP with
2111 0xf8000000. This assumes the zImage being placed in the first 128MB
2112 from start of memory.
2116 menu "CPU Power Management"
2119 source "drivers/cpufreq/Kconfig"
2122 source "drivers/cpuidle/Kconfig"
2126 menu "Floating point emulation"
2128 comment "At least one emulation must be selected"
2131 bool "NWFPE math emulation"
2132 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2134 Say Y to include the NWFPE floating point emulator in the kernel.
2135 This is necessary to run most binaries. Linux does not currently
2136 support floating point hardware so you need to say Y here even if
2137 your machine has an FPA or floating point co-processor podule.
2139 You may say N here if you are going to load the Acorn FPEmulator
2140 early in the bootup.
2143 bool "Support extended precision"
2144 depends on FPE_NWFPE
2146 Say Y to include 80-bit support in the kernel floating-point
2147 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2148 Note that gcc does not generate 80-bit operations by default,
2149 so in most cases this option only enlarges the size of the
2150 floating point emulator without any good reason.
2152 You almost surely want to say N here.
2155 bool "FastFPE math emulation (EXPERIMENTAL)"
2156 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2158 Say Y here to include the FAST floating point emulator in the kernel.
2159 This is an experimental much faster emulator which now also has full
2160 precision for the mantissa. It does not support any exceptions.
2161 It is very simple, and approximately 3-6 times faster than NWFPE.
2163 It should be sufficient for most programs. It may be not suitable
2164 for scientific calculations, but you have to check this for yourself.
2165 If you do not feel you need a faster FP emulation you should better
2169 bool "VFP-format floating point maths"
2170 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2172 Say Y to include VFP support code in the kernel. This is needed
2173 if your hardware includes a VFP unit.
2175 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2176 release notes and additional status information.
2178 Say N if your target does not have VFP hardware.
2186 bool "Advanced SIMD (NEON) Extension support"
2187 depends on VFPv3 && CPU_V7
2189 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2192 config KERNEL_MODE_NEON
2193 bool "Support for NEON in kernel mode"
2194 depends on NEON && AEABI
2196 Say Y to include support for NEON in kernel mode.
2200 menu "Userspace binary formats"
2202 source "fs/Kconfig.binfmt"
2205 tristate "RISC OS personality"
2208 Say Y here to include the kernel code necessary if you want to run
2209 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2210 experimental; if this sounds frightening, say N and sleep in peace.
2211 You can also say M here to compile this support as a module (which
2212 will be called arthur).
2216 menu "Power management options"
2218 source "kernel/power/Kconfig"
2220 config ARCH_SUSPEND_POSSIBLE
2221 depends on !ARCH_S5PC100
2222 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2223 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2226 config ARM_CPU_SUSPEND
2229 config ARCH_HIBERNATION_POSSIBLE
2232 default y if ARCH_SUSPEND_POSSIBLE
2236 source "net/Kconfig"
2238 source "drivers/Kconfig"
2242 source "arch/arm/Kconfig.debug"
2244 source "security/Kconfig"
2246 source "crypto/Kconfig"
2248 source "lib/Kconfig"
2250 source "arch/arm/kvm/Kconfig"