4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
317 select COMMON_CLK_VERSATILE
318 select GENERIC_CLOCKEVENTS
321 select MULTI_IRQ_HANDLER
322 select NEED_MACH_MEMORY_H
323 select PLAT_VERSATILE
326 select VERSATILE_FPGA_IRQ
328 Support for ARM's Integrator platform.
331 bool "ARM Ltd. RealView family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
336 select COMMON_CLK_VERSATILE
337 select GENERIC_CLOCKEVENTS
338 select GPIO_PL061 if GPIOLIB
340 select NEED_MACH_MEMORY_H
341 select PLAT_VERSATILE
342 select PLAT_VERSATILE_CLCD
344 This enables support for ARM Ltd RealView boards.
346 config ARCH_VERSATILE
347 bool "ARM Ltd. Versatile family"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select HAVE_MACH_CLKDEV
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
358 select PLAT_VERSATILE_CLOCK
359 select VERSATILE_FPGA_IRQ
361 This enables support for ARM Ltd Versatile board.
365 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_GPIO_H
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
385 select MULTI_IRQ_HANDLER
388 Support for Cirrus Logic 711x/721x/731x based boards.
391 bool "Cortina Systems Gemini"
392 select ARCH_REQUIRE_GPIOLIB
395 select GENERIC_CLOCKEVENTS
397 Support for the Cortina Systems Gemini family SoCs
401 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_IO_H
405 select NEED_MACH_MEMORY_H
408 This is an evaluation board for the StrongARM processor available
409 from Digital. It has limited hardware on-board, including an
410 Ethernet interface, two PCMCIA sockets, two serial ports and a
415 select ARCH_HAS_HOLES_MEMORYMODEL
416 select ARCH_REQUIRE_GPIOLIB
417 select ARCH_USES_GETTIMEOFFSET
422 select NEED_MACH_MEMORY_H
424 This enables support for the Cirrus EP93xx series of CPUs.
426 config ARCH_FOOTBRIDGE
430 select GENERIC_CLOCKEVENTS
432 select NEED_MACH_IO_H if !MMU
433 select NEED_MACH_MEMORY_H
435 Support for systems based on the DC21285 companion chip
436 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
439 bool "Hilscher NetX based"
443 select GENERIC_CLOCKEVENTS
445 This enables support for systems based on the Hilscher NetX Soc
451 select NEED_MACH_MEMORY_H
452 select NEED_RET_TO_USER
457 Support for Intel's IOP13XX (XScale) family of processors.
462 select ARCH_REQUIRE_GPIOLIB
465 select NEED_RET_TO_USER
469 Support for Intel's 80219 and IOP32X (XScale) family of
475 select ARCH_REQUIRE_GPIOLIB
478 select NEED_RET_TO_USER
482 Support for Intel's IOP33X (XScale) family of processors.
487 select ARCH_HAS_DMA_SET_COHERENT_MASK
488 select ARCH_SUPPORTS_BIG_ENDIAN
489 select ARCH_REQUIRE_GPIOLIB
492 select DMABOUNCE if PCI
493 select GENERIC_CLOCKEVENTS
494 select MIGHT_HAVE_PCI
495 select NEED_MACH_IO_H
496 select USB_EHCI_BIG_ENDIAN_DESC
497 select USB_EHCI_BIG_ENDIAN_MMIO
499 Support for Intel's IXP4XX (XScale) family of processors.
503 select ARCH_REQUIRE_GPIOLIB
505 select GENERIC_CLOCKEVENTS
506 select MIGHT_HAVE_PCI
510 select PLAT_ORION_LEGACY
511 select USB_ARCH_HAS_EHCI
513 Support for the Marvell Dove SoC 88AP510
516 bool "Marvell Kirkwood"
517 select ARCH_HAS_CPUFREQ
518 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
525 select PINCTRL_KIRKWOOD
526 select PLAT_ORION_LEGACY
528 Support for the following Marvell Kirkwood series SoCs:
529 88F6180, 88F6192 and 88F6281.
532 bool "Marvell MV78xx0"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
538 select PLAT_ORION_LEGACY
540 Support for the following Marvell MV78xx0 series SoCs:
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Orion 5x series SoCs:
554 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
555 Orion-2 (5281), Orion-1-90 (6183).
558 bool "Marvell PXA168/910/MMP2"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_ALLOCATOR
563 select GENERIC_CLOCKEVENTS
566 select MULTI_IRQ_HANDLER
571 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
574 bool "Micrel/Kendin KS8695"
575 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select NEED_MACH_MEMORY_H
581 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
582 System-on-Chip devices.
585 bool "Nuvoton W90X900 CPU"
586 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
592 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
593 At present, the w90x900 has been renamed nuc900, regarding
594 the ARM series product line, you can login the following
595 link address to know more.
597 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
598 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
602 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
610 select USB_ARCH_HAS_OHCI
613 Support for the NXP LPC32XX family of processors
616 bool "PXA2xx/PXA3xx-based"
618 select ARCH_HAS_CPUFREQ
620 select ARCH_REQUIRE_GPIOLIB
621 select ARM_CPU_SUSPEND if PM
625 select GENERIC_CLOCKEVENTS
628 select MULTI_IRQ_HANDLER
632 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
636 select ARCH_REQUIRE_GPIOLIB
637 select CLKSRC_OF if OF
639 select GENERIC_CLOCKEVENTS
641 Support for Qualcomm MSM/QSD based systems. This runs on the
642 apps processor of the MSM/QSD and depends on a shared memory
643 interface to the modem processor which runs the baseband
644 stack and controls some vital subsystems
645 (clock and power control, etc).
647 config ARCH_SHMOBILE_LEGACY
648 bool "Renesas ARM SoCs (non-multiplatform)"
650 select ARM_PATCH_PHYS_VIRT
652 select GENERIC_CLOCKEVENTS
653 select HAVE_ARM_SCU if SMP
654 select HAVE_ARM_TWD if SMP
655 select HAVE_MACH_CLKDEV
657 select MIGHT_HAVE_CACHE_L2X0
658 select MULTI_IRQ_HANDLER
661 select PM_GENERIC_DOMAINS if PM
664 Support for Renesas ARM SoC platforms using a non-multiplatform
665 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
671 select ARCH_MAY_HAVE_PC_FDC
672 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_USES_GETTIMEOFFSET
676 select HAVE_PATA_PLATFORM
678 select NEED_MACH_IO_H
679 select NEED_MACH_MEMORY_H
683 On the Acorn Risc-PC, Linux can support the internal IDE disk and
684 CD-ROM interface, serial and parallel port, and the floppy drive.
688 select ARCH_HAS_CPUFREQ
690 select ARCH_REQUIRE_GPIOLIB
691 select ARCH_SPARSEMEM_ENABLE
696 select GENERIC_CLOCKEVENTS
699 select NEED_MACH_MEMORY_H
702 Support for StrongARM 11x0 based boards.
705 bool "Samsung S3C24XX SoCs"
706 select ARCH_HAS_CPUFREQ
707 select ARCH_REQUIRE_GPIOLIB
709 select CLKSRC_SAMSUNG_PWM
710 select GENERIC_CLOCKEVENTS
712 select HAVE_S3C2410_I2C if I2C
713 select HAVE_S3C2410_WATCHDOG if WATCHDOG
714 select HAVE_S3C_RTC if RTC_CLASS
715 select MULTI_IRQ_HANDLER
716 select NEED_MACH_GPIO_H
717 select NEED_MACH_IO_H
720 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
721 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
722 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
723 Samsung SMDK2410 development board (and derivatives).
726 bool "Samsung S3C64XX"
727 select ARCH_HAS_CPUFREQ
728 select ARCH_REQUIRE_GPIOLIB
732 select CLKSRC_SAMSUNG_PWM
735 select GENERIC_CLOCKEVENTS
737 select HAVE_S3C2410_I2C if I2C
738 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 select NEED_MACH_GPIO_H
743 select PM_GENERIC_DOMAINS
745 select S3C_GPIO_TRACK
747 select SAMSUNG_GPIOLIB_4BIT
748 select SAMSUNG_WAKEMASK
749 select SAMSUNG_WDT_RESET
750 select USB_ARCH_HAS_OHCI
752 Samsung S3C64XX series based systems
755 bool "Samsung S5P6440 S5P6450"
757 select CLKSRC_SAMSUNG_PWM
759 select GENERIC_CLOCKEVENTS
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 select HAVE_S3C_RTC if RTC_CLASS
764 select NEED_MACH_GPIO_H
766 select SAMSUNG_WDT_RESET
768 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
772 bool "Samsung S5PC100"
773 select ARCH_REQUIRE_GPIOLIB
775 select CLKSRC_SAMSUNG_PWM
777 select GENERIC_CLOCKEVENTS
779 select HAVE_S3C2410_I2C if I2C
780 select HAVE_S3C2410_WATCHDOG if WATCHDOG
781 select HAVE_S3C_RTC if RTC_CLASS
782 select NEED_MACH_GPIO_H
784 select SAMSUNG_WDT_RESET
786 Samsung S5PC100 series based systems
789 bool "Samsung S5PV210/S5PC110"
790 select ARCH_HAS_CPUFREQ
791 select ARCH_HAS_HOLES_MEMORYMODEL
792 select ARCH_SPARSEMEM_ENABLE
794 select CLKSRC_SAMSUNG_PWM
796 select GENERIC_CLOCKEVENTS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select HAVE_S3C_RTC if RTC_CLASS
801 select NEED_MACH_GPIO_H
802 select NEED_MACH_MEMORY_H
805 Samsung S5PV210/S5PC110 series based systems
808 bool "Samsung EXYNOS"
809 select ARCH_HAS_CPUFREQ
810 select ARCH_HAS_HOLES_MEMORYMODEL
811 select ARCH_REQUIRE_GPIOLIB
812 select ARCH_SPARSEMEM_ENABLE
816 select GENERIC_CLOCKEVENTS
817 select HAVE_S3C2410_I2C if I2C
818 select HAVE_S3C2410_WATCHDOG if WATCHDOG
819 select HAVE_S3C_RTC if RTC_CLASS
820 select NEED_MACH_MEMORY_H
824 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
828 select ARCH_HAS_HOLES_MEMORYMODEL
829 select ARCH_REQUIRE_GPIOLIB
831 select GENERIC_ALLOCATOR
832 select GENERIC_CLOCKEVENTS
833 select GENERIC_IRQ_CHIP
839 Support for TI's DaVinci platform.
844 select ARCH_HAS_CPUFREQ
845 select ARCH_HAS_HOLES_MEMORYMODEL
847 select ARCH_REQUIRE_GPIOLIB
850 select GENERIC_CLOCKEVENTS
851 select GENERIC_IRQ_CHIP
854 select NEED_MACH_IO_H if PCCARD
855 select NEED_MACH_MEMORY_H
857 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
861 menu "Multiple platform selection"
862 depends on ARCH_MULTIPLATFORM
864 comment "CPU Core family selection"
866 config ARCH_MULTI_V4T
867 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
868 depends on !ARCH_MULTI_V6_V7
869 select ARCH_MULTI_V4_V5
870 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
871 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
872 CPU_ARM925T || CPU_ARM940T)
875 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
876 depends on !ARCH_MULTI_V6_V7
877 select ARCH_MULTI_V4_V5
878 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
879 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
880 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
882 config ARCH_MULTI_V4_V5
886 bool "ARMv6 based platforms (ARM11)"
887 select ARCH_MULTI_V6_V7
891 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
893 select ARCH_MULTI_V6_V7
896 config ARCH_MULTI_V6_V7
899 config ARCH_MULTI_CPU_AUTO
900 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
906 # This is sorted alphabetically by mach-* pathname. However, plat-*
907 # Kconfigs may be included either alphabetically (according to the
908 # plat- suffix) or along side the corresponding mach-* source.
910 source "arch/arm/mach-mvebu/Kconfig"
912 source "arch/arm/mach-at91/Kconfig"
914 source "arch/arm/mach-bcm/Kconfig"
916 source "arch/arm/mach-bcm2835/Kconfig"
918 source "arch/arm/mach-clps711x/Kconfig"
920 source "arch/arm/mach-cns3xxx/Kconfig"
922 source "arch/arm/mach-davinci/Kconfig"
924 source "arch/arm/mach-dove/Kconfig"
926 source "arch/arm/mach-ep93xx/Kconfig"
928 source "arch/arm/mach-footbridge/Kconfig"
930 source "arch/arm/mach-gemini/Kconfig"
932 source "arch/arm/mach-highbank/Kconfig"
934 source "arch/arm/mach-integrator/Kconfig"
936 source "arch/arm/mach-iop32x/Kconfig"
938 source "arch/arm/mach-iop33x/Kconfig"
940 source "arch/arm/mach-iop13xx/Kconfig"
942 source "arch/arm/mach-ixp4xx/Kconfig"
944 source "arch/arm/mach-keystone/Kconfig"
946 source "arch/arm/mach-kirkwood/Kconfig"
948 source "arch/arm/mach-ks8695/Kconfig"
950 source "arch/arm/mach-msm/Kconfig"
952 source "arch/arm/mach-mv78xx0/Kconfig"
954 source "arch/arm/mach-imx/Kconfig"
956 source "arch/arm/mach-mxs/Kconfig"
958 source "arch/arm/mach-netx/Kconfig"
960 source "arch/arm/mach-nomadik/Kconfig"
962 source "arch/arm/mach-nspire/Kconfig"
964 source "arch/arm/plat-omap/Kconfig"
966 source "arch/arm/mach-omap1/Kconfig"
968 source "arch/arm/mach-omap2/Kconfig"
970 source "arch/arm/mach-orion5x/Kconfig"
972 source "arch/arm/mach-picoxcell/Kconfig"
974 source "arch/arm/mach-pxa/Kconfig"
975 source "arch/arm/plat-pxa/Kconfig"
977 source "arch/arm/mach-mmp/Kconfig"
979 source "arch/arm/mach-realview/Kconfig"
981 source "arch/arm/mach-rockchip/Kconfig"
983 source "arch/arm/mach-sa1100/Kconfig"
985 source "arch/arm/plat-samsung/Kconfig"
987 source "arch/arm/mach-socfpga/Kconfig"
989 source "arch/arm/mach-spear/Kconfig"
991 source "arch/arm/mach-sti/Kconfig"
993 source "arch/arm/mach-s3c24xx/Kconfig"
995 source "arch/arm/mach-s3c64xx/Kconfig"
997 source "arch/arm/mach-s5p64x0/Kconfig"
999 source "arch/arm/mach-s5pc100/Kconfig"
1001 source "arch/arm/mach-s5pv210/Kconfig"
1003 source "arch/arm/mach-exynos/Kconfig"
1005 source "arch/arm/mach-shmobile/Kconfig"
1007 source "arch/arm/mach-sunxi/Kconfig"
1009 source "arch/arm/mach-prima2/Kconfig"
1011 source "arch/arm/mach-tegra/Kconfig"
1013 source "arch/arm/mach-u300/Kconfig"
1015 source "arch/arm/mach-ux500/Kconfig"
1017 source "arch/arm/mach-versatile/Kconfig"
1019 source "arch/arm/mach-vexpress/Kconfig"
1020 source "arch/arm/plat-versatile/Kconfig"
1022 source "arch/arm/mach-virt/Kconfig"
1024 source "arch/arm/mach-vt8500/Kconfig"
1026 source "arch/arm/mach-w90x900/Kconfig"
1028 source "arch/arm/mach-zynq/Kconfig"
1030 # Definitions to make life easier
1036 select GENERIC_CLOCKEVENTS
1042 select GENERIC_IRQ_CHIP
1045 config PLAT_ORION_LEGACY
1052 config PLAT_VERSATILE
1055 config ARM_TIMER_SP804
1058 select CLKSRC_OF if OF
1060 source arch/arm/mm/Kconfig
1064 default 16 if ARCH_EP93XX
1068 bool "Enable iWMMXt support" if !CPU_PJ4
1069 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1070 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1072 Enable support for iWMMXt context switching at run time if
1073 running on a CPU that supports it.
1075 config MULTI_IRQ_HANDLER
1078 Allow each machine to specify it's own IRQ handler at run time.
1081 source "arch/arm/Kconfig-nommu"
1084 config PJ4B_ERRATA_4742
1085 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1086 depends on CPU_PJ4B && MACH_ARMADA_370
1089 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1090 Event (WFE) IDLE states, a specific timing sensitivity exists between
1091 the retiring WFI/WFE instructions and the newly issued subsequent
1092 instructions. This sensitivity can result in a CPU hang scenario.
1094 The software must insert either a Data Synchronization Barrier (DSB)
1095 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1098 config ARM_ERRATA_326103
1099 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1102 Executing a SWP instruction to read-only memory does not set bit 11
1103 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1104 treat the access as a read, preventing a COW from occurring and
1105 causing the faulting task to livelock.
1107 config ARM_ERRATA_411920
1108 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1109 depends on CPU_V6 || CPU_V6K
1111 Invalidation of the Instruction Cache operation can
1112 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1113 It does not affect the MPCore. This option enables the ARM Ltd.
1114 recommended workaround.
1116 config ARM_ERRATA_430973
1117 bool "ARM errata: Stale prediction on replaced interworking branch"
1120 This option enables the workaround for the 430973 Cortex-A8
1121 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1122 interworking branch is replaced with another code sequence at the
1123 same virtual address, whether due to self-modifying code or virtual
1124 to physical address re-mapping, Cortex-A8 does not recover from the
1125 stale interworking branch prediction. This results in Cortex-A8
1126 executing the new code sequence in the incorrect ARM or Thumb state.
1127 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1128 and also flushes the branch target cache at every context switch.
1129 Note that setting specific bits in the ACTLR register may not be
1130 available in non-secure mode.
1132 config ARM_ERRATA_458693
1133 bool "ARM errata: Processor deadlock when a false hazard is created"
1135 depends on !ARCH_MULTIPLATFORM
1137 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1138 erratum. For very specific sequences of memory operations, it is
1139 possible for a hazard condition intended for a cache line to instead
1140 be incorrectly associated with a different cache line. This false
1141 hazard might then cause a processor deadlock. The workaround enables
1142 the L1 caching of the NEON accesses and disables the PLD instruction
1143 in the ACTLR register. Note that setting specific bits in the ACTLR
1144 register may not be available in non-secure mode.
1146 config ARM_ERRATA_460075
1147 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1149 depends on !ARCH_MULTIPLATFORM
1151 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1152 erratum. Any asynchronous access to the L2 cache may encounter a
1153 situation in which recent store transactions to the L2 cache are lost
1154 and overwritten with stale memory contents from external memory. The
1155 workaround disables the write-allocate mode for the L2 cache via the
1156 ACTLR register. Note that setting specific bits in the ACTLR register
1157 may not be available in non-secure mode.
1159 config ARM_ERRATA_742230
1160 bool "ARM errata: DMB operation may be faulty"
1161 depends on CPU_V7 && SMP
1162 depends on !ARCH_MULTIPLATFORM
1164 This option enables the workaround for the 742230 Cortex-A9
1165 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1166 between two write operations may not ensure the correct visibility
1167 ordering of the two writes. This workaround sets a specific bit in
1168 the diagnostic register of the Cortex-A9 which causes the DMB
1169 instruction to behave as a DSB, ensuring the correct behaviour of
1172 config ARM_ERRATA_742231
1173 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1174 depends on CPU_V7 && SMP
1175 depends on !ARCH_MULTIPLATFORM
1177 This option enables the workaround for the 742231 Cortex-A9
1178 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1179 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1180 accessing some data located in the same cache line, may get corrupted
1181 data due to bad handling of the address hazard when the line gets
1182 replaced from one of the CPUs at the same time as another CPU is
1183 accessing it. This workaround sets specific bits in the diagnostic
1184 register of the Cortex-A9 which reduces the linefill issuing
1185 capabilities of the processor.
1187 config PL310_ERRATA_588369
1188 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1189 depends on CACHE_L2X0
1191 The PL310 L2 cache controller implements three types of Clean &
1192 Invalidate maintenance operations: by Physical Address
1193 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1194 They are architecturally defined to behave as the execution of a
1195 clean operation followed immediately by an invalidate operation,
1196 both performing to the same memory location. This functionality
1197 is not correctly implemented in PL310 as clean lines are not
1198 invalidated as a result of these operations.
1200 config ARM_ERRATA_643719
1201 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1202 depends on CPU_V7 && SMP
1204 This option enables the workaround for the 643719 Cortex-A9 (prior to
1205 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1206 register returns zero when it should return one. The workaround
1207 corrects this value, ensuring cache maintenance operations which use
1208 it behave as intended and avoiding data corruption.
1210 config ARM_ERRATA_720789
1211 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1214 This option enables the workaround for the 720789 Cortex-A9 (prior to
1215 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1216 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1217 As a consequence of this erratum, some TLB entries which should be
1218 invalidated are not, resulting in an incoherency in the system page
1219 tables. The workaround changes the TLB flushing routines to invalidate
1220 entries regardless of the ASID.
1222 config PL310_ERRATA_727915
1223 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1224 depends on CACHE_L2X0
1226 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1227 operation (offset 0x7FC). This operation runs in background so that
1228 PL310 can handle normal accesses while it is in progress. Under very
1229 rare circumstances, due to this erratum, write data can be lost when
1230 PL310 treats a cacheable write transaction during a Clean &
1231 Invalidate by Way operation.
1233 config ARM_ERRATA_743622
1234 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1236 depends on !ARCH_MULTIPLATFORM
1238 This option enables the workaround for the 743622 Cortex-A9
1239 (r2p*) erratum. Under very rare conditions, a faulty
1240 optimisation in the Cortex-A9 Store Buffer may lead to data
1241 corruption. This workaround sets a specific bit in the diagnostic
1242 register of the Cortex-A9 which disables the Store Buffer
1243 optimisation, preventing the defect from occurring. This has no
1244 visible impact on the overall performance or power consumption of the
1247 config ARM_ERRATA_751472
1248 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1250 depends on !ARCH_MULTIPLATFORM
1252 This option enables the workaround for the 751472 Cortex-A9 (prior
1253 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1254 completion of a following broadcasted operation if the second
1255 operation is received by a CPU before the ICIALLUIS has completed,
1256 potentially leading to corrupted entries in the cache or TLB.
1258 config PL310_ERRATA_753970
1259 bool "PL310 errata: cache sync operation may be faulty"
1260 depends on CACHE_PL310
1262 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1264 Under some condition the effect of cache sync operation on
1265 the store buffer still remains when the operation completes.
1266 This means that the store buffer is always asked to drain and
1267 this prevents it from merging any further writes. The workaround
1268 is to replace the normal offset of cache sync operation (0x730)
1269 by another offset targeting an unmapped PL310 register 0x740.
1270 This has the same effect as the cache sync operation: store buffer
1271 drain and waiting for all buffers empty.
1273 config ARM_ERRATA_754322
1274 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1277 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1278 r3p*) erratum. A speculative memory access may cause a page table walk
1279 which starts prior to an ASID switch but completes afterwards. This
1280 can populate the micro-TLB with a stale entry which may be hit with
1281 the new ASID. This workaround places two dsb instructions in the mm
1282 switching code so that no page table walks can cross the ASID switch.
1284 config ARM_ERRATA_754327
1285 bool "ARM errata: no automatic Store Buffer drain"
1286 depends on CPU_V7 && SMP
1288 This option enables the workaround for the 754327 Cortex-A9 (prior to
1289 r2p0) erratum. The Store Buffer does not have any automatic draining
1290 mechanism and therefore a livelock may occur if an external agent
1291 continuously polls a memory location waiting to observe an update.
1292 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1293 written polling loops from denying visibility of updates to memory.
1295 config ARM_ERRATA_364296
1296 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1299 This options enables the workaround for the 364296 ARM1136
1300 r0p2 erratum (possible cache data corruption with
1301 hit-under-miss enabled). It sets the undocumented bit 31 in
1302 the auxiliary control register and the FI bit in the control
1303 register, thus disabling hit-under-miss without putting the
1304 processor into full low interrupt latency mode. ARM11MPCore
1307 config ARM_ERRATA_764369
1308 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1309 depends on CPU_V7 && SMP
1311 This option enables the workaround for erratum 764369
1312 affecting Cortex-A9 MPCore with two or more processors (all
1313 current revisions). Under certain timing circumstances, a data
1314 cache line maintenance operation by MVA targeting an Inner
1315 Shareable memory region may fail to proceed up to either the
1316 Point of Coherency or to the Point of Unification of the
1317 system. This workaround adds a DSB instruction before the
1318 relevant cache maintenance functions and sets a specific bit
1319 in the diagnostic control register of the SCU.
1321 config PL310_ERRATA_769419
1322 bool "PL310 errata: no automatic Store Buffer drain"
1323 depends on CACHE_L2X0
1325 On revisions of the PL310 prior to r3p2, the Store Buffer does
1326 not automatically drain. This can cause normal, non-cacheable
1327 writes to be retained when the memory system is idle, leading
1328 to suboptimal I/O performance for drivers using coherent DMA.
1329 This option adds a write barrier to the cpu_idle loop so that,
1330 on systems with an outer cache, the store buffer is drained
1333 config ARM_ERRATA_775420
1334 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1337 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1338 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1339 operation aborts with MMU exception, it might cause the processor
1340 to deadlock. This workaround puts DSB before executing ISB if
1341 an abort may occur on cache maintenance.
1343 config ARM_ERRATA_798181
1344 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1345 depends on CPU_V7 && SMP
1347 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1348 adequately shooting down all use of the old entries. This
1349 option enables the Linux kernel workaround for this erratum
1350 which sends an IPI to the CPUs that are running the same ASID
1351 as the one being invalidated.
1353 config ARM_ERRATA_773022
1354 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1357 This option enables the workaround for the 773022 Cortex-A15
1358 (up to r0p4) erratum. In certain rare sequences of code, the
1359 loop buffer may deliver incorrect instructions. This
1360 workaround disables the loop buffer to avoid the erratum.
1364 source "arch/arm/common/Kconfig"
1374 Find out whether you have ISA slots on your motherboard. ISA is the
1375 name of a bus system, i.e. the way the CPU talks to the other stuff
1376 inside your box. Other bus systems are PCI, EISA, MicroChannel
1377 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1378 newer boards don't support it. If you have ISA, say Y, otherwise N.
1380 # Select ISA DMA controller support
1385 # Select ISA DMA interface
1390 bool "PCI support" if MIGHT_HAVE_PCI
1392 Find out whether you have a PCI motherboard. PCI is the name of a
1393 bus system, i.e. the way the CPU talks to the other stuff inside
1394 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1395 VESA. If you have PCI, say Y, otherwise N.
1401 config PCI_NANOENGINE
1402 bool "BSE nanoEngine PCI support"
1403 depends on SA1100_NANOENGINE
1405 Enable PCI on the BSE nanoEngine board.
1410 config PCI_HOST_ITE8152
1412 depends on PCI && MACH_ARMCORE
1416 source "drivers/pci/Kconfig"
1417 source "drivers/pci/pcie/Kconfig"
1419 source "drivers/pcmcia/Kconfig"
1423 menu "Kernel Features"
1428 This option should be selected by machines which have an SMP-
1431 The only effect of this option is to make the SMP-related
1432 options available to the user for configuration.
1435 bool "Symmetric Multi-Processing"
1436 depends on CPU_V6K || CPU_V7
1437 depends on GENERIC_CLOCKEVENTS
1439 depends on MMU || ARM_MPU
1441 This enables support for systems with more than one CPU. If you have
1442 a system with only one CPU, like most personal computers, say N. If
1443 you have a system with more than one CPU, say Y.
1445 If you say N here, the kernel will run on single and multiprocessor
1446 machines, but will use only one CPU of a multiprocessor machine. If
1447 you say Y here, the kernel will run on many, but not all, single
1448 processor machines. On a single processor machine, the kernel will
1449 run faster if you say N here.
1451 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1452 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1453 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1455 If you don't know what to do here, say N.
1458 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1459 depends on SMP && !XIP_KERNEL && MMU
1462 SMP kernels contain instructions which fail on non-SMP processors.
1463 Enabling this option allows the kernel to modify itself to make
1464 these instructions safe. Disabling it allows about 1K of space
1467 If you don't know what to do here, say Y.
1469 config ARM_CPU_TOPOLOGY
1470 bool "Support cpu topology definition"
1471 depends on SMP && CPU_V7
1474 Support ARM cpu topology definition. The MPIDR register defines
1475 affinity between processors which is then used to describe the cpu
1476 topology of an ARM System.
1479 bool "Multi-core scheduler support"
1480 depends on ARM_CPU_TOPOLOGY
1482 Multi-core scheduler support improves the CPU scheduler's decision
1483 making when dealing with multi-core CPU chips at a cost of slightly
1484 increased overhead in some places. If unsure say N here.
1487 bool "SMT scheduler support"
1488 depends on ARM_CPU_TOPOLOGY
1490 Improves the CPU scheduler's decision making when dealing with
1491 MultiThreading at a cost of slightly increased overhead in some
1492 places. If unsure say N here.
1497 This option enables support for the ARM system coherency unit
1499 config HAVE_ARM_ARCH_TIMER
1500 bool "Architected timer support"
1502 select ARM_ARCH_TIMER
1503 select GENERIC_CLOCKEVENTS
1505 This option enables support for the ARM architected timer
1510 select CLKSRC_OF if OF
1512 This options enables support for the ARM timer and watchdog unit
1515 bool "Multi-Cluster Power Management"
1516 depends on CPU_V7 && SMP
1518 This option provides the common power management infrastructure
1519 for (multi-)cluster based systems, such as big.LITTLE based
1523 bool "big.LITTLE support (Experimental)"
1524 depends on CPU_V7 && SMP
1527 This option enables support selections for the big.LITTLE
1528 system architecture.
1531 bool "big.LITTLE switcher support"
1532 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1534 select ARM_CPU_SUSPEND
1536 The big.LITTLE "switcher" provides the core functionality to
1537 transparently handle transition between a cluster of A15's
1538 and a cluster of A7's in a big.LITTLE system.
1540 config BL_SWITCHER_DUMMY_IF
1541 tristate "Simple big.LITTLE switcher user interface"
1542 depends on BL_SWITCHER && DEBUG_KERNEL
1544 This is a simple and dummy char dev interface to control
1545 the big.LITTLE switcher core code. It is meant for
1546 debugging purposes only.
1549 prompt "Memory split"
1552 Select the desired split between kernel and user memory.
1554 If you are not absolutely sure what you are doing, leave this
1558 bool "3G/1G user/kernel split"
1560 bool "2G/2G user/kernel split"
1562 bool "1G/3G user/kernel split"
1567 default 0x40000000 if VMSPLIT_1G
1568 default 0x80000000 if VMSPLIT_2G
1572 int "Maximum number of CPUs (2-32)"
1578 bool "Support for hot-pluggable CPUs"
1581 Say Y here to experiment with turning CPUs off and on. CPUs
1582 can be controlled through /sys/devices/system/cpu.
1585 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1588 Say Y here if you want Linux to communicate with system firmware
1589 implementing the PSCI specification for CPU-centric power
1590 management operations described in ARM document number ARM DEN
1591 0022A ("Power State Coordination Interface System Software on
1594 # The GPIO number here must be sorted by descending number. In case of
1595 # a multiplatform kernel, we just want the highest value required by the
1596 # selected platforms.
1599 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1600 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1601 default 392 if ARCH_U8500
1602 default 352 if ARCH_VT8500
1603 default 288 if ARCH_SUNXI
1604 default 264 if MACH_H4700
1607 Maximum number of GPIOs in the system.
1609 If unsure, leave the default value.
1611 source kernel/Kconfig.preempt
1615 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1616 ARCH_S5PV210 || ARCH_EXYNOS4
1617 default AT91_TIMER_HZ if ARCH_AT91
1618 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1622 depends on HZ_FIXED = 0
1623 prompt "Timer frequency"
1647 default HZ_FIXED if HZ_FIXED != 0
1648 default 100 if HZ_100
1649 default 200 if HZ_200
1650 default 250 if HZ_250
1651 default 300 if HZ_300
1652 default 500 if HZ_500
1656 def_bool HIGH_RES_TIMERS
1659 def_bool HIGH_RES_TIMERS
1661 config THUMB2_KERNEL
1662 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1663 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1664 default y if CPU_THUMBONLY
1666 select ARM_ASM_UNIFIED
1669 By enabling this option, the kernel will be compiled in
1670 Thumb-2 mode. A compiler/assembler that understand the unified
1671 ARM-Thumb syntax is needed.
1675 config THUMB2_AVOID_R_ARM_THM_JUMP11
1676 bool "Work around buggy Thumb-2 short branch relocations in gas"
1677 depends on THUMB2_KERNEL && MODULES
1680 Various binutils versions can resolve Thumb-2 branches to
1681 locally-defined, preemptible global symbols as short-range "b.n"
1682 branch instructions.
1684 This is a problem, because there's no guarantee the final
1685 destination of the symbol, or any candidate locations for a
1686 trampoline, are within range of the branch. For this reason, the
1687 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1688 relocation in modules at all, and it makes little sense to add
1691 The symptom is that the kernel fails with an "unsupported
1692 relocation" error when loading some modules.
1694 Until fixed tools are available, passing
1695 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1696 code which hits this problem, at the cost of a bit of extra runtime
1697 stack usage in some cases.
1699 The problem is described in more detail at:
1700 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1702 Only Thumb-2 kernels are affected.
1704 Unless you are sure your tools don't have this problem, say Y.
1706 config ARM_ASM_UNIFIED
1710 bool "Use the ARM EABI to compile the kernel"
1712 This option allows for the kernel to be compiled using the latest
1713 ARM ABI (aka EABI). This is only useful if you are using a user
1714 space environment that is also compiled with EABI.
1716 Since there are major incompatibilities between the legacy ABI and
1717 EABI, especially with regard to structure member alignment, this
1718 option also changes the kernel syscall calling convention to
1719 disambiguate both ABIs and allow for backward compatibility support
1720 (selected with CONFIG_OABI_COMPAT).
1722 To use this you need GCC version 4.0.0 or later.
1725 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1726 depends on AEABI && !THUMB2_KERNEL
1728 This option preserves the old syscall interface along with the
1729 new (ARM EABI) one. It also provides a compatibility layer to
1730 intercept syscalls that have structure arguments which layout
1731 in memory differs between the legacy ABI and the new ARM EABI
1732 (only for non "thumb" binaries). This option adds a tiny
1733 overhead to all syscalls and produces a slightly larger kernel.
1735 The seccomp filter system will not be available when this is
1736 selected, since there is no way yet to sensibly distinguish
1737 between calling conventions during filtering.
1739 If you know you'll be using only pure EABI user space then you
1740 can say N here. If this option is not selected and you attempt
1741 to execute a legacy ABI binary then the result will be
1742 UNPREDICTABLE (in fact it can be predicted that it won't work
1743 at all). If in doubt say N.
1745 config ARCH_HAS_HOLES_MEMORYMODEL
1748 config ARCH_SPARSEMEM_ENABLE
1751 config ARCH_SPARSEMEM_DEFAULT
1752 def_bool ARCH_SPARSEMEM_ENABLE
1754 config ARCH_SELECT_MEMORY_MODEL
1755 def_bool ARCH_SPARSEMEM_ENABLE
1757 config HAVE_ARCH_PFN_VALID
1758 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1761 bool "High Memory Support"
1764 The address space of ARM processors is only 4 Gigabytes large
1765 and it has to accommodate user address space, kernel address
1766 space as well as some memory mapped IO. That means that, if you
1767 have a large amount of physical memory and/or IO, not all of the
1768 memory can be "permanently mapped" by the kernel. The physical
1769 memory that is not permanently mapped is called "high memory".
1771 Depending on the selected kernel/user memory split, minimum
1772 vmalloc space and actual amount of RAM, you may not need this
1773 option which should result in a slightly faster kernel.
1778 bool "Allocate 2nd-level pagetables from highmem"
1781 config HW_PERF_EVENTS
1782 bool "Enable hardware performance counter support for perf events"
1783 depends on PERF_EVENTS
1786 Enable hardware performance counter support for perf events. If
1787 disabled, perf events will use software events only.
1789 config SYS_SUPPORTS_HUGETLBFS
1793 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1797 config ARCH_WANT_GENERAL_HUGETLB
1802 config FORCE_MAX_ZONEORDER
1803 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1804 range 11 64 if ARCH_SHMOBILE_LEGACY
1805 default "12" if SOC_AM33XX
1806 default "9" if SA1111
1809 The kernel memory allocator divides physically contiguous memory
1810 blocks into "zones", where each zone is a power of two number of
1811 pages. This option selects the largest power of two that the kernel
1812 keeps in the memory allocator. If you need to allocate very large
1813 blocks of physically contiguous memory, then you may need to
1814 increase this value.
1816 This config option is actually maximum order plus one. For example,
1817 a value of 11 means that the largest free memory block is 2^10 pages.
1819 config ALIGNMENT_TRAP
1821 depends on CPU_CP15_MMU
1822 default y if !ARCH_EBSA110
1823 select HAVE_PROC_CPU if PROC_FS
1825 ARM processors cannot fetch/store information which is not
1826 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1827 address divisible by 4. On 32-bit ARM processors, these non-aligned
1828 fetch/store instructions will be emulated in software if you say
1829 here, which has a severe performance impact. This is necessary for
1830 correct operation of some network protocols. With an IP-only
1831 configuration it is safe to say N, otherwise say Y.
1833 config UACCESS_WITH_MEMCPY
1834 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1836 default y if CPU_FEROCEON
1838 Implement faster copy_to_user and clear_user methods for CPU
1839 cores where a 8-word STM instruction give significantly higher
1840 memory write throughput than a sequence of individual 32bit stores.
1842 A possible side effect is a slight increase in scheduling latency
1843 between threads sharing the same address space if they invoke
1844 such copy operations with large buffers.
1846 However, if the CPU data cache is using a write-allocate mode,
1847 this option is unlikely to provide any performance gain.
1851 prompt "Enable seccomp to safely compute untrusted bytecode"
1853 This kernel feature is useful for number crunching applications
1854 that may need to compute untrusted bytecode during their
1855 execution. By using pipes or other transports made available to
1856 the process as file descriptors supporting the read/write
1857 syscalls, it's possible to isolate those applications in
1858 their own address space using seccomp. Once seccomp is
1859 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1860 and the task is only allowed to execute a few safe syscalls
1861 defined by each seccomp mode.
1863 config CC_STACKPROTECTOR
1864 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1866 This option turns on the -fstack-protector GCC feature. This
1867 feature puts, at the beginning of functions, a canary value on
1868 the stack just before the return address, and validates
1869 the value just before actually returning. Stack based buffer
1870 overflows (that need to overwrite this return address) now also
1871 overwrite the canary, which gets detected and the attack is then
1872 neutralized via a kernel panic.
1873 This feature requires gcc version 4.2 or above.
1886 bool "Xen guest support on ARM (EXPERIMENTAL)"
1887 depends on ARM && AEABI && OF
1888 depends on CPU_V7 && !CPU_V6
1889 depends on !GENERIC_ATOMIC64
1893 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1900 bool "Flattened Device Tree support"
1903 select OF_EARLY_FLATTREE
1905 Include support for flattened device tree machine descriptions.
1908 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1911 This is the traditional way of passing data to the kernel at boot
1912 time. If you are solely relying on the flattened device tree (or
1913 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1914 to remove ATAGS support from your kernel binary. If unsure,
1917 config DEPRECATED_PARAM_STRUCT
1918 bool "Provide old way to pass kernel parameters"
1921 This was deprecated in 2001 and announced to live on for 5 years.
1922 Some old boot loaders still use this way.
1924 # Compressed boot loader in ROM. Yes, we really want to ask about
1925 # TEXT and BSS so we preserve their values in the config files.
1926 config ZBOOT_ROM_TEXT
1927 hex "Compressed ROM boot loader base address"
1930 The physical address at which the ROM-able zImage is to be
1931 placed in the target. Platforms which normally make use of
1932 ROM-able zImage formats normally set this to a suitable
1933 value in their defconfig file.
1935 If ZBOOT_ROM is not enabled, this has no effect.
1937 config ZBOOT_ROM_BSS
1938 hex "Compressed ROM boot loader BSS address"
1941 The base address of an area of read/write memory in the target
1942 for the ROM-able zImage which must be available while the
1943 decompressor is running. It must be large enough to hold the
1944 entire decompressed kernel plus an additional 128 KiB.
1945 Platforms which normally make use of ROM-able zImage formats
1946 normally set this to a suitable value in their defconfig file.
1948 If ZBOOT_ROM is not enabled, this has no effect.
1951 bool "Compressed boot loader in ROM/flash"
1952 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1954 Say Y here if you intend to execute your compressed kernel image
1955 (zImage) directly from ROM or flash. If unsure, say N.
1958 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1959 depends on ZBOOT_ROM && ARCH_SH7372
1960 default ZBOOT_ROM_NONE
1962 Include experimental SD/MMC loading code in the ROM-able zImage.
1963 With this enabled it is possible to write the ROM-able zImage
1964 kernel image to an MMC or SD card and boot the kernel straight
1965 from the reset vector. At reset the processor Mask ROM will load
1966 the first part of the ROM-able zImage which in turn loads the
1967 rest the kernel image to RAM.
1969 config ZBOOT_ROM_NONE
1970 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1972 Do not load image from SD or MMC
1974 config ZBOOT_ROM_MMCIF
1975 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1977 Load image from MMCIF hardware block.
1979 config ZBOOT_ROM_SH_MOBILE_SDHI
1980 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1982 Load image from SDHI hardware block
1986 config ARM_APPENDED_DTB
1987 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1988 depends on OF && !ZBOOT_ROM
1990 With this option, the boot code will look for a device tree binary
1991 (DTB) appended to zImage
1992 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1994 This is meant as a backward compatibility convenience for those
1995 systems with a bootloader that can't be upgraded to accommodate
1996 the documented boot protocol using a device tree.
1998 Beware that there is very little in terms of protection against
1999 this option being confused by leftover garbage in memory that might
2000 look like a DTB header after a reboot if no actual DTB is appended
2001 to zImage. Do not leave this option active in a production kernel
2002 if you don't intend to always append a DTB. Proper passing of the
2003 location into r2 of a bootloader provided DTB is always preferable
2006 config ARM_ATAG_DTB_COMPAT
2007 bool "Supplement the appended DTB with traditional ATAG information"
2008 depends on ARM_APPENDED_DTB
2010 Some old bootloaders can't be updated to a DTB capable one, yet
2011 they provide ATAGs with memory configuration, the ramdisk address,
2012 the kernel cmdline string, etc. Such information is dynamically
2013 provided by the bootloader and can't always be stored in a static
2014 DTB. To allow a device tree enabled kernel to be used with such
2015 bootloaders, this option allows zImage to extract the information
2016 from the ATAG list and store it at run time into the appended DTB.
2019 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2020 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2022 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2023 bool "Use bootloader kernel arguments if available"
2025 Uses the command-line options passed by the boot loader instead of
2026 the device tree bootargs property. If the boot loader doesn't provide
2027 any, the device tree bootargs property will be used.
2029 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2030 bool "Extend with bootloader kernel arguments"
2032 The command-line arguments provided by the boot loader will be
2033 appended to the the device tree bootargs property.
2038 string "Default kernel command string"
2041 On some architectures (EBSA110 and CATS), there is currently no way
2042 for the boot loader to pass arguments to the kernel. For these
2043 architectures, you should supply some command-line options at build
2044 time by entering them here. As a minimum, you should specify the
2045 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2048 prompt "Kernel command line type" if CMDLINE != ""
2049 default CMDLINE_FROM_BOOTLOADER
2052 config CMDLINE_FROM_BOOTLOADER
2053 bool "Use bootloader kernel arguments if available"
2055 Uses the command-line options passed by the boot loader. If
2056 the boot loader doesn't provide any, the default kernel command
2057 string provided in CMDLINE will be used.
2059 config CMDLINE_EXTEND
2060 bool "Extend bootloader kernel arguments"
2062 The command-line arguments provided by the boot loader will be
2063 appended to the default kernel command string.
2065 config CMDLINE_FORCE
2066 bool "Always use the default kernel command string"
2068 Always use the default kernel command string, even if the boot
2069 loader passes other arguments to the kernel.
2070 This is useful if you cannot or don't want to change the
2071 command-line options your boot loader passes to the kernel.
2075 bool "Kernel Execute-In-Place from ROM"
2076 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2078 Execute-In-Place allows the kernel to run from non-volatile storage
2079 directly addressable by the CPU, such as NOR flash. This saves RAM
2080 space since the text section of the kernel is not loaded from flash
2081 to RAM. Read-write sections, such as the data section and stack,
2082 are still copied to RAM. The XIP kernel is not compressed since
2083 it has to run directly from flash, so it will take more space to
2084 store it. The flash address used to link the kernel object files,
2085 and for storing it, is configuration dependent. Therefore, if you
2086 say Y here, you must know the proper physical address where to
2087 store the kernel image depending on your own flash memory usage.
2089 Also note that the make target becomes "make xipImage" rather than
2090 "make zImage" or "make Image". The final kernel binary to put in
2091 ROM memory will be arch/arm/boot/xipImage.
2095 config XIP_PHYS_ADDR
2096 hex "XIP Kernel Physical Location"
2097 depends on XIP_KERNEL
2098 default "0x00080000"
2100 This is the physical address in your flash memory the kernel will
2101 be linked for and stored to. This address is dependent on your
2105 bool "Kexec system call (EXPERIMENTAL)"
2106 depends on (!SMP || PM_SLEEP_SMP)
2108 kexec is a system call that implements the ability to shutdown your
2109 current kernel, and to start another kernel. It is like a reboot
2110 but it is independent of the system firmware. And like a reboot
2111 you can start any kernel with it, not just Linux.
2113 It is an ongoing process to be certain the hardware in a machine
2114 is properly shutdown, so do not be surprised if this code does not
2115 initially work for you.
2118 bool "Export atags in procfs"
2119 depends on ATAGS && KEXEC
2122 Should the atags used to boot the kernel be exported in an "atags"
2123 file in procfs. Useful with kexec.
2126 bool "Build kdump crash kernel (EXPERIMENTAL)"
2128 Generate crash dump after being started by kexec. This should
2129 be normally only set in special crash dump kernels which are
2130 loaded in the main kernel with kexec-tools into a specially
2131 reserved region and then later executed after a crash by
2132 kdump/kexec. The crash dump kernel must be compiled to a
2133 memory address not used by the main kernel
2135 For more details see Documentation/kdump/kdump.txt
2137 config AUTO_ZRELADDR
2138 bool "Auto calculation of the decompressed kernel image address"
2139 depends on !ZBOOT_ROM
2141 ZRELADDR is the physical address where the decompressed kernel
2142 image will be placed. If AUTO_ZRELADDR is selected, the address
2143 will be determined at run-time by masking the current IP with
2144 0xf8000000. This assumes the zImage being placed in the first 128MB
2145 from start of memory.
2149 menu "CPU Power Management"
2152 source "drivers/cpufreq/Kconfig"
2155 source "drivers/cpuidle/Kconfig"
2159 menu "Floating point emulation"
2161 comment "At least one emulation must be selected"
2164 bool "NWFPE math emulation"
2165 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2167 Say Y to include the NWFPE floating point emulator in the kernel.
2168 This is necessary to run most binaries. Linux does not currently
2169 support floating point hardware so you need to say Y here even if
2170 your machine has an FPA or floating point co-processor podule.
2172 You may say N here if you are going to load the Acorn FPEmulator
2173 early in the bootup.
2176 bool "Support extended precision"
2177 depends on FPE_NWFPE
2179 Say Y to include 80-bit support in the kernel floating-point
2180 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2181 Note that gcc does not generate 80-bit operations by default,
2182 so in most cases this option only enlarges the size of the
2183 floating point emulator without any good reason.
2185 You almost surely want to say N here.
2188 bool "FastFPE math emulation (EXPERIMENTAL)"
2189 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2191 Say Y here to include the FAST floating point emulator in the kernel.
2192 This is an experimental much faster emulator which now also has full
2193 precision for the mantissa. It does not support any exceptions.
2194 It is very simple, and approximately 3-6 times faster than NWFPE.
2196 It should be sufficient for most programs. It may be not suitable
2197 for scientific calculations, but you have to check this for yourself.
2198 If you do not feel you need a faster FP emulation you should better
2202 bool "VFP-format floating point maths"
2203 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2205 Say Y to include VFP support code in the kernel. This is needed
2206 if your hardware includes a VFP unit.
2208 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2209 release notes and additional status information.
2211 Say N if your target does not have VFP hardware.
2219 bool "Advanced SIMD (NEON) Extension support"
2220 depends on VFPv3 && CPU_V7
2222 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2225 config KERNEL_MODE_NEON
2226 bool "Support for NEON in kernel mode"
2227 depends on NEON && AEABI
2229 Say Y to include support for NEON in kernel mode.
2233 menu "Userspace binary formats"
2235 source "fs/Kconfig.binfmt"
2238 tristate "RISC OS personality"
2241 Say Y here to include the kernel code necessary if you want to run
2242 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2243 experimental; if this sounds frightening, say N and sleep in peace.
2244 You can also say M here to compile this support as a module (which
2245 will be called arthur).
2249 menu "Power management options"
2251 source "kernel/power/Kconfig"
2253 config ARCH_SUSPEND_POSSIBLE
2254 depends on !ARCH_S5PC100
2255 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2256 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2259 config ARM_CPU_SUSPEND
2264 source "net/Kconfig"
2266 source "drivers/Kconfig"
2270 source "arch/arm/Kconfig.debug"
2272 source "security/Kconfig"
2274 source "crypto/Kconfig"
2276 source "lib/Kconfig"
2278 source "arch/arm/kvm/Kconfig"