4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
18 select GENERIC_ALLOCATOR
19 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
20 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_IRQ_PROBE
23 select GENERIC_IRQ_SHOW
24 select GENERIC_IRQ_SHOW_LEVEL
25 select GENERIC_PCI_IOMAP
26 select GENERIC_SCHED_CLOCK
27 select GENERIC_SMP_IDLE_THREAD
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select HANDLE_DOMAIN_IRQ
31 select HARDIRQS_SW_RESEND
32 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
33 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
34 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
36 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_TRACEHOOK
39 select HAVE_CC_STACKPROTECTOR
40 select HAVE_CONTEXT_TRACKING
41 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK
43 select HAVE_DMA_API_DEBUG
45 select HAVE_DMA_CONTIGUOUS if MMU
46 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
47 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
48 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
49 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
50 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
51 select HAVE_GENERIC_DMA_COHERENT
52 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
53 select HAVE_IDE if PCI || ISA || PCMCIA
54 select HAVE_IRQ_TIME_ACCOUNTING
55 select HAVE_KERNEL_GZIP
56 select HAVE_KERNEL_LZ4
57 select HAVE_KERNEL_LZMA
58 select HAVE_KERNEL_LZO
60 select HAVE_KPROBES if !XIP_KERNEL
61 select HAVE_KRETPROBES if (HAVE_KPROBES)
63 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
64 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
65 select HAVE_OPTPROBES if !THUMB2_KERNEL
66 select HAVE_PERF_EVENTS
68 select HAVE_PERF_USER_STACK_DUMP
69 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
70 select HAVE_REGS_AND_STACK_ACCESS_API
71 select HAVE_SYSCALL_TRACEPOINTS
73 select HAVE_VIRT_CPU_ACCOUNTING_GEN
74 select IRQ_FORCED_THREADING
75 select MODULES_USE_ELF_REL
78 select OLD_SIGSUSPEND3
79 select PERF_USE_VMALLOC
81 select SYS_SUPPORTS_APM_EMULATION
82 # Above selects are sorted alphabetically; please add new ones
83 # according to that. Thanks.
85 The ARM series is a line of low-power-consumption RISC chip designs
86 licensed by ARM Ltd and targeted at embedded applications and
87 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
88 manufactured, but legacy ARM-based PC hardware remains popular in
89 Europe. There is an ARM Linux project with a web page at
90 <http://www.arm.linux.org.uk/>.
92 config ARM_HAS_SG_CHAIN
93 select ARCH_HAS_SG_CHAIN
96 config NEED_SG_DMA_LENGTH
99 config ARM_DMA_USE_IOMMU
101 select ARM_HAS_SG_CHAIN
102 select NEED_SG_DMA_LENGTH
106 config ARM_DMA_IOMMU_ALIGNMENT
107 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
111 DMA mapping framework by default aligns all buffers to the smallest
112 PAGE_SIZE order which is greater than or equal to the requested buffer
113 size. This works well for buffers up to a few hundreds kilobytes, but
114 for larger buffers it just a waste of address space. Drivers which has
115 relatively small addressing window (like 64Mib) might run out of
116 virtual space with just a few allocations.
118 With this parameter you can specify the maximum PAGE_SIZE order for
119 DMA IOMMU buffers. Larger buffers will be aligned only to this
120 specified order. The order is expressed as a power of two multiplied
125 config MIGHT_HAVE_PCI
128 config SYS_SUPPORTS_APM_EMULATION
133 select GENERIC_ALLOCATOR
144 The Extended Industry Standard Architecture (EISA) bus was
145 developed as an open alternative to the IBM MicroChannel bus.
147 The EISA bus provided some of the features of the IBM MicroChannel
148 bus while maintaining backward compatibility with cards made for
149 the older ISA bus. The EISA bus saw limited use between 1988 and
150 1995 when it was made obsolete by the PCI bus.
152 Say Y here if you are building a kernel for an EISA-based machine.
159 config STACKTRACE_SUPPORT
163 config HAVE_LATENCYTOP_SUPPORT
168 config LOCKDEP_SUPPORT
172 config TRACE_IRQFLAGS_SUPPORT
176 config RWSEM_XCHGADD_ALGORITHM
180 config ARCH_HAS_ILOG2_U32
183 config ARCH_HAS_ILOG2_U64
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_SUPPORTS_UPROBES
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
269 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
274 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 default 0x20000000 if ARCH_S5PV210
277 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
309 # The "ARM system type" choice list is ordered alphabetically by option
310 # text. Please add new entries in the option alphabetic order.
313 prompt "ARM system type"
314 default ARCH_VERSATILE if !MMU
315 default ARCH_MULTIPLATFORM if MMU
317 config ARCH_MULTIPLATFORM
318 bool "Allow multiple platforms to be selected"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_HAS_SG_CHAIN
322 select ARM_PATCH_PHYS_VIRT
326 select GENERIC_CLOCKEVENTS
327 select MIGHT_HAVE_PCI
328 select MULTI_IRQ_HANDLER
333 bool "ARM Ltd. RealView family"
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_TIMER_SP804
338 select COMMON_CLK_VERSATILE
339 select GENERIC_CLOCKEVENTS
340 select GPIO_PL061 if GPIOLIB
342 select NEED_MACH_MEMORY_H
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_SCHED_CLOCK
346 This enables support for ARM Ltd RealView boards.
348 config ARCH_VERSATILE
349 bool "ARM Ltd. Versatile family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
356 select HAVE_MACH_CLKDEV
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_CLOCK
360 select PLAT_VERSATILE_SCHED_CLOCK
361 select VERSATILE_FPGA_IRQ
363 This enables support for ARM Ltd Versatile board.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367 select ARCH_REQUIRE_GPIOLIB
372 select GENERIC_CLOCKEVENTS
376 Support for Cirrus Logic 711x/721x/731x based boards.
379 bool "Cortina Systems Gemini"
380 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
385 Support for the Cortina Systems Gemini family SoCs
389 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_IO_H
393 select NEED_MACH_MEMORY_H
396 This is an evaluation board for the StrongARM processor available
397 from Digital. It has limited hardware on-board, including an
398 Ethernet interface, two PCMCIA sockets, two serial ports and a
402 bool "Energy Micro efm32"
404 select ARCH_REQUIRE_GPIOLIB
410 select GENERIC_CLOCKEVENTS
416 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
421 select ARCH_HAS_HOLES_MEMORYMODEL
422 select ARCH_REQUIRE_GPIOLIB
423 select ARCH_USES_GETTIMEOFFSET
429 This enables support for the Cirrus EP93xx series of CPUs.
431 config ARCH_FOOTBRIDGE
435 select GENERIC_CLOCKEVENTS
437 select NEED_MACH_IO_H if !MMU
438 select NEED_MACH_MEMORY_H
440 Support for systems based on the DC21285 companion chip
441 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
444 bool "Hilscher NetX based"
448 select GENERIC_CLOCKEVENTS
450 This enables support for systems based on the Hilscher NetX Soc
456 select NEED_MACH_MEMORY_H
457 select NEED_RET_TO_USER
463 Support for Intel's IOP13XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
471 select NEED_RET_TO_USER
475 Support for Intel's 80219 and IOP32X (XScale) family of
481 select ARCH_REQUIRE_GPIOLIB
484 select NEED_RET_TO_USER
488 Support for Intel's IOP33X (XScale) family of processors.
493 select ARCH_HAS_DMA_SET_COHERENT_MASK
494 select ARCH_REQUIRE_GPIOLIB
495 select ARCH_SUPPORTS_BIG_ENDIAN
498 select DMABOUNCE if PCI
499 select GENERIC_CLOCKEVENTS
500 select MIGHT_HAVE_PCI
501 select NEED_MACH_IO_H
502 select USB_EHCI_BIG_ENDIAN_DESC
503 select USB_EHCI_BIG_ENDIAN_MMIO
505 Support for Intel's IXP4XX (XScale) family of processors.
509 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
512 select MIGHT_HAVE_PCI
516 select PLAT_ORION_LEGACY
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
527 select PLAT_ORION_LEGACY
529 Support for the following Marvell MV78xx0 series SoCs:
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
542 Support for the following Marvell Orion 5x series SoCs:
543 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
544 Orion-2 (5281), Orion-1-90 (6183).
547 bool "Marvell PXA168/910/MMP2"
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_ALLOCATOR
552 select GENERIC_CLOCKEVENTS
555 select MULTI_IRQ_HANDLER
560 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
563 bool "Micrel/Kendin KS8695"
564 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
568 select NEED_MACH_MEMORY_H
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
575 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
600 Support for the NXP LPC32XX family of processors
603 bool "PXA2xx/PXA3xx-based"
606 select ARCH_REQUIRE_GPIOLIB
607 select ARM_CPU_SUSPEND if PM
613 select GENERIC_CLOCKEVENTS
617 select MULTI_IRQ_HANDLER
621 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
623 config ARCH_SHMOBILE_LEGACY
624 bool "Renesas ARM SoCs (non-multiplatform)"
626 select ARM_PATCH_PHYS_VIRT if MMU
629 select GENERIC_CLOCKEVENTS
630 select HAVE_ARM_SCU if SMP
631 select HAVE_ARM_TWD if SMP
633 select MIGHT_HAVE_CACHE_L2X0
634 select MULTI_IRQ_HANDLER
637 select PM_GENERIC_DOMAINS if PM
641 Support for Renesas ARM SoC platforms using a non-multiplatform
642 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
648 select ARCH_MAY_HAVE_PC_FDC
649 select ARCH_SPARSEMEM_ENABLE
650 select ARCH_USES_GETTIMEOFFSET
654 select HAVE_PATA_PLATFORM
656 select NEED_MACH_IO_H
657 select NEED_MACH_MEMORY_H
661 On the Acorn Risc-PC, Linux can support the internal IDE disk and
662 CD-ROM interface, serial and parallel port, and the floppy drive.
667 select ARCH_REQUIRE_GPIOLIB
668 select ARCH_SPARSEMEM_ENABLE
673 select GENERIC_CLOCKEVENTS
677 select MULTI_IRQ_HANDLER
678 select NEED_MACH_MEMORY_H
681 Support for StrongARM 11x0 based boards.
684 bool "Samsung S3C24XX SoCs"
685 select ARCH_REQUIRE_GPIOLIB
688 select CLKSRC_SAMSUNG_PWM
689 select GENERIC_CLOCKEVENTS
691 select HAVE_S3C2410_I2C if I2C
692 select HAVE_S3C2410_WATCHDOG if WATCHDOG
693 select HAVE_S3C_RTC if RTC_CLASS
694 select MULTI_IRQ_HANDLER
695 select NEED_MACH_IO_H
698 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
699 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
700 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
701 Samsung SMDK2410 development board (and derivatives).
704 bool "Samsung S3C64XX"
705 select ARCH_REQUIRE_GPIOLIB
710 select CLKSRC_SAMSUNG_PWM
711 select COMMON_CLK_SAMSUNG
713 select GENERIC_CLOCKEVENTS
715 select HAVE_S3C2410_I2C if I2C
716 select HAVE_S3C2410_WATCHDOG if WATCHDOG
720 select PM_GENERIC_DOMAINS if PM
722 select S3C_GPIO_TRACK
724 select SAMSUNG_WAKEMASK
725 select SAMSUNG_WDT_RESET
727 Samsung S3C64XX series based systems
731 select ARCH_HAS_HOLES_MEMORYMODEL
732 select ARCH_REQUIRE_GPIOLIB
734 select GENERIC_ALLOCATOR
735 select GENERIC_CLOCKEVENTS
736 select GENERIC_IRQ_CHIP
742 Support for TI's DaVinci platform.
747 select ARCH_HAS_HOLES_MEMORYMODEL
749 select ARCH_REQUIRE_GPIOLIB
752 select GENERIC_CLOCKEVENTS
753 select GENERIC_IRQ_CHIP
756 select NEED_MACH_IO_H if PCCARD
757 select NEED_MACH_MEMORY_H
759 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
763 menu "Multiple platform selection"
764 depends on ARCH_MULTIPLATFORM
766 comment "CPU Core family selection"
769 bool "ARMv4 based platforms (FA526)"
770 depends on !ARCH_MULTI_V6_V7
771 select ARCH_MULTI_V4_V5
774 config ARCH_MULTI_V4T
775 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
776 depends on !ARCH_MULTI_V6_V7
777 select ARCH_MULTI_V4_V5
778 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
779 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
780 CPU_ARM925T || CPU_ARM940T)
783 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
784 depends on !ARCH_MULTI_V6_V7
785 select ARCH_MULTI_V4_V5
786 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
787 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
788 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
790 config ARCH_MULTI_V4_V5
794 bool "ARMv6 based platforms (ARM11)"
795 select ARCH_MULTI_V6_V7
799 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
801 select ARCH_MULTI_V6_V7
805 config ARCH_MULTI_V6_V7
807 select MIGHT_HAVE_CACHE_L2X0
809 config ARCH_MULTI_CPU_AUTO
810 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
816 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
820 select HAVE_ARM_ARCH_TIMER
823 # This is sorted alphabetically by mach-* pathname. However, plat-*
824 # Kconfigs may be included either alphabetically (according to the
825 # plat- suffix) or along side the corresponding mach-* source.
827 source "arch/arm/mach-mvebu/Kconfig"
829 source "arch/arm/mach-alpine/Kconfig"
831 source "arch/arm/mach-asm9260/Kconfig"
833 source "arch/arm/mach-at91/Kconfig"
835 source "arch/arm/mach-axxia/Kconfig"
837 source "arch/arm/mach-bcm/Kconfig"
839 source "arch/arm/mach-berlin/Kconfig"
841 source "arch/arm/mach-clps711x/Kconfig"
843 source "arch/arm/mach-cns3xxx/Kconfig"
845 source "arch/arm/mach-davinci/Kconfig"
847 source "arch/arm/mach-digicolor/Kconfig"
849 source "arch/arm/mach-dove/Kconfig"
851 source "arch/arm/mach-ep93xx/Kconfig"
853 source "arch/arm/mach-footbridge/Kconfig"
855 source "arch/arm/mach-gemini/Kconfig"
857 source "arch/arm/mach-highbank/Kconfig"
859 source "arch/arm/mach-hisi/Kconfig"
861 source "arch/arm/mach-integrator/Kconfig"
863 source "arch/arm/mach-iop32x/Kconfig"
865 source "arch/arm/mach-iop33x/Kconfig"
867 source "arch/arm/mach-iop13xx/Kconfig"
869 source "arch/arm/mach-ixp4xx/Kconfig"
871 source "arch/arm/mach-keystone/Kconfig"
873 source "arch/arm/mach-ks8695/Kconfig"
875 source "arch/arm/mach-meson/Kconfig"
877 source "arch/arm/mach-moxart/Kconfig"
879 source "arch/arm/mach-mv78xx0/Kconfig"
881 source "arch/arm/mach-imx/Kconfig"
883 source "arch/arm/mach-mediatek/Kconfig"
885 source "arch/arm/mach-mxs/Kconfig"
887 source "arch/arm/mach-netx/Kconfig"
889 source "arch/arm/mach-nomadik/Kconfig"
891 source "arch/arm/mach-nspire/Kconfig"
893 source "arch/arm/plat-omap/Kconfig"
895 source "arch/arm/mach-omap1/Kconfig"
897 source "arch/arm/mach-omap2/Kconfig"
899 source "arch/arm/mach-orion5x/Kconfig"
901 source "arch/arm/mach-picoxcell/Kconfig"
903 source "arch/arm/mach-pxa/Kconfig"
904 source "arch/arm/plat-pxa/Kconfig"
906 source "arch/arm/mach-mmp/Kconfig"
908 source "arch/arm/mach-qcom/Kconfig"
910 source "arch/arm/mach-realview/Kconfig"
912 source "arch/arm/mach-rockchip/Kconfig"
914 source "arch/arm/mach-sa1100/Kconfig"
916 source "arch/arm/mach-socfpga/Kconfig"
918 source "arch/arm/mach-spear/Kconfig"
920 source "arch/arm/mach-sti/Kconfig"
922 source "arch/arm/mach-s3c24xx/Kconfig"
924 source "arch/arm/mach-s3c64xx/Kconfig"
926 source "arch/arm/mach-s5pv210/Kconfig"
928 source "arch/arm/mach-exynos/Kconfig"
929 source "arch/arm/plat-samsung/Kconfig"
931 source "arch/arm/mach-shmobile/Kconfig"
933 source "arch/arm/mach-sunxi/Kconfig"
935 source "arch/arm/mach-prima2/Kconfig"
937 source "arch/arm/mach-tegra/Kconfig"
939 source "arch/arm/mach-u300/Kconfig"
941 source "arch/arm/mach-uniphier/Kconfig"
943 source "arch/arm/mach-ux500/Kconfig"
945 source "arch/arm/mach-versatile/Kconfig"
947 source "arch/arm/mach-vexpress/Kconfig"
948 source "arch/arm/plat-versatile/Kconfig"
950 source "arch/arm/mach-vt8500/Kconfig"
952 source "arch/arm/mach-w90x900/Kconfig"
954 source "arch/arm/mach-zynq/Kconfig"
956 # Definitions to make life easier
962 select GENERIC_CLOCKEVENTS
968 select GENERIC_IRQ_CHIP
971 config PLAT_ORION_LEGACY
978 config PLAT_VERSATILE
981 config ARM_TIMER_SP804
984 select CLKSRC_OF if OF
986 source "arch/arm/firmware/Kconfig"
988 source arch/arm/mm/Kconfig
991 bool "Enable iWMMXt support"
992 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
993 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
995 Enable support for iWMMXt context switching at run time if
996 running on a CPU that supports it.
998 config MULTI_IRQ_HANDLER
1001 Allow each machine to specify it's own IRQ handler at run time.
1004 source "arch/arm/Kconfig-nommu"
1007 config PJ4B_ERRATA_4742
1008 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1009 depends on CPU_PJ4B && MACH_ARMADA_370
1012 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1013 Event (WFE) IDLE states, a specific timing sensitivity exists between
1014 the retiring WFI/WFE instructions and the newly issued subsequent
1015 instructions. This sensitivity can result in a CPU hang scenario.
1017 The software must insert either a Data Synchronization Barrier (DSB)
1018 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1021 config ARM_ERRATA_326103
1022 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1025 Executing a SWP instruction to read-only memory does not set bit 11
1026 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1027 treat the access as a read, preventing a COW from occurring and
1028 causing the faulting task to livelock.
1030 config ARM_ERRATA_411920
1031 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1032 depends on CPU_V6 || CPU_V6K
1034 Invalidation of the Instruction Cache operation can
1035 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1036 It does not affect the MPCore. This option enables the ARM Ltd.
1037 recommended workaround.
1039 config ARM_ERRATA_430973
1040 bool "ARM errata: Stale prediction on replaced interworking branch"
1043 This option enables the workaround for the 430973 Cortex-A8
1044 r1p* erratum. If a code sequence containing an ARM/Thumb
1045 interworking branch is replaced with another code sequence at the
1046 same virtual address, whether due to self-modifying code or virtual
1047 to physical address re-mapping, Cortex-A8 does not recover from the
1048 stale interworking branch prediction. This results in Cortex-A8
1049 executing the new code sequence in the incorrect ARM or Thumb state.
1050 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1051 and also flushes the branch target cache at every context switch.
1052 Note that setting specific bits in the ACTLR register may not be
1053 available in non-secure mode.
1055 config ARM_ERRATA_458693
1056 bool "ARM errata: Processor deadlock when a false hazard is created"
1058 depends on !ARCH_MULTIPLATFORM
1060 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1061 erratum. For very specific sequences of memory operations, it is
1062 possible for a hazard condition intended for a cache line to instead
1063 be incorrectly associated with a different cache line. This false
1064 hazard might then cause a processor deadlock. The workaround enables
1065 the L1 caching of the NEON accesses and disables the PLD instruction
1066 in the ACTLR register. Note that setting specific bits in the ACTLR
1067 register may not be available in non-secure mode.
1069 config ARM_ERRATA_460075
1070 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1072 depends on !ARCH_MULTIPLATFORM
1074 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1075 erratum. Any asynchronous access to the L2 cache may encounter a
1076 situation in which recent store transactions to the L2 cache are lost
1077 and overwritten with stale memory contents from external memory. The
1078 workaround disables the write-allocate mode for the L2 cache via the
1079 ACTLR register. Note that setting specific bits in the ACTLR register
1080 may not be available in non-secure mode.
1082 config ARM_ERRATA_742230
1083 bool "ARM errata: DMB operation may be faulty"
1084 depends on CPU_V7 && SMP
1085 depends on !ARCH_MULTIPLATFORM
1087 This option enables the workaround for the 742230 Cortex-A9
1088 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1089 between two write operations may not ensure the correct visibility
1090 ordering of the two writes. This workaround sets a specific bit in
1091 the diagnostic register of the Cortex-A9 which causes the DMB
1092 instruction to behave as a DSB, ensuring the correct behaviour of
1095 config ARM_ERRATA_742231
1096 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1097 depends on CPU_V7 && SMP
1098 depends on !ARCH_MULTIPLATFORM
1100 This option enables the workaround for the 742231 Cortex-A9
1101 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1102 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1103 accessing some data located in the same cache line, may get corrupted
1104 data due to bad handling of the address hazard when the line gets
1105 replaced from one of the CPUs at the same time as another CPU is
1106 accessing it. This workaround sets specific bits in the diagnostic
1107 register of the Cortex-A9 which reduces the linefill issuing
1108 capabilities of the processor.
1110 config ARM_ERRATA_643719
1111 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1112 depends on CPU_V7 && SMP
1115 This option enables the workaround for the 643719 Cortex-A9 (prior to
1116 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1117 register returns zero when it should return one. The workaround
1118 corrects this value, ensuring cache maintenance operations which use
1119 it behave as intended and avoiding data corruption.
1121 config ARM_ERRATA_720789
1122 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1125 This option enables the workaround for the 720789 Cortex-A9 (prior to
1126 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1127 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1128 As a consequence of this erratum, some TLB entries which should be
1129 invalidated are not, resulting in an incoherency in the system page
1130 tables. The workaround changes the TLB flushing routines to invalidate
1131 entries regardless of the ASID.
1133 config ARM_ERRATA_743622
1134 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1136 depends on !ARCH_MULTIPLATFORM
1138 This option enables the workaround for the 743622 Cortex-A9
1139 (r2p*) erratum. Under very rare conditions, a faulty
1140 optimisation in the Cortex-A9 Store Buffer may lead to data
1141 corruption. This workaround sets a specific bit in the diagnostic
1142 register of the Cortex-A9 which disables the Store Buffer
1143 optimisation, preventing the defect from occurring. This has no
1144 visible impact on the overall performance or power consumption of the
1147 config ARM_ERRATA_751472
1148 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1150 depends on !ARCH_MULTIPLATFORM
1152 This option enables the workaround for the 751472 Cortex-A9 (prior
1153 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1154 completion of a following broadcasted operation if the second
1155 operation is received by a CPU before the ICIALLUIS has completed,
1156 potentially leading to corrupted entries in the cache or TLB.
1158 config ARM_ERRATA_754322
1159 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1162 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1163 r3p*) erratum. A speculative memory access may cause a page table walk
1164 which starts prior to an ASID switch but completes afterwards. This
1165 can populate the micro-TLB with a stale entry which may be hit with
1166 the new ASID. This workaround places two dsb instructions in the mm
1167 switching code so that no page table walks can cross the ASID switch.
1169 config ARM_ERRATA_754327
1170 bool "ARM errata: no automatic Store Buffer drain"
1171 depends on CPU_V7 && SMP
1173 This option enables the workaround for the 754327 Cortex-A9 (prior to
1174 r2p0) erratum. The Store Buffer does not have any automatic draining
1175 mechanism and therefore a livelock may occur if an external agent
1176 continuously polls a memory location waiting to observe an update.
1177 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1178 written polling loops from denying visibility of updates to memory.
1180 config ARM_ERRATA_364296
1181 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1184 This options enables the workaround for the 364296 ARM1136
1185 r0p2 erratum (possible cache data corruption with
1186 hit-under-miss enabled). It sets the undocumented bit 31 in
1187 the auxiliary control register and the FI bit in the control
1188 register, thus disabling hit-under-miss without putting the
1189 processor into full low interrupt latency mode. ARM11MPCore
1192 config ARM_ERRATA_764369
1193 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for erratum 764369
1197 affecting Cortex-A9 MPCore with two or more processors (all
1198 current revisions). Under certain timing circumstances, a data
1199 cache line maintenance operation by MVA targeting an Inner
1200 Shareable memory region may fail to proceed up to either the
1201 Point of Coherency or to the Point of Unification of the
1202 system. This workaround adds a DSB instruction before the
1203 relevant cache maintenance functions and sets a specific bit
1204 in the diagnostic control register of the SCU.
1206 config ARM_ERRATA_775420
1207 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1210 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1211 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1212 operation aborts with MMU exception, it might cause the processor
1213 to deadlock. This workaround puts DSB before executing ISB if
1214 an abort may occur on cache maintenance.
1216 config ARM_ERRATA_798181
1217 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1218 depends on CPU_V7 && SMP
1220 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1221 adequately shooting down all use of the old entries. This
1222 option enables the Linux kernel workaround for this erratum
1223 which sends an IPI to the CPUs that are running the same ASID
1224 as the one being invalidated.
1226 config ARM_ERRATA_773022
1227 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1230 This option enables the workaround for the 773022 Cortex-A15
1231 (up to r0p4) erratum. In certain rare sequences of code, the
1232 loop buffer may deliver incorrect instructions. This
1233 workaround disables the loop buffer to avoid the erratum.
1237 source "arch/arm/common/Kconfig"
1244 Find out whether you have ISA slots on your motherboard. ISA is the
1245 name of a bus system, i.e. the way the CPU talks to the other stuff
1246 inside your box. Other bus systems are PCI, EISA, MicroChannel
1247 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1248 newer boards don't support it. If you have ISA, say Y, otherwise N.
1250 # Select ISA DMA controller support
1255 # Select ISA DMA interface
1260 bool "PCI support" if MIGHT_HAVE_PCI
1262 Find out whether you have a PCI motherboard. PCI is the name of a
1263 bus system, i.e. the way the CPU talks to the other stuff inside
1264 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1265 VESA. If you have PCI, say Y, otherwise N.
1271 config PCI_DOMAINS_GENERIC
1272 def_bool PCI_DOMAINS
1274 config PCI_NANOENGINE
1275 bool "BSE nanoEngine PCI support"
1276 depends on SA1100_NANOENGINE
1278 Enable PCI on the BSE nanoEngine board.
1283 config PCI_HOST_ITE8152
1285 depends on PCI && MACH_ARMCORE
1289 source "drivers/pci/Kconfig"
1290 source "drivers/pci/pcie/Kconfig"
1292 source "drivers/pcmcia/Kconfig"
1296 menu "Kernel Features"
1301 This option should be selected by machines which have an SMP-
1304 The only effect of this option is to make the SMP-related
1305 options available to the user for configuration.
1308 bool "Symmetric Multi-Processing"
1309 depends on CPU_V6K || CPU_V7
1310 depends on GENERIC_CLOCKEVENTS
1312 depends on MMU || ARM_MPU
1314 This enables support for systems with more than one CPU. If you have
1315 a system with only one CPU, say N. If you have a system with more
1316 than one CPU, say Y.
1318 If you say N here, the kernel will run on uni- and multiprocessor
1319 machines, but will use only one CPU of a multiprocessor machine. If
1320 you say Y here, the kernel will run on many, but not all,
1321 uniprocessor machines. On a uniprocessor machine, the kernel
1322 will run faster if you say N here.
1324 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1325 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1326 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1328 If you don't know what to do here, say N.
1331 bool "Allow booting SMP kernel on uniprocessor systems"
1332 depends on SMP && !XIP_KERNEL && MMU
1335 SMP kernels contain instructions which fail on non-SMP processors.
1336 Enabling this option allows the kernel to modify itself to make
1337 these instructions safe. Disabling it allows about 1K of space
1340 If you don't know what to do here, say Y.
1342 config ARM_CPU_TOPOLOGY
1343 bool "Support cpu topology definition"
1344 depends on SMP && CPU_V7
1347 Support ARM cpu topology definition. The MPIDR register defines
1348 affinity between processors which is then used to describe the cpu
1349 topology of an ARM System.
1352 bool "Multi-core scheduler support"
1353 depends on ARM_CPU_TOPOLOGY
1355 Multi-core scheduler support improves the CPU scheduler's decision
1356 making when dealing with multi-core CPU chips at a cost of slightly
1357 increased overhead in some places. If unsure say N here.
1360 bool "SMT scheduler support"
1361 depends on ARM_CPU_TOPOLOGY
1363 Improves the CPU scheduler's decision making when dealing with
1364 MultiThreading at a cost of slightly increased overhead in some
1365 places. If unsure say N here.
1370 This option enables support for the ARM system coherency unit
1372 config HAVE_ARM_ARCH_TIMER
1373 bool "Architected timer support"
1375 select ARM_ARCH_TIMER
1376 select GENERIC_CLOCKEVENTS
1378 This option enables support for the ARM architected timer
1383 select CLKSRC_OF if OF
1385 This options enables support for the ARM timer and watchdog unit
1388 bool "Multi-Cluster Power Management"
1389 depends on CPU_V7 && SMP
1391 This option provides the common power management infrastructure
1392 for (multi-)cluster based systems, such as big.LITTLE based
1395 config MCPM_QUAD_CLUSTER
1399 To avoid wasting resources unnecessarily, MCPM only supports up
1400 to 2 clusters by default.
1401 Platforms with 3 or 4 clusters that use MCPM must select this
1402 option to allow the additional clusters to be managed.
1405 bool "big.LITTLE support (Experimental)"
1406 depends on CPU_V7 && SMP
1409 This option enables support selections for the big.LITTLE
1410 system architecture.
1413 bool "big.LITTLE switcher support"
1414 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1415 select ARM_CPU_SUSPEND
1418 The big.LITTLE "switcher" provides the core functionality to
1419 transparently handle transition between a cluster of A15's
1420 and a cluster of A7's in a big.LITTLE system.
1422 config BL_SWITCHER_DUMMY_IF
1423 tristate "Simple big.LITTLE switcher user interface"
1424 depends on BL_SWITCHER && DEBUG_KERNEL
1426 This is a simple and dummy char dev interface to control
1427 the big.LITTLE switcher core code. It is meant for
1428 debugging purposes only.
1431 prompt "Memory split"
1435 Select the desired split between kernel and user memory.
1437 If you are not absolutely sure what you are doing, leave this
1441 bool "3G/1G user/kernel split"
1443 bool "2G/2G user/kernel split"
1445 bool "1G/3G user/kernel split"
1450 default PHYS_OFFSET if !MMU
1451 default 0x40000000 if VMSPLIT_1G
1452 default 0x80000000 if VMSPLIT_2G
1456 int "Maximum number of CPUs (2-32)"
1462 bool "Support for hot-pluggable CPUs"
1465 Say Y here to experiment with turning CPUs off and on. CPUs
1466 can be controlled through /sys/devices/system/cpu.
1469 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1472 Say Y here if you want Linux to communicate with system firmware
1473 implementing the PSCI specification for CPU-centric power
1474 management operations described in ARM document number ARM DEN
1475 0022A ("Power State Coordination Interface System Software on
1478 # The GPIO number here must be sorted by descending number. In case of
1479 # a multiplatform kernel, we just want the highest value required by the
1480 # selected platforms.
1483 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1484 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1485 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1486 default 416 if ARCH_SUNXI
1487 default 392 if ARCH_U8500
1488 default 352 if ARCH_VT8500
1489 default 288 if ARCH_ROCKCHIP
1490 default 264 if MACH_H4700
1493 Maximum number of GPIOs in the system.
1495 If unsure, leave the default value.
1497 source kernel/Kconfig.preempt
1501 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1502 ARCH_S5PV210 || ARCH_EXYNOS4
1503 default 128 if SOC_AT91RM9200
1504 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1508 depends on HZ_FIXED = 0
1509 prompt "Timer frequency"
1533 default HZ_FIXED if HZ_FIXED != 0
1534 default 100 if HZ_100
1535 default 200 if HZ_200
1536 default 250 if HZ_250
1537 default 300 if HZ_300
1538 default 500 if HZ_500
1542 def_bool HIGH_RES_TIMERS
1544 config THUMB2_KERNEL
1545 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1546 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1547 default y if CPU_THUMBONLY
1549 select ARM_ASM_UNIFIED
1552 By enabling this option, the kernel will be compiled in
1553 Thumb-2 mode. A compiler/assembler that understand the unified
1554 ARM-Thumb syntax is needed.
1558 config THUMB2_AVOID_R_ARM_THM_JUMP11
1559 bool "Work around buggy Thumb-2 short branch relocations in gas"
1560 depends on THUMB2_KERNEL && MODULES
1563 Various binutils versions can resolve Thumb-2 branches to
1564 locally-defined, preemptible global symbols as short-range "b.n"
1565 branch instructions.
1567 This is a problem, because there's no guarantee the final
1568 destination of the symbol, or any candidate locations for a
1569 trampoline, are within range of the branch. For this reason, the
1570 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1571 relocation in modules at all, and it makes little sense to add
1574 The symptom is that the kernel fails with an "unsupported
1575 relocation" error when loading some modules.
1577 Until fixed tools are available, passing
1578 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1579 code which hits this problem, at the cost of a bit of extra runtime
1580 stack usage in some cases.
1582 The problem is described in more detail at:
1583 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1585 Only Thumb-2 kernels are affected.
1587 Unless you are sure your tools don't have this problem, say Y.
1589 config ARM_ASM_UNIFIED
1593 bool "Use the ARM EABI to compile the kernel"
1595 This option allows for the kernel to be compiled using the latest
1596 ARM ABI (aka EABI). This is only useful if you are using a user
1597 space environment that is also compiled with EABI.
1599 Since there are major incompatibilities between the legacy ABI and
1600 EABI, especially with regard to structure member alignment, this
1601 option also changes the kernel syscall calling convention to
1602 disambiguate both ABIs and allow for backward compatibility support
1603 (selected with CONFIG_OABI_COMPAT).
1605 To use this you need GCC version 4.0.0 or later.
1608 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1609 depends on AEABI && !THUMB2_KERNEL
1611 This option preserves the old syscall interface along with the
1612 new (ARM EABI) one. It also provides a compatibility layer to
1613 intercept syscalls that have structure arguments which layout
1614 in memory differs between the legacy ABI and the new ARM EABI
1615 (only for non "thumb" binaries). This option adds a tiny
1616 overhead to all syscalls and produces a slightly larger kernel.
1618 The seccomp filter system will not be available when this is
1619 selected, since there is no way yet to sensibly distinguish
1620 between calling conventions during filtering.
1622 If you know you'll be using only pure EABI user space then you
1623 can say N here. If this option is not selected and you attempt
1624 to execute a legacy ABI binary then the result will be
1625 UNPREDICTABLE (in fact it can be predicted that it won't work
1626 at all). If in doubt say N.
1628 config ARCH_HAS_HOLES_MEMORYMODEL
1631 config ARCH_SPARSEMEM_ENABLE
1634 config ARCH_SPARSEMEM_DEFAULT
1635 def_bool ARCH_SPARSEMEM_ENABLE
1637 config ARCH_SELECT_MEMORY_MODEL
1638 def_bool ARCH_SPARSEMEM_ENABLE
1640 config HAVE_ARCH_PFN_VALID
1641 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1643 config HAVE_GENERIC_RCU_GUP
1648 bool "High Memory Support"
1651 The address space of ARM processors is only 4 Gigabytes large
1652 and it has to accommodate user address space, kernel address
1653 space as well as some memory mapped IO. That means that, if you
1654 have a large amount of physical memory and/or IO, not all of the
1655 memory can be "permanently mapped" by the kernel. The physical
1656 memory that is not permanently mapped is called "high memory".
1658 Depending on the selected kernel/user memory split, minimum
1659 vmalloc space and actual amount of RAM, you may not need this
1660 option which should result in a slightly faster kernel.
1665 bool "Allocate 2nd-level pagetables from highmem"
1668 config HW_PERF_EVENTS
1669 bool "Enable hardware performance counter support for perf events"
1670 depends on PERF_EVENTS
1673 Enable hardware performance counter support for perf events. If
1674 disabled, perf events will use software events only.
1676 config SYS_SUPPORTS_HUGETLBFS
1680 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1684 config ARCH_WANT_GENERAL_HUGETLB
1689 config FORCE_MAX_ZONEORDER
1690 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1691 range 11 64 if ARCH_SHMOBILE_LEGACY
1692 default "12" if SOC_AM33XX
1693 default "9" if SA1111 || ARCH_EFM32
1696 The kernel memory allocator divides physically contiguous memory
1697 blocks into "zones", where each zone is a power of two number of
1698 pages. This option selects the largest power of two that the kernel
1699 keeps in the memory allocator. If you need to allocate very large
1700 blocks of physically contiguous memory, then you may need to
1701 increase this value.
1703 This config option is actually maximum order plus one. For example,
1704 a value of 11 means that the largest free memory block is 2^10 pages.
1706 config ALIGNMENT_TRAP
1708 depends on CPU_CP15_MMU
1709 default y if !ARCH_EBSA110
1710 select HAVE_PROC_CPU if PROC_FS
1712 ARM processors cannot fetch/store information which is not
1713 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1714 address divisible by 4. On 32-bit ARM processors, these non-aligned
1715 fetch/store instructions will be emulated in software if you say
1716 here, which has a severe performance impact. This is necessary for
1717 correct operation of some network protocols. With an IP-only
1718 configuration it is safe to say N, otherwise say Y.
1720 config UACCESS_WITH_MEMCPY
1721 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1723 default y if CPU_FEROCEON
1725 Implement faster copy_to_user and clear_user methods for CPU
1726 cores where a 8-word STM instruction give significantly higher
1727 memory write throughput than a sequence of individual 32bit stores.
1729 A possible side effect is a slight increase in scheduling latency
1730 between threads sharing the same address space if they invoke
1731 such copy operations with large buffers.
1733 However, if the CPU data cache is using a write-allocate mode,
1734 this option is unlikely to provide any performance gain.
1738 prompt "Enable seccomp to safely compute untrusted bytecode"
1740 This kernel feature is useful for number crunching applications
1741 that may need to compute untrusted bytecode during their
1742 execution. By using pipes or other transports made available to
1743 the process as file descriptors supporting the read/write
1744 syscalls, it's possible to isolate those applications in
1745 their own address space using seccomp. Once seccomp is
1746 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1747 and the task is only allowed to execute a few safe syscalls
1748 defined by each seccomp mode.
1761 bool "Xen guest support on ARM"
1762 depends on ARM && AEABI && OF
1763 depends on CPU_V7 && !CPU_V6
1764 depends on !GENERIC_ATOMIC64
1766 select ARCH_DMA_ADDR_T_64BIT
1770 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1777 bool "Flattened Device Tree support"
1780 select OF_EARLY_FLATTREE
1781 select OF_RESERVED_MEM
1783 Include support for flattened device tree machine descriptions.
1786 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1789 This is the traditional way of passing data to the kernel at boot
1790 time. If you are solely relying on the flattened device tree (or
1791 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1792 to remove ATAGS support from your kernel binary. If unsure,
1795 config DEPRECATED_PARAM_STRUCT
1796 bool "Provide old way to pass kernel parameters"
1799 This was deprecated in 2001 and announced to live on for 5 years.
1800 Some old boot loaders still use this way.
1802 # Compressed boot loader in ROM. Yes, we really want to ask about
1803 # TEXT and BSS so we preserve their values in the config files.
1804 config ZBOOT_ROM_TEXT
1805 hex "Compressed ROM boot loader base address"
1808 The physical address at which the ROM-able zImage is to be
1809 placed in the target. Platforms which normally make use of
1810 ROM-able zImage formats normally set this to a suitable
1811 value in their defconfig file.
1813 If ZBOOT_ROM is not enabled, this has no effect.
1815 config ZBOOT_ROM_BSS
1816 hex "Compressed ROM boot loader BSS address"
1819 The base address of an area of read/write memory in the target
1820 for the ROM-able zImage which must be available while the
1821 decompressor is running. It must be large enough to hold the
1822 entire decompressed kernel plus an additional 128 KiB.
1823 Platforms which normally make use of ROM-able zImage formats
1824 normally set this to a suitable value in their defconfig file.
1826 If ZBOOT_ROM is not enabled, this has no effect.
1829 bool "Compressed boot loader in ROM/flash"
1830 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1831 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1833 Say Y here if you intend to execute your compressed kernel image
1834 (zImage) directly from ROM or flash. If unsure, say N.
1836 config ARM_APPENDED_DTB
1837 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1840 With this option, the boot code will look for a device tree binary
1841 (DTB) appended to zImage
1842 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1844 This is meant as a backward compatibility convenience for those
1845 systems with a bootloader that can't be upgraded to accommodate
1846 the documented boot protocol using a device tree.
1848 Beware that there is very little in terms of protection against
1849 this option being confused by leftover garbage in memory that might
1850 look like a DTB header after a reboot if no actual DTB is appended
1851 to zImage. Do not leave this option active in a production kernel
1852 if you don't intend to always append a DTB. Proper passing of the
1853 location into r2 of a bootloader provided DTB is always preferable
1856 config ARM_ATAG_DTB_COMPAT
1857 bool "Supplement the appended DTB with traditional ATAG information"
1858 depends on ARM_APPENDED_DTB
1860 Some old bootloaders can't be updated to a DTB capable one, yet
1861 they provide ATAGs with memory configuration, the ramdisk address,
1862 the kernel cmdline string, etc. Such information is dynamically
1863 provided by the bootloader and can't always be stored in a static
1864 DTB. To allow a device tree enabled kernel to be used with such
1865 bootloaders, this option allows zImage to extract the information
1866 from the ATAG list and store it at run time into the appended DTB.
1869 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1870 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1872 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1873 bool "Use bootloader kernel arguments if available"
1875 Uses the command-line options passed by the boot loader instead of
1876 the device tree bootargs property. If the boot loader doesn't provide
1877 any, the device tree bootargs property will be used.
1879 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1880 bool "Extend with bootloader kernel arguments"
1882 The command-line arguments provided by the boot loader will be
1883 appended to the the device tree bootargs property.
1888 string "Default kernel command string"
1891 On some architectures (EBSA110 and CATS), there is currently no way
1892 for the boot loader to pass arguments to the kernel. For these
1893 architectures, you should supply some command-line options at build
1894 time by entering them here. As a minimum, you should specify the
1895 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1898 prompt "Kernel command line type" if CMDLINE != ""
1899 default CMDLINE_FROM_BOOTLOADER
1902 config CMDLINE_FROM_BOOTLOADER
1903 bool "Use bootloader kernel arguments if available"
1905 Uses the command-line options passed by the boot loader. If
1906 the boot loader doesn't provide any, the default kernel command
1907 string provided in CMDLINE will be used.
1909 config CMDLINE_EXTEND
1910 bool "Extend bootloader kernel arguments"
1912 The command-line arguments provided by the boot loader will be
1913 appended to the default kernel command string.
1915 config CMDLINE_FORCE
1916 bool "Always use the default kernel command string"
1918 Always use the default kernel command string, even if the boot
1919 loader passes other arguments to the kernel.
1920 This is useful if you cannot or don't want to change the
1921 command-line options your boot loader passes to the kernel.
1925 bool "Kernel Execute-In-Place from ROM"
1926 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1928 Execute-In-Place allows the kernel to run from non-volatile storage
1929 directly addressable by the CPU, such as NOR flash. This saves RAM
1930 space since the text section of the kernel is not loaded from flash
1931 to RAM. Read-write sections, such as the data section and stack,
1932 are still copied to RAM. The XIP kernel is not compressed since
1933 it has to run directly from flash, so it will take more space to
1934 store it. The flash address used to link the kernel object files,
1935 and for storing it, is configuration dependent. Therefore, if you
1936 say Y here, you must know the proper physical address where to
1937 store the kernel image depending on your own flash memory usage.
1939 Also note that the make target becomes "make xipImage" rather than
1940 "make zImage" or "make Image". The final kernel binary to put in
1941 ROM memory will be arch/arm/boot/xipImage.
1945 config XIP_PHYS_ADDR
1946 hex "XIP Kernel Physical Location"
1947 depends on XIP_KERNEL
1948 default "0x00080000"
1950 This is the physical address in your flash memory the kernel will
1951 be linked for and stored to. This address is dependent on your
1955 bool "Kexec system call (EXPERIMENTAL)"
1956 depends on (!SMP || PM_SLEEP_SMP)
1958 kexec is a system call that implements the ability to shutdown your
1959 current kernel, and to start another kernel. It is like a reboot
1960 but it is independent of the system firmware. And like a reboot
1961 you can start any kernel with it, not just Linux.
1963 It is an ongoing process to be certain the hardware in a machine
1964 is properly shutdown, so do not be surprised if this code does not
1965 initially work for you.
1968 bool "Export atags in procfs"
1969 depends on ATAGS && KEXEC
1972 Should the atags used to boot the kernel be exported in an "atags"
1973 file in procfs. Useful with kexec.
1976 bool "Build kdump crash kernel (EXPERIMENTAL)"
1978 Generate crash dump after being started by kexec. This should
1979 be normally only set in special crash dump kernels which are
1980 loaded in the main kernel with kexec-tools into a specially
1981 reserved region and then later executed after a crash by
1982 kdump/kexec. The crash dump kernel must be compiled to a
1983 memory address not used by the main kernel
1985 For more details see Documentation/kdump/kdump.txt
1987 config AUTO_ZRELADDR
1988 bool "Auto calculation of the decompressed kernel image address"
1990 ZRELADDR is the physical address where the decompressed kernel
1991 image will be placed. If AUTO_ZRELADDR is selected, the address
1992 will be determined at run-time by masking the current IP with
1993 0xf8000000. This assumes the zImage being placed in the first 128MB
1994 from start of memory.
1998 menu "CPU Power Management"
2000 source "drivers/cpufreq/Kconfig"
2002 source "drivers/cpuidle/Kconfig"
2006 menu "Floating point emulation"
2008 comment "At least one emulation must be selected"
2011 bool "NWFPE math emulation"
2012 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2014 Say Y to include the NWFPE floating point emulator in the kernel.
2015 This is necessary to run most binaries. Linux does not currently
2016 support floating point hardware so you need to say Y here even if
2017 your machine has an FPA or floating point co-processor podule.
2019 You may say N here if you are going to load the Acorn FPEmulator
2020 early in the bootup.
2023 bool "Support extended precision"
2024 depends on FPE_NWFPE
2026 Say Y to include 80-bit support in the kernel floating-point
2027 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2028 Note that gcc does not generate 80-bit operations by default,
2029 so in most cases this option only enlarges the size of the
2030 floating point emulator without any good reason.
2032 You almost surely want to say N here.
2035 bool "FastFPE math emulation (EXPERIMENTAL)"
2036 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2038 Say Y here to include the FAST floating point emulator in the kernel.
2039 This is an experimental much faster emulator which now also has full
2040 precision for the mantissa. It does not support any exceptions.
2041 It is very simple, and approximately 3-6 times faster than NWFPE.
2043 It should be sufficient for most programs. It may be not suitable
2044 for scientific calculations, but you have to check this for yourself.
2045 If you do not feel you need a faster FP emulation you should better
2049 bool "VFP-format floating point maths"
2050 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2052 Say Y to include VFP support code in the kernel. This is needed
2053 if your hardware includes a VFP unit.
2055 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2056 release notes and additional status information.
2058 Say N if your target does not have VFP hardware.
2066 bool "Advanced SIMD (NEON) Extension support"
2067 depends on VFPv3 && CPU_V7
2069 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2072 config KERNEL_MODE_NEON
2073 bool "Support for NEON in kernel mode"
2074 depends on NEON && AEABI
2076 Say Y to include support for NEON in kernel mode.
2080 menu "Userspace binary formats"
2082 source "fs/Kconfig.binfmt"
2086 menu "Power management options"
2088 source "kernel/power/Kconfig"
2090 config ARCH_SUSPEND_POSSIBLE
2091 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2092 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2095 config ARM_CPU_SUSPEND
2098 config ARCH_HIBERNATION_POSSIBLE
2101 default y if ARCH_SUSPEND_POSSIBLE
2105 source "net/Kconfig"
2107 source "drivers/Kconfig"
2109 source "drivers/firmware/Kconfig"
2113 source "arch/arm/Kconfig.debug"
2115 source "security/Kconfig"
2117 source "crypto/Kconfig"
2119 source "arch/arm/crypto/Kconfig"
2122 source "lib/Kconfig"
2124 source "arch/arm/kvm/Kconfig"