4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
256 select ARCH_HAS_CPUFREQ
258 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
266 select MULTI_IRQ_HANDLER
268 Support for ARM's Integrator platform.
271 bool "ARM Ltd. RealView family"
274 select HAVE_MACH_CLKDEV
276 select GENERIC_CLOCKEVENTS
277 select ARCH_WANT_OPTIONAL_GPIOLIB
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_CLCD
280 select ARM_TIMER_SP804
281 select GPIO_PL061 if GPIOLIB
282 select NEED_MACH_MEMORY_H
284 This enables support for ARM Ltd RealView boards.
286 config ARCH_VERSATILE
287 bool "ARM Ltd. Versatile family"
291 select HAVE_MACH_CLKDEV
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
297 select PLAT_VERSATILE_FPGA_IRQ
298 select ARM_TIMER_SP804
300 This enables support for ARM Ltd Versatile board.
303 bool "ARM Ltd. Versatile Express family"
304 select ARCH_WANT_OPTIONAL_GPIOLIB
306 select ARM_TIMER_SP804
308 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
311 select HAVE_PATA_PLATFORM
314 select PLAT_VERSATILE
315 select PLAT_VERSATILE_CLCD
317 This enables support for the ARM Ltd Versatile Express boards.
321 select ARCH_REQUIRE_GPIOLIB
325 select NEED_MACH_IO_H if PCCARD
327 This enables support for systems based on Atmel
328 AT91RM9200 and AT91SAM9* processors.
331 bool "Broadcom BCMRING"
335 select ARM_TIMER_SP804
337 select GENERIC_CLOCKEVENTS
338 select ARCH_WANT_OPTIONAL_GPIOLIB
340 Support for Broadcom's BCMRing platform.
343 bool "Calxeda Highbank-based"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
347 select ARM_TIMER_SP804
351 select GENERIC_CLOCKEVENTS
357 Support for the Calxeda Highbank SoC based boards.
360 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
362 select ARCH_USES_GETTIMEOFFSET
363 select NEED_MACH_MEMORY_H
365 Support for Cirrus Logic 711x/721x/731x based boards.
368 bool "Cavium Networks CNS3XXX family"
370 select GENERIC_CLOCKEVENTS
372 select MIGHT_HAVE_CACHE_L2X0
373 select MIGHT_HAVE_PCI
374 select PCI_DOMAINS if PCI
376 Support for Cavium Networks CNS3XXX platform.
379 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
384 Support for the Cortina Systems Gemini family SoCs
387 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
390 select GENERIC_CLOCKEVENTS
392 select GENERIC_IRQ_CHIP
393 select MIGHT_HAVE_CACHE_L2X0
399 Support for CSR SiRFSoC ARM Cortex A9 Platform
406 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
421 select ARCH_REQUIRE_GPIOLIB
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXC/iMX-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_IRQ_CHIP
447 select MULTI_IRQ_HANDLER
449 Support for Freescale MXC/iMX-based family of processors
452 bool "Freescale MXS-based"
453 select GENERIC_CLOCKEVENTS
454 select ARCH_REQUIRE_GPIOLIB
458 select HAVE_CLK_PREPARE
462 Support for Freescale MXS-based family of processors
465 bool "Hilscher NetX based"
469 select GENERIC_CLOCKEVENTS
471 This enables support for systems based on the Hilscher NetX Soc
474 bool "Hynix HMS720x-based"
477 select ARCH_USES_GETTIMEOFFSET
479 This enables support for systems based on the Hynix HMS720x
487 select ARCH_SUPPORTS_MSI
489 select NEED_MACH_IO_H
490 select NEED_MACH_MEMORY_H
491 select NEED_RET_TO_USER
493 Support for Intel's IOP13XX (XScale) family of processors.
499 select NEED_MACH_IO_H
500 select NEED_RET_TO_USER
503 select ARCH_REQUIRE_GPIOLIB
505 Support for Intel's 80219 and IOP32X (XScale) family of
512 select NEED_MACH_IO_H
513 select NEED_RET_TO_USER
516 select ARCH_REQUIRE_GPIOLIB
518 Support for Intel's IOP33X (XScale) family of processors.
523 select ARCH_HAS_DMA_SET_COHERENT_MASK
526 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
528 select MIGHT_HAVE_PCI
529 select NEED_MACH_IO_H
530 select DMABOUNCE if PCI
532 Support for Intel's IXP4XX (XScale) family of processors.
538 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
548 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
559 select ARCH_REQUIRE_GPIOLIB
562 select USB_ARCH_HAS_OHCI
564 select GENERIC_CLOCKEVENTS
567 Support for the NXP LPC32XX family of processors
570 bool "Marvell MV78xx0"
573 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_IO_H
578 Support for the following Marvell MV78xx0 series SoCs:
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
588 select NEED_MACH_IO_H
591 Support for the following Marvell Orion 5x series SoCs:
592 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
593 Orion-2 (5281), Orion-1-90 (6183).
596 bool "Marvell PXA168/910/MMP2"
598 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
605 select GENERIC_ALLOCATOR
607 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
610 bool "Micrel/Kendin KS8695"
612 select ARCH_REQUIRE_GPIOLIB
613 select ARCH_USES_GETTIMEOFFSET
614 select NEED_MACH_MEMORY_H
616 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
617 System-on-Chip devices.
620 bool "Nuvoton W90X900 CPU"
622 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
627 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
628 At present, the w90x900 has been renamed nuc900, regarding
629 the ARM series product line, you can login the following
630 link address to know more.
632 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
633 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
639 select GENERIC_CLOCKEVENTS
643 select MIGHT_HAVE_CACHE_L2X0
644 select ARCH_HAS_CPUFREQ
646 This enables support for NVIDIA Tegra based systems (Tegra APX,
647 Tegra 6xx and Tegra 2 series).
649 config ARCH_PICOXCELL
650 bool "Picochip picoXcell"
651 select ARCH_REQUIRE_GPIOLIB
652 select ARM_PATCH_PHYS_VIRT
656 select GENERIC_CLOCKEVENTS
663 This enables support for systems based on the Picochip picoXcell
664 family of Femtocell devices. The picoxcell support requires device tree
668 bool "Philips Nexperia PNX4008 Mobile"
671 select ARCH_USES_GETTIMEOFFSET
673 This enables support for Philips PNX4008 mobile platform.
676 bool "PXA2xx/PXA3xx-based"
679 select ARCH_HAS_CPUFREQ
682 select ARCH_REQUIRE_GPIOLIB
683 select GENERIC_CLOCKEVENTS
688 select MULTI_IRQ_HANDLER
689 select ARM_CPU_SUSPEND if PM
692 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
697 select GENERIC_CLOCKEVENTS
698 select ARCH_REQUIRE_GPIOLIB
701 Support for Qualcomm MSM/QSD based systems. This runs on the
702 apps processor of the MSM/QSD and depends on a shared memory
703 interface to the modem processor which runs the baseband
704 stack and controls some vital subsystems
705 (clock and power control, etc).
708 bool "Renesas SH-Mobile / R-Mobile"
711 select HAVE_MACH_CLKDEV
713 select GENERIC_CLOCKEVENTS
714 select MIGHT_HAVE_CACHE_L2X0
717 select MULTI_IRQ_HANDLER
718 select PM_GENERIC_DOMAINS if PM
719 select NEED_MACH_MEMORY_H
721 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
727 select ARCH_MAY_HAVE_PC_FDC
728 select HAVE_PATA_PLATFORM
731 select ARCH_SPARSEMEM_ENABLE
732 select ARCH_USES_GETTIMEOFFSET
734 select NEED_MACH_IO_H
735 select NEED_MACH_MEMORY_H
737 On the Acorn Risc-PC, Linux can support the internal IDE disk and
738 CD-ROM interface, serial and parallel port, and the floppy drive.
745 select ARCH_SPARSEMEM_ENABLE
747 select ARCH_HAS_CPUFREQ
749 select GENERIC_CLOCKEVENTS
751 select ARCH_REQUIRE_GPIOLIB
753 select NEED_MACH_MEMORY_H
756 Support for StrongARM 11x0 based boards.
759 bool "Samsung S3C24XX SoCs"
761 select ARCH_HAS_CPUFREQ
764 select ARCH_USES_GETTIMEOFFSET
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C_RTC if RTC_CLASS
767 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select NEED_MACH_IO_H
770 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
771 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
772 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
773 Samsung SMDK2410 development board (and derivatives).
776 bool "Samsung S3C64XX"
784 select ARCH_USES_GETTIMEOFFSET
785 select ARCH_HAS_CPUFREQ
786 select ARCH_REQUIRE_GPIOLIB
787 select SAMSUNG_CLKSRC
788 select SAMSUNG_IRQ_VIC_TIMER
789 select S3C_GPIO_TRACK
791 select USB_ARCH_HAS_OHCI
792 select SAMSUNG_GPIOLIB_4BIT
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 Samsung S3C64XX series based systems
799 bool "Samsung S5P6440 S5P6450"
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select GENERIC_CLOCKEVENTS
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C_RTC if RTC_CLASS
810 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
814 bool "Samsung S5PC100"
819 select ARCH_USES_GETTIMEOFFSET
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C_RTC if RTC_CLASS
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 Samsung S5PC100 series based systems
827 bool "Samsung S5PV210/S5PC110"
829 select ARCH_SPARSEMEM_ENABLE
830 select ARCH_HAS_HOLES_MEMORYMODEL
835 select ARCH_HAS_CPUFREQ
836 select GENERIC_CLOCKEVENTS
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C_RTC if RTC_CLASS
839 select HAVE_S3C2410_WATCHDOG if WATCHDOG
840 select NEED_MACH_MEMORY_H
842 Samsung S5PV210/S5PC110 series based systems
845 bool "SAMSUNG EXYNOS"
847 select ARCH_SPARSEMEM_ENABLE
848 select ARCH_HAS_HOLES_MEMORYMODEL
852 select ARCH_HAS_CPUFREQ
853 select GENERIC_CLOCKEVENTS
854 select HAVE_S3C_RTC if RTC_CLASS
855 select HAVE_S3C2410_I2C if I2C
856 select HAVE_S3C2410_WATCHDOG if WATCHDOG
857 select NEED_MACH_MEMORY_H
859 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
868 select ARCH_USES_GETTIMEOFFSET
869 select NEED_MACH_MEMORY_H
871 Support for the StrongARM based Digital DNARD machine, also known
872 as "Shark" (<http://www.shark-linux.de/shark.html>).
875 bool "ST-Ericsson U300 Series"
881 select ARM_PATCH_PHYS_VIRT
883 select GENERIC_CLOCKEVENTS
885 select HAVE_MACH_CLKDEV
887 select ARCH_REQUIRE_GPIOLIB
889 Support for ST-Ericsson U300 series mobile platforms.
892 bool "ST-Ericsson U8500 Series"
896 select GENERIC_CLOCKEVENTS
898 select ARCH_REQUIRE_GPIOLIB
899 select ARCH_HAS_CPUFREQ
901 select MIGHT_HAVE_CACHE_L2X0
903 Support for ST-Ericsson's Ux500 architecture
906 bool "STMicroelectronics Nomadik"
911 select GENERIC_CLOCKEVENTS
913 select MIGHT_HAVE_CACHE_L2X0
914 select ARCH_REQUIRE_GPIOLIB
916 Support for the Nomadik platform by ST-Ericsson
920 select GENERIC_CLOCKEVENTS
921 select ARCH_REQUIRE_GPIOLIB
925 select GENERIC_ALLOCATOR
926 select GENERIC_IRQ_CHIP
927 select ARCH_HAS_HOLES_MEMORYMODEL
929 Support for TI's DaVinci platform.
934 select ARCH_REQUIRE_GPIOLIB
935 select ARCH_HAS_CPUFREQ
937 select GENERIC_CLOCKEVENTS
938 select ARCH_HAS_HOLES_MEMORYMODEL
940 Support for TI's OMAP platform (OMAP1/2/3/4).
945 select ARCH_REQUIRE_GPIOLIB
949 select GENERIC_CLOCKEVENTS
952 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
955 bool "VIA/WonderMedia 85xx"
958 select ARCH_HAS_CPUFREQ
959 select GENERIC_CLOCKEVENTS
960 select ARCH_REQUIRE_GPIOLIB
963 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
966 bool "Xilinx Zynq ARM Cortex A9 Platform"
968 select GENERIC_CLOCKEVENTS
973 select MIGHT_HAVE_CACHE_L2X0
976 Support for Xilinx Zynq ARM Cortex A9 Platform
980 # This is sorted alphabetically by mach-* pathname. However, plat-*
981 # Kconfigs may be included either alphabetically (according to the
982 # plat- suffix) or along side the corresponding mach-* source.
984 source "arch/arm/mach-at91/Kconfig"
986 source "arch/arm/mach-bcmring/Kconfig"
988 source "arch/arm/mach-clps711x/Kconfig"
990 source "arch/arm/mach-cns3xxx/Kconfig"
992 source "arch/arm/mach-davinci/Kconfig"
994 source "arch/arm/mach-dove/Kconfig"
996 source "arch/arm/mach-ep93xx/Kconfig"
998 source "arch/arm/mach-footbridge/Kconfig"
1000 source "arch/arm/mach-gemini/Kconfig"
1002 source "arch/arm/mach-h720x/Kconfig"
1004 source "arch/arm/mach-integrator/Kconfig"
1006 source "arch/arm/mach-iop32x/Kconfig"
1008 source "arch/arm/mach-iop33x/Kconfig"
1010 source "arch/arm/mach-iop13xx/Kconfig"
1012 source "arch/arm/mach-ixp4xx/Kconfig"
1014 source "arch/arm/mach-kirkwood/Kconfig"
1016 source "arch/arm/mach-ks8695/Kconfig"
1018 source "arch/arm/mach-lpc32xx/Kconfig"
1020 source "arch/arm/mach-msm/Kconfig"
1022 source "arch/arm/mach-mv78xx0/Kconfig"
1024 source "arch/arm/plat-mxc/Kconfig"
1026 source "arch/arm/mach-mxs/Kconfig"
1028 source "arch/arm/mach-netx/Kconfig"
1030 source "arch/arm/mach-nomadik/Kconfig"
1031 source "arch/arm/plat-nomadik/Kconfig"
1033 source "arch/arm/plat-omap/Kconfig"
1035 source "arch/arm/mach-omap1/Kconfig"
1037 source "arch/arm/mach-omap2/Kconfig"
1039 source "arch/arm/mach-orion5x/Kconfig"
1041 source "arch/arm/mach-pxa/Kconfig"
1042 source "arch/arm/plat-pxa/Kconfig"
1044 source "arch/arm/mach-mmp/Kconfig"
1046 source "arch/arm/mach-realview/Kconfig"
1048 source "arch/arm/mach-sa1100/Kconfig"
1050 source "arch/arm/plat-samsung/Kconfig"
1051 source "arch/arm/plat-s3c24xx/Kconfig"
1053 source "arch/arm/plat-spear/Kconfig"
1055 source "arch/arm/mach-s3c24xx/Kconfig"
1057 source "arch/arm/mach-s3c2412/Kconfig"
1058 source "arch/arm/mach-s3c2440/Kconfig"
1062 source "arch/arm/mach-s3c64xx/Kconfig"
1065 source "arch/arm/mach-s5p64x0/Kconfig"
1067 source "arch/arm/mach-s5pc100/Kconfig"
1069 source "arch/arm/mach-s5pv210/Kconfig"
1071 source "arch/arm/mach-exynos/Kconfig"
1073 source "arch/arm/mach-shmobile/Kconfig"
1075 source "arch/arm/mach-tegra/Kconfig"
1077 source "arch/arm/mach-u300/Kconfig"
1079 source "arch/arm/mach-ux500/Kconfig"
1081 source "arch/arm/mach-versatile/Kconfig"
1083 source "arch/arm/mach-vexpress/Kconfig"
1084 source "arch/arm/plat-versatile/Kconfig"
1086 source "arch/arm/mach-vt8500/Kconfig"
1088 source "arch/arm/mach-w90x900/Kconfig"
1090 # Definitions to make life easier
1096 select GENERIC_CLOCKEVENTS
1101 select GENERIC_IRQ_CHIP
1107 config PLAT_VERSATILE
1110 config ARM_TIMER_SP804
1113 select HAVE_SCHED_CLOCK
1115 source arch/arm/mm/Kconfig
1119 default 16 if ARCH_EP93XX
1123 bool "Enable iWMMXt support"
1124 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1125 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1127 Enable support for iWMMXt context switching at run time if
1128 running on a CPU that supports it.
1132 depends on CPU_XSCALE
1136 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1137 (!ARCH_OMAP3 || OMAP3_EMU)
1141 config MULTI_IRQ_HANDLER
1144 Allow each machine to specify it's own IRQ handler at run time.
1147 source "arch/arm/Kconfig-nommu"
1150 config ARM_ERRATA_326103
1151 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1154 Executing a SWP instruction to read-only memory does not set bit 11
1155 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1156 treat the access as a read, preventing a COW from occurring and
1157 causing the faulting task to livelock.
1159 config ARM_ERRATA_411920
1160 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1161 depends on CPU_V6 || CPU_V6K
1163 Invalidation of the Instruction Cache operation can
1164 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1165 It does not affect the MPCore. This option enables the ARM Ltd.
1166 recommended workaround.
1168 config ARM_ERRATA_430973
1169 bool "ARM errata: Stale prediction on replaced interworking branch"
1172 This option enables the workaround for the 430973 Cortex-A8
1173 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1174 interworking branch is replaced with another code sequence at the
1175 same virtual address, whether due to self-modifying code or virtual
1176 to physical address re-mapping, Cortex-A8 does not recover from the
1177 stale interworking branch prediction. This results in Cortex-A8
1178 executing the new code sequence in the incorrect ARM or Thumb state.
1179 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1180 and also flushes the branch target cache at every context switch.
1181 Note that setting specific bits in the ACTLR register may not be
1182 available in non-secure mode.
1184 config ARM_ERRATA_458693
1185 bool "ARM errata: Processor deadlock when a false hazard is created"
1188 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1189 erratum. For very specific sequences of memory operations, it is
1190 possible for a hazard condition intended for a cache line to instead
1191 be incorrectly associated with a different cache line. This false
1192 hazard might then cause a processor deadlock. The workaround enables
1193 the L1 caching of the NEON accesses and disables the PLD instruction
1194 in the ACTLR register. Note that setting specific bits in the ACTLR
1195 register may not be available in non-secure mode.
1197 config ARM_ERRATA_460075
1198 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1201 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1202 erratum. Any asynchronous access to the L2 cache may encounter a
1203 situation in which recent store transactions to the L2 cache are lost
1204 and overwritten with stale memory contents from external memory. The
1205 workaround disables the write-allocate mode for the L2 cache via the
1206 ACTLR register. Note that setting specific bits in the ACTLR register
1207 may not be available in non-secure mode.
1209 config ARM_ERRATA_742230
1210 bool "ARM errata: DMB operation may be faulty"
1211 depends on CPU_V7 && SMP
1213 This option enables the workaround for the 742230 Cortex-A9
1214 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1215 between two write operations may not ensure the correct visibility
1216 ordering of the two writes. This workaround sets a specific bit in
1217 the diagnostic register of the Cortex-A9 which causes the DMB
1218 instruction to behave as a DSB, ensuring the correct behaviour of
1221 config ARM_ERRATA_742231
1222 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1223 depends on CPU_V7 && SMP
1225 This option enables the workaround for the 742231 Cortex-A9
1226 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1227 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1228 accessing some data located in the same cache line, may get corrupted
1229 data due to bad handling of the address hazard when the line gets
1230 replaced from one of the CPUs at the same time as another CPU is
1231 accessing it. This workaround sets specific bits in the diagnostic
1232 register of the Cortex-A9 which reduces the linefill issuing
1233 capabilities of the processor.
1235 config PL310_ERRATA_588369
1236 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1237 depends on CACHE_L2X0
1239 The PL310 L2 cache controller implements three types of Clean &
1240 Invalidate maintenance operations: by Physical Address
1241 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1242 They are architecturally defined to behave as the execution of a
1243 clean operation followed immediately by an invalidate operation,
1244 both performing to the same memory location. This functionality
1245 is not correctly implemented in PL310 as clean lines are not
1246 invalidated as a result of these operations.
1248 config ARM_ERRATA_720789
1249 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1252 This option enables the workaround for the 720789 Cortex-A9 (prior to
1253 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1254 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1255 As a consequence of this erratum, some TLB entries which should be
1256 invalidated are not, resulting in an incoherency in the system page
1257 tables. The workaround changes the TLB flushing routines to invalidate
1258 entries regardless of the ASID.
1260 config PL310_ERRATA_727915
1261 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1262 depends on CACHE_L2X0
1264 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1265 operation (offset 0x7FC). This operation runs in background so that
1266 PL310 can handle normal accesses while it is in progress. Under very
1267 rare circumstances, due to this erratum, write data can be lost when
1268 PL310 treats a cacheable write transaction during a Clean &
1269 Invalidate by Way operation.
1271 config ARM_ERRATA_743622
1272 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1275 This option enables the workaround for the 743622 Cortex-A9
1276 (r2p*) erratum. Under very rare conditions, a faulty
1277 optimisation in the Cortex-A9 Store Buffer may lead to data
1278 corruption. This workaround sets a specific bit in the diagnostic
1279 register of the Cortex-A9 which disables the Store Buffer
1280 optimisation, preventing the defect from occurring. This has no
1281 visible impact on the overall performance or power consumption of the
1284 config ARM_ERRATA_751472
1285 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1288 This option enables the workaround for the 751472 Cortex-A9 (prior
1289 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1290 completion of a following broadcasted operation if the second
1291 operation is received by a CPU before the ICIALLUIS has completed,
1292 potentially leading to corrupted entries in the cache or TLB.
1294 config PL310_ERRATA_753970
1295 bool "PL310 errata: cache sync operation may be faulty"
1296 depends on CACHE_PL310
1298 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1300 Under some condition the effect of cache sync operation on
1301 the store buffer still remains when the operation completes.
1302 This means that the store buffer is always asked to drain and
1303 this prevents it from merging any further writes. The workaround
1304 is to replace the normal offset of cache sync operation (0x730)
1305 by another offset targeting an unmapped PL310 register 0x740.
1306 This has the same effect as the cache sync operation: store buffer
1307 drain and waiting for all buffers empty.
1309 config ARM_ERRATA_754322
1310 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1313 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1314 r3p*) erratum. A speculative memory access may cause a page table walk
1315 which starts prior to an ASID switch but completes afterwards. This
1316 can populate the micro-TLB with a stale entry which may be hit with
1317 the new ASID. This workaround places two dsb instructions in the mm
1318 switching code so that no page table walks can cross the ASID switch.
1320 config ARM_ERRATA_754327
1321 bool "ARM errata: no automatic Store Buffer drain"
1322 depends on CPU_V7 && SMP
1324 This option enables the workaround for the 754327 Cortex-A9 (prior to
1325 r2p0) erratum. The Store Buffer does not have any automatic draining
1326 mechanism and therefore a livelock may occur if an external agent
1327 continuously polls a memory location waiting to observe an update.
1328 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1329 written polling loops from denying visibility of updates to memory.
1331 config ARM_ERRATA_364296
1332 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1333 depends on CPU_V6 && !SMP
1335 This options enables the workaround for the 364296 ARM1136
1336 r0p2 erratum (possible cache data corruption with
1337 hit-under-miss enabled). It sets the undocumented bit 31 in
1338 the auxiliary control register and the FI bit in the control
1339 register, thus disabling hit-under-miss without putting the
1340 processor into full low interrupt latency mode. ARM11MPCore
1343 config ARM_ERRATA_764369
1344 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1345 depends on CPU_V7 && SMP
1347 This option enables the workaround for erratum 764369
1348 affecting Cortex-A9 MPCore with two or more processors (all
1349 current revisions). Under certain timing circumstances, a data
1350 cache line maintenance operation by MVA targeting an Inner
1351 Shareable memory region may fail to proceed up to either the
1352 Point of Coherency or to the Point of Unification of the
1353 system. This workaround adds a DSB instruction before the
1354 relevant cache maintenance functions and sets a specific bit
1355 in the diagnostic control register of the SCU.
1357 config PL310_ERRATA_769419
1358 bool "PL310 errata: no automatic Store Buffer drain"
1359 depends on CACHE_L2X0
1361 On revisions of the PL310 prior to r3p2, the Store Buffer does
1362 not automatically drain. This can cause normal, non-cacheable
1363 writes to be retained when the memory system is idle, leading
1364 to suboptimal I/O performance for drivers using coherent DMA.
1365 This option adds a write barrier to the cpu_idle loop so that,
1366 on systems with an outer cache, the store buffer is drained
1371 source "arch/arm/common/Kconfig"
1381 Find out whether you have ISA slots on your motherboard. ISA is the
1382 name of a bus system, i.e. the way the CPU talks to the other stuff
1383 inside your box. Other bus systems are PCI, EISA, MicroChannel
1384 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1385 newer boards don't support it. If you have ISA, say Y, otherwise N.
1387 # Select ISA DMA controller support
1392 # Select ISA DMA interface
1397 bool "PCI support" if MIGHT_HAVE_PCI
1399 Find out whether you have a PCI motherboard. PCI is the name of a
1400 bus system, i.e. the way the CPU talks to the other stuff inside
1401 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1402 VESA. If you have PCI, say Y, otherwise N.
1408 config PCI_NANOENGINE
1409 bool "BSE nanoEngine PCI support"
1410 depends on SA1100_NANOENGINE
1412 Enable PCI on the BSE nanoEngine board.
1417 # Select the host bridge type
1418 config PCI_HOST_VIA82C505
1420 depends on PCI && ARCH_SHARK
1423 config PCI_HOST_ITE8152
1425 depends on PCI && MACH_ARMCORE
1429 source "drivers/pci/Kconfig"
1431 source "drivers/pcmcia/Kconfig"
1435 menu "Kernel Features"
1440 This option should be selected by machines which have an SMP-
1443 The only effect of this option is to make the SMP-related
1444 options available to the user for configuration.
1447 bool "Symmetric Multi-Processing"
1448 depends on CPU_V6K || CPU_V7
1449 depends on GENERIC_CLOCKEVENTS
1452 select USE_GENERIC_SMP_HELPERS
1453 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1455 This enables support for systems with more than one CPU. If you have
1456 a system with only one CPU, like most personal computers, say N. If
1457 you have a system with more than one CPU, say Y.
1459 If you say N here, the kernel will run on single and multiprocessor
1460 machines, but will use only one CPU of a multiprocessor machine. If
1461 you say Y here, the kernel will run on many, but not all, single
1462 processor machines. On a single processor machine, the kernel will
1463 run faster if you say N here.
1465 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1466 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1467 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1469 If you don't know what to do here, say N.
1472 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1473 depends on EXPERIMENTAL
1474 depends on SMP && !XIP_KERNEL
1477 SMP kernels contain instructions which fail on non-SMP processors.
1478 Enabling this option allows the kernel to modify itself to make
1479 these instructions safe. Disabling it allows about 1K of space
1482 If you don't know what to do here, say Y.
1484 config ARM_CPU_TOPOLOGY
1485 bool "Support cpu topology definition"
1486 depends on SMP && CPU_V7
1489 Support ARM cpu topology definition. The MPIDR register defines
1490 affinity between processors which is then used to describe the cpu
1491 topology of an ARM System.
1494 bool "Multi-core scheduler support"
1495 depends on ARM_CPU_TOPOLOGY
1497 Multi-core scheduler support improves the CPU scheduler's decision
1498 making when dealing with multi-core CPU chips at a cost of slightly
1499 increased overhead in some places. If unsure say N here.
1502 bool "SMT scheduler support"
1503 depends on ARM_CPU_TOPOLOGY
1505 Improves the CPU scheduler's decision making when dealing with
1506 MultiThreading at a cost of slightly increased overhead in some
1507 places. If unsure say N here.
1512 This option enables support for the ARM system coherency unit
1514 config ARM_ARCH_TIMER
1515 bool "Architected timer support"
1518 This option enables support for the ARM architected timer
1524 This options enables support for the ARM timer and watchdog unit
1527 prompt "Memory split"
1530 Select the desired split between kernel and user memory.
1532 If you are not absolutely sure what you are doing, leave this
1536 bool "3G/1G user/kernel split"
1538 bool "2G/2G user/kernel split"
1540 bool "1G/3G user/kernel split"
1545 default 0x40000000 if VMSPLIT_1G
1546 default 0x80000000 if VMSPLIT_2G
1550 int "Maximum number of CPUs (2-32)"
1556 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1557 depends on SMP && HOTPLUG && EXPERIMENTAL
1559 Say Y here to experiment with turning CPUs off and on. CPUs
1560 can be controlled through /sys/devices/system/cpu.
1563 bool "Use local timer interrupts"
1566 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1568 Enable support for local timers on SMP platforms, rather then the
1569 legacy IPI broadcast method. Local timers allows the system
1570 accounting to be spread across the timer interval, preventing a
1571 "thundering herd" at every timer tick.
1575 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1576 default 355 if ARCH_U8500
1577 default 264 if MACH_H4700
1580 Maximum number of GPIOs in the system.
1582 If unsure, leave the default value.
1584 source kernel/Kconfig.preempt
1588 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1589 ARCH_S5PV210 || ARCH_EXYNOS4
1590 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1591 default AT91_TIMER_HZ if ARCH_AT91
1592 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1595 config THUMB2_KERNEL
1596 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1597 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1599 select ARM_ASM_UNIFIED
1602 By enabling this option, the kernel will be compiled in
1603 Thumb-2 mode. A compiler/assembler that understand the unified
1604 ARM-Thumb syntax is needed.
1608 config THUMB2_AVOID_R_ARM_THM_JUMP11
1609 bool "Work around buggy Thumb-2 short branch relocations in gas"
1610 depends on THUMB2_KERNEL && MODULES
1613 Various binutils versions can resolve Thumb-2 branches to
1614 locally-defined, preemptible global symbols as short-range "b.n"
1615 branch instructions.
1617 This is a problem, because there's no guarantee the final
1618 destination of the symbol, or any candidate locations for a
1619 trampoline, are within range of the branch. For this reason, the
1620 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1621 relocation in modules at all, and it makes little sense to add
1624 The symptom is that the kernel fails with an "unsupported
1625 relocation" error when loading some modules.
1627 Until fixed tools are available, passing
1628 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1629 code which hits this problem, at the cost of a bit of extra runtime
1630 stack usage in some cases.
1632 The problem is described in more detail at:
1633 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1635 Only Thumb-2 kernels are affected.
1637 Unless you are sure your tools don't have this problem, say Y.
1639 config ARM_ASM_UNIFIED
1643 bool "Use the ARM EABI to compile the kernel"
1645 This option allows for the kernel to be compiled using the latest
1646 ARM ABI (aka EABI). This is only useful if you are using a user
1647 space environment that is also compiled with EABI.
1649 Since there are major incompatibilities between the legacy ABI and
1650 EABI, especially with regard to structure member alignment, this
1651 option also changes the kernel syscall calling convention to
1652 disambiguate both ABIs and allow for backward compatibility support
1653 (selected with CONFIG_OABI_COMPAT).
1655 To use this you need GCC version 4.0.0 or later.
1658 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1659 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1662 This option preserves the old syscall interface along with the
1663 new (ARM EABI) one. It also provides a compatibility layer to
1664 intercept syscalls that have structure arguments which layout
1665 in memory differs between the legacy ABI and the new ARM EABI
1666 (only for non "thumb" binaries). This option adds a tiny
1667 overhead to all syscalls and produces a slightly larger kernel.
1668 If you know you'll be using only pure EABI user space then you
1669 can say N here. If this option is not selected and you attempt
1670 to execute a legacy ABI binary then the result will be
1671 UNPREDICTABLE (in fact it can be predicted that it won't work
1672 at all). If in doubt say Y.
1674 config ARCH_HAS_HOLES_MEMORYMODEL
1677 config ARCH_SPARSEMEM_ENABLE
1680 config ARCH_SPARSEMEM_DEFAULT
1681 def_bool ARCH_SPARSEMEM_ENABLE
1683 config ARCH_SELECT_MEMORY_MODEL
1684 def_bool ARCH_SPARSEMEM_ENABLE
1686 config HAVE_ARCH_PFN_VALID
1687 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1690 bool "High Memory Support"
1693 The address space of ARM processors is only 4 Gigabytes large
1694 and it has to accommodate user address space, kernel address
1695 space as well as some memory mapped IO. That means that, if you
1696 have a large amount of physical memory and/or IO, not all of the
1697 memory can be "permanently mapped" by the kernel. The physical
1698 memory that is not permanently mapped is called "high memory".
1700 Depending on the selected kernel/user memory split, minimum
1701 vmalloc space and actual amount of RAM, you may not need this
1702 option which should result in a slightly faster kernel.
1707 bool "Allocate 2nd-level pagetables from highmem"
1710 config HW_PERF_EVENTS
1711 bool "Enable hardware performance counter support for perf events"
1712 depends on PERF_EVENTS && CPU_HAS_PMU
1715 Enable hardware performance counter support for perf events. If
1716 disabled, perf events will use software events only.
1720 config FORCE_MAX_ZONEORDER
1721 int "Maximum zone order" if ARCH_SHMOBILE
1722 range 11 64 if ARCH_SHMOBILE
1723 default "9" if SA1111
1726 The kernel memory allocator divides physically contiguous memory
1727 blocks into "zones", where each zone is a power of two number of
1728 pages. This option selects the largest power of two that the kernel
1729 keeps in the memory allocator. If you need to allocate very large
1730 blocks of physically contiguous memory, then you may need to
1731 increase this value.
1733 This config option is actually maximum order plus one. For example,
1734 a value of 11 means that the largest free memory block is 2^10 pages.
1737 bool "Timer and CPU usage LEDs"
1738 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1739 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1740 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1741 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1742 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1743 ARCH_AT91 || ARCH_DAVINCI || \
1744 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1746 If you say Y here, the LEDs on your machine will be used
1747 to provide useful information about your current system status.
1749 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1750 be able to select which LEDs are active using the options below. If
1751 you are compiling a kernel for the EBSA-110 or the LART however, the
1752 red LED will simply flash regularly to indicate that the system is
1753 still functional. It is safe to say Y here if you have a CATS
1754 system, but the driver will do nothing.
1757 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1758 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1759 || MACH_OMAP_PERSEUS2
1761 depends on !GENERIC_CLOCKEVENTS
1762 default y if ARCH_EBSA110
1764 If you say Y here, one of the system LEDs (the green one on the
1765 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1766 will flash regularly to indicate that the system is still
1767 operational. This is mainly useful to kernel hackers who are
1768 debugging unstable kernels.
1770 The LART uses the same LED for both Timer LED and CPU usage LED
1771 functions. You may choose to use both, but the Timer LED function
1772 will overrule the CPU usage LED.
1775 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1777 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1778 || MACH_OMAP_PERSEUS2
1781 If you say Y here, the red LED will be used to give a good real
1782 time indication of CPU usage, by lighting whenever the idle task
1783 is not currently executing.
1785 The LART uses the same LED for both Timer LED and CPU usage LED
1786 functions. You may choose to use both, but the Timer LED function
1787 will overrule the CPU usage LED.
1789 config ALIGNMENT_TRAP
1791 depends on CPU_CP15_MMU
1792 default y if !ARCH_EBSA110
1793 select HAVE_PROC_CPU if PROC_FS
1795 ARM processors cannot fetch/store information which is not
1796 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1797 address divisible by 4. On 32-bit ARM processors, these non-aligned
1798 fetch/store instructions will be emulated in software if you say
1799 here, which has a severe performance impact. This is necessary for
1800 correct operation of some network protocols. With an IP-only
1801 configuration it is safe to say N, otherwise say Y.
1803 config UACCESS_WITH_MEMCPY
1804 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1805 depends on MMU && EXPERIMENTAL
1806 default y if CPU_FEROCEON
1808 Implement faster copy_to_user and clear_user methods for CPU
1809 cores where a 8-word STM instruction give significantly higher
1810 memory write throughput than a sequence of individual 32bit stores.
1812 A possible side effect is a slight increase in scheduling latency
1813 between threads sharing the same address space if they invoke
1814 such copy operations with large buffers.
1816 However, if the CPU data cache is using a write-allocate mode,
1817 this option is unlikely to provide any performance gain.
1821 prompt "Enable seccomp to safely compute untrusted bytecode"
1823 This kernel feature is useful for number crunching applications
1824 that may need to compute untrusted bytecode during their
1825 execution. By using pipes or other transports made available to
1826 the process as file descriptors supporting the read/write
1827 syscalls, it's possible to isolate those applications in
1828 their own address space using seccomp. Once seccomp is
1829 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1830 and the task is only allowed to execute a few safe syscalls
1831 defined by each seccomp mode.
1833 config CC_STACKPROTECTOR
1834 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1835 depends on EXPERIMENTAL
1837 This option turns on the -fstack-protector GCC feature. This
1838 feature puts, at the beginning of functions, a canary value on
1839 the stack just before the return address, and validates
1840 the value just before actually returning. Stack based buffer
1841 overflows (that need to overwrite this return address) now also
1842 overwrite the canary, which gets detected and the attack is then
1843 neutralized via a kernel panic.
1844 This feature requires gcc version 4.2 or above.
1846 config DEPRECATED_PARAM_STRUCT
1847 bool "Provide old way to pass kernel parameters"
1849 This was deprecated in 2001 and announced to live on for 5 years.
1850 Some old boot loaders still use this way.
1857 bool "Flattened Device Tree support"
1859 select OF_EARLY_FLATTREE
1862 Include support for flattened device tree machine descriptions.
1864 # Compressed boot loader in ROM. Yes, we really want to ask about
1865 # TEXT and BSS so we preserve their values in the config files.
1866 config ZBOOT_ROM_TEXT
1867 hex "Compressed ROM boot loader base address"
1870 The physical address at which the ROM-able zImage is to be
1871 placed in the target. Platforms which normally make use of
1872 ROM-able zImage formats normally set this to a suitable
1873 value in their defconfig file.
1875 If ZBOOT_ROM is not enabled, this has no effect.
1877 config ZBOOT_ROM_BSS
1878 hex "Compressed ROM boot loader BSS address"
1881 The base address of an area of read/write memory in the target
1882 for the ROM-able zImage which must be available while the
1883 decompressor is running. It must be large enough to hold the
1884 entire decompressed kernel plus an additional 128 KiB.
1885 Platforms which normally make use of ROM-able zImage formats
1886 normally set this to a suitable value in their defconfig file.
1888 If ZBOOT_ROM is not enabled, this has no effect.
1891 bool "Compressed boot loader in ROM/flash"
1892 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1894 Say Y here if you intend to execute your compressed kernel image
1895 (zImage) directly from ROM or flash. If unsure, say N.
1898 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1899 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1900 default ZBOOT_ROM_NONE
1902 Include experimental SD/MMC loading code in the ROM-able zImage.
1903 With this enabled it is possible to write the ROM-able zImage
1904 kernel image to an MMC or SD card and boot the kernel straight
1905 from the reset vector. At reset the processor Mask ROM will load
1906 the first part of the ROM-able zImage which in turn loads the
1907 rest the kernel image to RAM.
1909 config ZBOOT_ROM_NONE
1910 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1912 Do not load image from SD or MMC
1914 config ZBOOT_ROM_MMCIF
1915 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1917 Load image from MMCIF hardware block.
1919 config ZBOOT_ROM_SH_MOBILE_SDHI
1920 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1922 Load image from SDHI hardware block
1926 config ARM_APPENDED_DTB
1927 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1928 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1930 With this option, the boot code will look for a device tree binary
1931 (DTB) appended to zImage
1932 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1934 This is meant as a backward compatibility convenience for those
1935 systems with a bootloader that can't be upgraded to accommodate
1936 the documented boot protocol using a device tree.
1938 Beware that there is very little in terms of protection against
1939 this option being confused by leftover garbage in memory that might
1940 look like a DTB header after a reboot if no actual DTB is appended
1941 to zImage. Do not leave this option active in a production kernel
1942 if you don't intend to always append a DTB. Proper passing of the
1943 location into r2 of a bootloader provided DTB is always preferable
1946 config ARM_ATAG_DTB_COMPAT
1947 bool "Supplement the appended DTB with traditional ATAG information"
1948 depends on ARM_APPENDED_DTB
1950 Some old bootloaders can't be updated to a DTB capable one, yet
1951 they provide ATAGs with memory configuration, the ramdisk address,
1952 the kernel cmdline string, etc. Such information is dynamically
1953 provided by the bootloader and can't always be stored in a static
1954 DTB. To allow a device tree enabled kernel to be used with such
1955 bootloaders, this option allows zImage to extract the information
1956 from the ATAG list and store it at run time into the appended DTB.
1959 string "Default kernel command string"
1962 On some architectures (EBSA110 and CATS), there is currently no way
1963 for the boot loader to pass arguments to the kernel. For these
1964 architectures, you should supply some command-line options at build
1965 time by entering them here. As a minimum, you should specify the
1966 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1969 prompt "Kernel command line type" if CMDLINE != ""
1970 default CMDLINE_FROM_BOOTLOADER
1972 config CMDLINE_FROM_BOOTLOADER
1973 bool "Use bootloader kernel arguments if available"
1975 Uses the command-line options passed by the boot loader. If
1976 the boot loader doesn't provide any, the default kernel command
1977 string provided in CMDLINE will be used.
1979 config CMDLINE_EXTEND
1980 bool "Extend bootloader kernel arguments"
1982 The command-line arguments provided by the boot loader will be
1983 appended to the default kernel command string.
1985 config CMDLINE_FORCE
1986 bool "Always use the default kernel command string"
1988 Always use the default kernel command string, even if the boot
1989 loader passes other arguments to the kernel.
1990 This is useful if you cannot or don't want to change the
1991 command-line options your boot loader passes to the kernel.
1995 bool "Kernel Execute-In-Place from ROM"
1996 depends on !ZBOOT_ROM && !ARM_LPAE
1998 Execute-In-Place allows the kernel to run from non-volatile storage
1999 directly addressable by the CPU, such as NOR flash. This saves RAM
2000 space since the text section of the kernel is not loaded from flash
2001 to RAM. Read-write sections, such as the data section and stack,
2002 are still copied to RAM. The XIP kernel is not compressed since
2003 it has to run directly from flash, so it will take more space to
2004 store it. The flash address used to link the kernel object files,
2005 and for storing it, is configuration dependent. Therefore, if you
2006 say Y here, you must know the proper physical address where to
2007 store the kernel image depending on your own flash memory usage.
2009 Also note that the make target becomes "make xipImage" rather than
2010 "make zImage" or "make Image". The final kernel binary to put in
2011 ROM memory will be arch/arm/boot/xipImage.
2015 config XIP_PHYS_ADDR
2016 hex "XIP Kernel Physical Location"
2017 depends on XIP_KERNEL
2018 default "0x00080000"
2020 This is the physical address in your flash memory the kernel will
2021 be linked for and stored to. This address is dependent on your
2025 bool "Kexec system call (EXPERIMENTAL)"
2026 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2028 kexec is a system call that implements the ability to shutdown your
2029 current kernel, and to start another kernel. It is like a reboot
2030 but it is independent of the system firmware. And like a reboot
2031 you can start any kernel with it, not just Linux.
2033 It is an ongoing process to be certain the hardware in a machine
2034 is properly shutdown, so do not be surprised if this code does not
2035 initially work for you. It may help to enable device hotplugging
2039 bool "Export atags in procfs"
2043 Should the atags used to boot the kernel be exported in an "atags"
2044 file in procfs. Useful with kexec.
2047 bool "Build kdump crash kernel (EXPERIMENTAL)"
2048 depends on EXPERIMENTAL
2050 Generate crash dump after being started by kexec. This should
2051 be normally only set in special crash dump kernels which are
2052 loaded in the main kernel with kexec-tools into a specially
2053 reserved region and then later executed after a crash by
2054 kdump/kexec. The crash dump kernel must be compiled to a
2055 memory address not used by the main kernel
2057 For more details see Documentation/kdump/kdump.txt
2059 config AUTO_ZRELADDR
2060 bool "Auto calculation of the decompressed kernel image address"
2061 depends on !ZBOOT_ROM && !ARCH_U300
2063 ZRELADDR is the physical address where the decompressed kernel
2064 image will be placed. If AUTO_ZRELADDR is selected, the address
2065 will be determined at run-time by masking the current IP with
2066 0xf8000000. This assumes the zImage being placed in the first 128MB
2067 from start of memory.
2071 menu "CPU Power Management"
2075 source "drivers/cpufreq/Kconfig"
2078 tristate "CPUfreq driver for i.MX CPUs"
2079 depends on ARCH_MXC && CPU_FREQ
2081 This enables the CPUfreq driver for i.MX CPUs.
2083 config CPU_FREQ_SA1100
2086 config CPU_FREQ_SA1110
2089 config CPU_FREQ_INTEGRATOR
2090 tristate "CPUfreq driver for ARM Integrator CPUs"
2091 depends on ARCH_INTEGRATOR && CPU_FREQ
2094 This enables the CPUfreq driver for ARM Integrator CPUs.
2096 For details, take a look at <file:Documentation/cpu-freq>.
2102 depends on CPU_FREQ && ARCH_PXA && PXA25x
2104 select CPU_FREQ_TABLE
2105 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2110 Internal configuration node for common cpufreq on Samsung SoC
2112 config CPU_FREQ_S3C24XX
2113 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2114 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2117 This enables the CPUfreq driver for the Samsung S3C24XX family
2120 For details, take a look at <file:Documentation/cpu-freq>.
2124 config CPU_FREQ_S3C24XX_PLL
2125 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2126 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2128 Compile in support for changing the PLL frequency from the
2129 S3C24XX series CPUfreq driver. The PLL takes time to settle
2130 after a frequency change, so by default it is not enabled.
2132 This also means that the PLL tables for the selected CPU(s) will
2133 be built which may increase the size of the kernel image.
2135 config CPU_FREQ_S3C24XX_DEBUG
2136 bool "Debug CPUfreq Samsung driver core"
2137 depends on CPU_FREQ_S3C24XX
2139 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2141 config CPU_FREQ_S3C24XX_IODEBUG
2142 bool "Debug CPUfreq Samsung driver IO timing"
2143 depends on CPU_FREQ_S3C24XX
2145 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2147 config CPU_FREQ_S3C24XX_DEBUGFS
2148 bool "Export debugfs for CPUFreq"
2149 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2151 Export status information via debugfs.
2155 source "drivers/cpuidle/Kconfig"
2159 menu "Floating point emulation"
2161 comment "At least one emulation must be selected"
2164 bool "NWFPE math emulation"
2165 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2167 Say Y to include the NWFPE floating point emulator in the kernel.
2168 This is necessary to run most binaries. Linux does not currently
2169 support floating point hardware so you need to say Y here even if
2170 your machine has an FPA or floating point co-processor podule.
2172 You may say N here if you are going to load the Acorn FPEmulator
2173 early in the bootup.
2176 bool "Support extended precision"
2177 depends on FPE_NWFPE
2179 Say Y to include 80-bit support in the kernel floating-point
2180 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2181 Note that gcc does not generate 80-bit operations by default,
2182 so in most cases this option only enlarges the size of the
2183 floating point emulator without any good reason.
2185 You almost surely want to say N here.
2188 bool "FastFPE math emulation (EXPERIMENTAL)"
2189 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2191 Say Y here to include the FAST floating point emulator in the kernel.
2192 This is an experimental much faster emulator which now also has full
2193 precision for the mantissa. It does not support any exceptions.
2194 It is very simple, and approximately 3-6 times faster than NWFPE.
2196 It should be sufficient for most programs. It may be not suitable
2197 for scientific calculations, but you have to check this for yourself.
2198 If you do not feel you need a faster FP emulation you should better
2202 bool "VFP-format floating point maths"
2203 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2205 Say Y to include VFP support code in the kernel. This is needed
2206 if your hardware includes a VFP unit.
2208 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2209 release notes and additional status information.
2211 Say N if your target does not have VFP hardware.
2219 bool "Advanced SIMD (NEON) Extension support"
2220 depends on VFPv3 && CPU_V7
2222 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2227 menu "Userspace binary formats"
2229 source "fs/Kconfig.binfmt"
2232 tristate "RISC OS personality"
2235 Say Y here to include the kernel code necessary if you want to run
2236 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2237 experimental; if this sounds frightening, say N and sleep in peace.
2238 You can also say M here to compile this support as a module (which
2239 will be called arthur).
2243 menu "Power management options"
2245 source "kernel/power/Kconfig"
2247 config ARCH_SUSPEND_POSSIBLE
2248 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2249 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2250 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2253 config ARM_CPU_SUSPEND
2258 source "net/Kconfig"
2260 source "drivers/Kconfig"
2264 source "arch/arm/Kconfig.debug"
2266 source "security/Kconfig"
2268 source "crypto/Kconfig"
2270 source "lib/Kconfig"