4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
276 select COMMON_CLK_VERSATILE
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_IO_H
283 select NEED_MACH_MEMORY_H
285 select MULTI_IRQ_HANDLER
287 Support for ARM's Integrator platform.
290 bool "ARM Ltd. RealView family"
293 select COMMON_CLK_VERSATILE
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLCD
299 select ARM_TIMER_SP804
300 select GPIO_PL061 if GPIOLIB
301 select NEED_MACH_MEMORY_H
303 This enables support for ARM Ltd RealView boards.
305 config ARCH_VERSATILE
306 bool "ARM Ltd. Versatile family"
310 select HAVE_MACH_CLKDEV
312 select GENERIC_CLOCKEVENTS
313 select ARCH_WANT_OPTIONAL_GPIOLIB
314 select NEED_MACH_IO_H if PCI
315 select PLAT_VERSATILE
316 select PLAT_VERSATILE_CLOCK
317 select PLAT_VERSATILE_CLCD
318 select PLAT_VERSATILE_FPGA_IRQ
319 select ARM_TIMER_SP804
321 This enables support for ARM Ltd Versatile board.
324 bool "ARM Ltd. Versatile Express family"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select ARM_TIMER_SP804
330 select GENERIC_CLOCKEVENTS
332 select HAVE_PATA_PLATFORM
335 select PLAT_VERSATILE
336 select PLAT_VERSATILE_CLCD
337 select REGULATOR_FIXED_VOLTAGE if REGULATOR
339 This enables support for the ARM Ltd Versatile Express boards.
343 select ARCH_REQUIRE_GPIOLIB
347 select NEED_MACH_IO_H if PCCARD
349 This enables support for systems based on Atmel
350 AT91RM9200 and AT91SAM9* processors.
353 bool "Broadcom BCMRING"
357 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select ARCH_WANT_OPTIONAL_GPIOLIB
362 Support for Broadcom's BCMRing platform.
365 bool "Calxeda Highbank-based"
366 select ARCH_WANT_OPTIONAL_GPIOLIB
369 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
380 Support for the Calxeda Highbank SoC based boards.
383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
385 select ARCH_USES_GETTIMEOFFSET
386 select NEED_MACH_MEMORY_H
388 Support for Cirrus Logic 711x/721x/731x based boards.
391 bool "Cavium Networks CNS3XXX family"
393 select GENERIC_CLOCKEVENTS
395 select MIGHT_HAVE_CACHE_L2X0
396 select MIGHT_HAVE_PCI
397 select PCI_DOMAINS if PCI
399 Support for Cavium Networks CNS3XXX platform.
402 bool "Cortina Systems Gemini"
404 select ARCH_REQUIRE_GPIOLIB
405 select ARCH_USES_GETTIMEOFFSET
407 Support for the Cortina Systems Gemini family SoCs
410 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
413 select ARCH_REQUIRE_GPIOLIB
414 select GENERIC_CLOCKEVENTS
416 select GENERIC_IRQ_CHIP
417 select MIGHT_HAVE_CACHE_L2X0
423 Support for CSR SiRFSoC ARM Cortex A9 Platform
430 select ARCH_USES_GETTIMEOFFSET
431 select NEED_MACH_IO_H
432 select NEED_MACH_MEMORY_H
434 This is an evaluation board for the StrongARM processor available
435 from Digital. It has limited hardware on-board, including an
436 Ethernet interface, two PCMCIA sockets, two serial ports and a
445 select ARCH_REQUIRE_GPIOLIB
446 select ARCH_HAS_HOLES_MEMORYMODEL
447 select ARCH_USES_GETTIMEOFFSET
448 select NEED_MACH_MEMORY_H
450 This enables support for the Cirrus EP93xx series of CPUs.
452 config ARCH_FOOTBRIDGE
456 select GENERIC_CLOCKEVENTS
458 select NEED_MACH_IO_H
459 select NEED_MACH_MEMORY_H
461 Support for systems based on the DC21285 companion chip
462 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
465 bool "Freescale MXC/iMX-based"
466 select GENERIC_CLOCKEVENTS
467 select ARCH_REQUIRE_GPIOLIB
470 select GENERIC_IRQ_CHIP
471 select MULTI_IRQ_HANDLER
475 Support for Freescale MXC/iMX-based family of processors
478 bool "Freescale MXS-based"
479 select GENERIC_CLOCKEVENTS
480 select ARCH_REQUIRE_GPIOLIB
484 select HAVE_CLK_PREPARE
488 Support for Freescale MXS-based family of processors
491 bool "Hilscher NetX based"
495 select GENERIC_CLOCKEVENTS
497 This enables support for systems based on the Hilscher NetX Soc
500 bool "Hynix HMS720x-based"
503 select ARCH_USES_GETTIMEOFFSET
505 This enables support for systems based on the Hynix HMS720x
513 select ARCH_SUPPORTS_MSI
515 select NEED_MACH_IO_H
516 select NEED_MACH_MEMORY_H
517 select NEED_RET_TO_USER
519 Support for Intel's IOP13XX (XScale) family of processors.
525 select NEED_MACH_IO_H
526 select NEED_RET_TO_USER
529 select ARCH_REQUIRE_GPIOLIB
531 Support for Intel's 80219 and IOP32X (XScale) family of
538 select NEED_MACH_IO_H
539 select NEED_RET_TO_USER
542 select ARCH_REQUIRE_GPIOLIB
544 Support for Intel's IOP33X (XScale) family of processors.
549 select ARCH_HAS_DMA_SET_COHERENT_MASK
552 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
554 select MIGHT_HAVE_PCI
555 select NEED_MACH_IO_H
556 select DMABOUNCE if PCI
558 Support for Intel's IXP4XX (XScale) family of processors.
561 bool "Marvell SOCs with Device Tree support"
562 select GENERIC_CLOCKEVENTS
563 select MULTI_IRQ_HANDLER
566 select GENERIC_IRQ_CHIP
570 Support for the Marvell SoC Family with device tree support
576 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
578 select NEED_MACH_IO_H
581 Support for the Marvell Dove SoC 88AP510
584 bool "Marvell Kirkwood"
587 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_CLOCKEVENTS
589 select NEED_MACH_IO_H
592 Support for the following Marvell Kirkwood series SoCs:
593 88F6180, 88F6192 and 88F6281.
599 select ARCH_REQUIRE_GPIOLIB
602 select USB_ARCH_HAS_OHCI
604 select GENERIC_CLOCKEVENTS
608 Support for the NXP LPC32XX family of processors
611 bool "Marvell MV78xx0"
614 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
616 select NEED_MACH_IO_H
619 Support for the following Marvell MV78xx0 series SoCs:
627 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
629 select NEED_MACH_IO_H
632 Support for the following Marvell Orion 5x series SoCs:
633 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
634 Orion-2 (5281), Orion-1-90 (6183).
637 bool "Marvell PXA168/910/MMP2"
639 select ARCH_REQUIRE_GPIOLIB
641 select GENERIC_CLOCKEVENTS
646 select GENERIC_ALLOCATOR
648 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
651 bool "Micrel/Kendin KS8695"
653 select ARCH_REQUIRE_GPIOLIB
654 select ARCH_USES_GETTIMEOFFSET
655 select NEED_MACH_MEMORY_H
657 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
658 System-on-Chip devices.
661 bool "Nuvoton W90X900 CPU"
663 select ARCH_REQUIRE_GPIOLIB
666 select GENERIC_CLOCKEVENTS
668 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
669 At present, the w90x900 has been renamed nuc900, regarding
670 the ARM series product line, you can login the following
671 link address to know more.
673 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
674 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
680 select GENERIC_CLOCKEVENTS
684 select MIGHT_HAVE_CACHE_L2X0
685 select NEED_MACH_IO_H if PCI
686 select ARCH_HAS_CPUFREQ
689 This enables support for NVIDIA Tegra based systems (Tegra APX,
690 Tegra 6xx and Tegra 2 series).
692 config ARCH_PICOXCELL
693 bool "Picochip picoXcell"
694 select ARCH_REQUIRE_GPIOLIB
695 select ARM_PATCH_PHYS_VIRT
699 select DW_APB_TIMER_OF
700 select GENERIC_CLOCKEVENTS
707 This enables support for systems based on the Picochip picoXcell
708 family of Femtocell devices. The picoxcell support requires device tree
712 bool "Philips Nexperia PNX4008 Mobile"
715 select ARCH_USES_GETTIMEOFFSET
717 This enables support for Philips PNX4008 mobile platform.
720 bool "PXA2xx/PXA3xx-based"
723 select ARCH_HAS_CPUFREQ
726 select ARCH_REQUIRE_GPIOLIB
727 select GENERIC_CLOCKEVENTS
732 select MULTI_IRQ_HANDLER
733 select ARM_CPU_SUSPEND if PM
736 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
741 select GENERIC_CLOCKEVENTS
742 select ARCH_REQUIRE_GPIOLIB
745 Support for Qualcomm MSM/QSD based systems. This runs on the
746 apps processor of the MSM/QSD and depends on a shared memory
747 interface to the modem processor which runs the baseband
748 stack and controls some vital subsystems
749 (clock and power control, etc).
752 bool "Renesas SH-Mobile / R-Mobile"
755 select HAVE_MACH_CLKDEV
757 select GENERIC_CLOCKEVENTS
758 select MIGHT_HAVE_CACHE_L2X0
761 select MULTI_IRQ_HANDLER
762 select PM_GENERIC_DOMAINS if PM
763 select NEED_MACH_MEMORY_H
765 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
771 select ARCH_MAY_HAVE_PC_FDC
772 select HAVE_PATA_PLATFORM
775 select ARCH_SPARSEMEM_ENABLE
776 select ARCH_USES_GETTIMEOFFSET
778 select NEED_MACH_IO_H
779 select NEED_MACH_MEMORY_H
781 On the Acorn Risc-PC, Linux can support the internal IDE disk and
782 CD-ROM interface, serial and parallel port, and the floppy drive.
789 select ARCH_SPARSEMEM_ENABLE
791 select ARCH_HAS_CPUFREQ
793 select GENERIC_CLOCKEVENTS
795 select ARCH_REQUIRE_GPIOLIB
797 select NEED_MACH_MEMORY_H
800 Support for StrongARM 11x0 based boards.
803 bool "Samsung S3C24XX SoCs"
805 select ARCH_HAS_CPUFREQ
808 select ARCH_USES_GETTIMEOFFSET
809 select HAVE_S3C2410_I2C if I2C
810 select HAVE_S3C_RTC if RTC_CLASS
811 select HAVE_S3C2410_WATCHDOG if WATCHDOG
812 select NEED_MACH_IO_H
814 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
815 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
816 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
817 Samsung SMDK2410 development board (and derivatives).
820 bool "Samsung S3C64XX"
828 select ARCH_USES_GETTIMEOFFSET
829 select ARCH_HAS_CPUFREQ
830 select ARCH_REQUIRE_GPIOLIB
831 select SAMSUNG_CLKSRC
832 select SAMSUNG_IRQ_VIC_TIMER
833 select S3C_GPIO_TRACK
835 select USB_ARCH_HAS_OHCI
836 select SAMSUNG_GPIOLIB_4BIT
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
840 Samsung S3C64XX series based systems
843 bool "Samsung S5P6440 S5P6450"
849 select HAVE_S3C2410_WATCHDOG if WATCHDOG
850 select GENERIC_CLOCKEVENTS
851 select HAVE_S3C2410_I2C if I2C
852 select HAVE_S3C_RTC if RTC_CLASS
854 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
858 bool "Samsung S5PC100"
863 select ARCH_USES_GETTIMEOFFSET
864 select HAVE_S3C2410_I2C if I2C
865 select HAVE_S3C_RTC if RTC_CLASS
866 select HAVE_S3C2410_WATCHDOG if WATCHDOG
868 Samsung S5PC100 series based systems
871 bool "Samsung S5PV210/S5PC110"
873 select ARCH_SPARSEMEM_ENABLE
874 select ARCH_HAS_HOLES_MEMORYMODEL
879 select ARCH_HAS_CPUFREQ
880 select GENERIC_CLOCKEVENTS
881 select HAVE_S3C2410_I2C if I2C
882 select HAVE_S3C_RTC if RTC_CLASS
883 select HAVE_S3C2410_WATCHDOG if WATCHDOG
884 select NEED_MACH_MEMORY_H
886 Samsung S5PV210/S5PC110 series based systems
889 bool "SAMSUNG EXYNOS"
891 select ARCH_SPARSEMEM_ENABLE
892 select ARCH_HAS_HOLES_MEMORYMODEL
896 select ARCH_HAS_CPUFREQ
897 select GENERIC_CLOCKEVENTS
898 select HAVE_S3C_RTC if RTC_CLASS
899 select HAVE_S3C2410_I2C if I2C
900 select HAVE_S3C2410_WATCHDOG if WATCHDOG
901 select NEED_MACH_MEMORY_H
903 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
912 select ARCH_USES_GETTIMEOFFSET
913 select NEED_MACH_MEMORY_H
914 select NEED_MACH_IO_H
916 Support for the StrongARM based Digital DNARD machine, also known
917 as "Shark" (<http://www.shark-linux.de/shark.html>).
920 bool "ST-Ericsson U300 Series"
926 select ARM_PATCH_PHYS_VIRT
928 select GENERIC_CLOCKEVENTS
932 select ARCH_REQUIRE_GPIOLIB
934 Support for ST-Ericsson U300 series mobile platforms.
937 bool "ST-Ericsson U8500 Series"
941 select GENERIC_CLOCKEVENTS
943 select ARCH_REQUIRE_GPIOLIB
944 select ARCH_HAS_CPUFREQ
946 select MIGHT_HAVE_CACHE_L2X0
948 Support for ST-Ericsson's Ux500 architecture
951 bool "STMicroelectronics Nomadik"
956 select GENERIC_CLOCKEVENTS
958 select MIGHT_HAVE_CACHE_L2X0
959 select ARCH_REQUIRE_GPIOLIB
961 Support for the Nomadik platform by ST-Ericsson
965 select GENERIC_CLOCKEVENTS
966 select ARCH_REQUIRE_GPIOLIB
970 select GENERIC_ALLOCATOR
971 select GENERIC_IRQ_CHIP
972 select ARCH_HAS_HOLES_MEMORYMODEL
974 Support for TI's DaVinci platform.
980 select ARCH_REQUIRE_GPIOLIB
981 select ARCH_HAS_CPUFREQ
983 select GENERIC_CLOCKEVENTS
984 select ARCH_HAS_HOLES_MEMORYMODEL
986 Support for TI's OMAP platform (OMAP1/2/3/4).
991 select ARCH_REQUIRE_GPIOLIB
995 select GENERIC_CLOCKEVENTS
998 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1001 bool "VIA/WonderMedia 85xx"
1004 select ARCH_HAS_CPUFREQ
1005 select GENERIC_CLOCKEVENTS
1006 select ARCH_REQUIRE_GPIOLIB
1008 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1011 bool "Xilinx Zynq ARM Cortex A9 Platform"
1013 select GENERIC_CLOCKEVENTS
1014 select CLKDEV_LOOKUP
1018 select MIGHT_HAVE_CACHE_L2X0
1021 Support for Xilinx Zynq ARM Cortex A9 Platform
1025 # This is sorted alphabetically by mach-* pathname. However, plat-*
1026 # Kconfigs may be included either alphabetically (according to the
1027 # plat- suffix) or along side the corresponding mach-* source.
1029 source "arch/arm/mach-mvebu/Kconfig"
1031 source "arch/arm/mach-at91/Kconfig"
1033 source "arch/arm/mach-bcmring/Kconfig"
1035 source "arch/arm/mach-clps711x/Kconfig"
1037 source "arch/arm/mach-cns3xxx/Kconfig"
1039 source "arch/arm/mach-davinci/Kconfig"
1041 source "arch/arm/mach-dove/Kconfig"
1043 source "arch/arm/mach-ep93xx/Kconfig"
1045 source "arch/arm/mach-footbridge/Kconfig"
1047 source "arch/arm/mach-gemini/Kconfig"
1049 source "arch/arm/mach-h720x/Kconfig"
1051 source "arch/arm/mach-integrator/Kconfig"
1053 source "arch/arm/mach-iop32x/Kconfig"
1055 source "arch/arm/mach-iop33x/Kconfig"
1057 source "arch/arm/mach-iop13xx/Kconfig"
1059 source "arch/arm/mach-ixp4xx/Kconfig"
1061 source "arch/arm/mach-kirkwood/Kconfig"
1063 source "arch/arm/mach-ks8695/Kconfig"
1065 source "arch/arm/mach-msm/Kconfig"
1067 source "arch/arm/mach-mv78xx0/Kconfig"
1069 source "arch/arm/plat-mxc/Kconfig"
1071 source "arch/arm/mach-mxs/Kconfig"
1073 source "arch/arm/mach-netx/Kconfig"
1075 source "arch/arm/mach-nomadik/Kconfig"
1076 source "arch/arm/plat-nomadik/Kconfig"
1078 source "arch/arm/plat-omap/Kconfig"
1080 source "arch/arm/mach-omap1/Kconfig"
1082 source "arch/arm/mach-omap2/Kconfig"
1084 source "arch/arm/mach-orion5x/Kconfig"
1086 source "arch/arm/mach-pxa/Kconfig"
1087 source "arch/arm/plat-pxa/Kconfig"
1089 source "arch/arm/mach-mmp/Kconfig"
1091 source "arch/arm/mach-realview/Kconfig"
1093 source "arch/arm/mach-sa1100/Kconfig"
1095 source "arch/arm/plat-samsung/Kconfig"
1096 source "arch/arm/plat-s3c24xx/Kconfig"
1098 source "arch/arm/plat-spear/Kconfig"
1100 source "arch/arm/mach-s3c24xx/Kconfig"
1102 source "arch/arm/mach-s3c2412/Kconfig"
1103 source "arch/arm/mach-s3c2440/Kconfig"
1107 source "arch/arm/mach-s3c64xx/Kconfig"
1110 source "arch/arm/mach-s5p64x0/Kconfig"
1112 source "arch/arm/mach-s5pc100/Kconfig"
1114 source "arch/arm/mach-s5pv210/Kconfig"
1116 source "arch/arm/mach-exynos/Kconfig"
1118 source "arch/arm/mach-shmobile/Kconfig"
1120 source "arch/arm/mach-tegra/Kconfig"
1122 source "arch/arm/mach-u300/Kconfig"
1124 source "arch/arm/mach-ux500/Kconfig"
1126 source "arch/arm/mach-versatile/Kconfig"
1128 source "arch/arm/mach-vexpress/Kconfig"
1129 source "arch/arm/plat-versatile/Kconfig"
1131 source "arch/arm/mach-vt8500/Kconfig"
1133 source "arch/arm/mach-w90x900/Kconfig"
1135 # Definitions to make life easier
1141 select GENERIC_CLOCKEVENTS
1146 select GENERIC_IRQ_CHIP
1153 config PLAT_VERSATILE
1156 config ARM_TIMER_SP804
1159 select HAVE_SCHED_CLOCK
1161 source arch/arm/mm/Kconfig
1165 default 16 if ARCH_EP93XX
1169 bool "Enable iWMMXt support"
1170 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1171 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1173 Enable support for iWMMXt context switching at run time if
1174 running on a CPU that supports it.
1178 depends on CPU_XSCALE
1182 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1183 (!ARCH_OMAP3 || OMAP3_EMU)
1187 config MULTI_IRQ_HANDLER
1190 Allow each machine to specify it's own IRQ handler at run time.
1193 source "arch/arm/Kconfig-nommu"
1196 config ARM_ERRATA_326103
1197 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1200 Executing a SWP instruction to read-only memory does not set bit 11
1201 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1202 treat the access as a read, preventing a COW from occurring and
1203 causing the faulting task to livelock.
1205 config ARM_ERRATA_411920
1206 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1207 depends on CPU_V6 || CPU_V6K
1209 Invalidation of the Instruction Cache operation can
1210 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1211 It does not affect the MPCore. This option enables the ARM Ltd.
1212 recommended workaround.
1214 config ARM_ERRATA_430973
1215 bool "ARM errata: Stale prediction on replaced interworking branch"
1218 This option enables the workaround for the 430973 Cortex-A8
1219 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1220 interworking branch is replaced with another code sequence at the
1221 same virtual address, whether due to self-modifying code or virtual
1222 to physical address re-mapping, Cortex-A8 does not recover from the
1223 stale interworking branch prediction. This results in Cortex-A8
1224 executing the new code sequence in the incorrect ARM or Thumb state.
1225 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1226 and also flushes the branch target cache at every context switch.
1227 Note that setting specific bits in the ACTLR register may not be
1228 available in non-secure mode.
1230 config ARM_ERRATA_458693
1231 bool "ARM errata: Processor deadlock when a false hazard is created"
1234 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1235 erratum. For very specific sequences of memory operations, it is
1236 possible for a hazard condition intended for a cache line to instead
1237 be incorrectly associated with a different cache line. This false
1238 hazard might then cause a processor deadlock. The workaround enables
1239 the L1 caching of the NEON accesses and disables the PLD instruction
1240 in the ACTLR register. Note that setting specific bits in the ACTLR
1241 register may not be available in non-secure mode.
1243 config ARM_ERRATA_460075
1244 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1247 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1248 erratum. Any asynchronous access to the L2 cache may encounter a
1249 situation in which recent store transactions to the L2 cache are lost
1250 and overwritten with stale memory contents from external memory. The
1251 workaround disables the write-allocate mode for the L2 cache via the
1252 ACTLR register. Note that setting specific bits in the ACTLR register
1253 may not be available in non-secure mode.
1255 config ARM_ERRATA_742230
1256 bool "ARM errata: DMB operation may be faulty"
1257 depends on CPU_V7 && SMP
1259 This option enables the workaround for the 742230 Cortex-A9
1260 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1261 between two write operations may not ensure the correct visibility
1262 ordering of the two writes. This workaround sets a specific bit in
1263 the diagnostic register of the Cortex-A9 which causes the DMB
1264 instruction to behave as a DSB, ensuring the correct behaviour of
1267 config ARM_ERRATA_742231
1268 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1269 depends on CPU_V7 && SMP
1271 This option enables the workaround for the 742231 Cortex-A9
1272 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1273 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1274 accessing some data located in the same cache line, may get corrupted
1275 data due to bad handling of the address hazard when the line gets
1276 replaced from one of the CPUs at the same time as another CPU is
1277 accessing it. This workaround sets specific bits in the diagnostic
1278 register of the Cortex-A9 which reduces the linefill issuing
1279 capabilities of the processor.
1281 config PL310_ERRATA_588369
1282 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1283 depends on CACHE_L2X0
1285 The PL310 L2 cache controller implements three types of Clean &
1286 Invalidate maintenance operations: by Physical Address
1287 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1288 They are architecturally defined to behave as the execution of a
1289 clean operation followed immediately by an invalidate operation,
1290 both performing to the same memory location. This functionality
1291 is not correctly implemented in PL310 as clean lines are not
1292 invalidated as a result of these operations.
1294 config ARM_ERRATA_720789
1295 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1298 This option enables the workaround for the 720789 Cortex-A9 (prior to
1299 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1300 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1301 As a consequence of this erratum, some TLB entries which should be
1302 invalidated are not, resulting in an incoherency in the system page
1303 tables. The workaround changes the TLB flushing routines to invalidate
1304 entries regardless of the ASID.
1306 config PL310_ERRATA_727915
1307 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1308 depends on CACHE_L2X0
1310 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1311 operation (offset 0x7FC). This operation runs in background so that
1312 PL310 can handle normal accesses while it is in progress. Under very
1313 rare circumstances, due to this erratum, write data can be lost when
1314 PL310 treats a cacheable write transaction during a Clean &
1315 Invalidate by Way operation.
1317 config ARM_ERRATA_743622
1318 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1321 This option enables the workaround for the 743622 Cortex-A9
1322 (r2p*) erratum. Under very rare conditions, a faulty
1323 optimisation in the Cortex-A9 Store Buffer may lead to data
1324 corruption. This workaround sets a specific bit in the diagnostic
1325 register of the Cortex-A9 which disables the Store Buffer
1326 optimisation, preventing the defect from occurring. This has no
1327 visible impact on the overall performance or power consumption of the
1330 config ARM_ERRATA_751472
1331 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1334 This option enables the workaround for the 751472 Cortex-A9 (prior
1335 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1336 completion of a following broadcasted operation if the second
1337 operation is received by a CPU before the ICIALLUIS has completed,
1338 potentially leading to corrupted entries in the cache or TLB.
1340 config PL310_ERRATA_753970
1341 bool "PL310 errata: cache sync operation may be faulty"
1342 depends on CACHE_PL310
1344 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1346 Under some condition the effect of cache sync operation on
1347 the store buffer still remains when the operation completes.
1348 This means that the store buffer is always asked to drain and
1349 this prevents it from merging any further writes. The workaround
1350 is to replace the normal offset of cache sync operation (0x730)
1351 by another offset targeting an unmapped PL310 register 0x740.
1352 This has the same effect as the cache sync operation: store buffer
1353 drain and waiting for all buffers empty.
1355 config ARM_ERRATA_754322
1356 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1359 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1360 r3p*) erratum. A speculative memory access may cause a page table walk
1361 which starts prior to an ASID switch but completes afterwards. This
1362 can populate the micro-TLB with a stale entry which may be hit with
1363 the new ASID. This workaround places two dsb instructions in the mm
1364 switching code so that no page table walks can cross the ASID switch.
1366 config ARM_ERRATA_754327
1367 bool "ARM errata: no automatic Store Buffer drain"
1368 depends on CPU_V7 && SMP
1370 This option enables the workaround for the 754327 Cortex-A9 (prior to
1371 r2p0) erratum. The Store Buffer does not have any automatic draining
1372 mechanism and therefore a livelock may occur if an external agent
1373 continuously polls a memory location waiting to observe an update.
1374 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1375 written polling loops from denying visibility of updates to memory.
1377 config ARM_ERRATA_364296
1378 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1379 depends on CPU_V6 && !SMP
1381 This options enables the workaround for the 364296 ARM1136
1382 r0p2 erratum (possible cache data corruption with
1383 hit-under-miss enabled). It sets the undocumented bit 31 in
1384 the auxiliary control register and the FI bit in the control
1385 register, thus disabling hit-under-miss without putting the
1386 processor into full low interrupt latency mode. ARM11MPCore
1389 config ARM_ERRATA_764369
1390 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1391 depends on CPU_V7 && SMP
1393 This option enables the workaround for erratum 764369
1394 affecting Cortex-A9 MPCore with two or more processors (all
1395 current revisions). Under certain timing circumstances, a data
1396 cache line maintenance operation by MVA targeting an Inner
1397 Shareable memory region may fail to proceed up to either the
1398 Point of Coherency or to the Point of Unification of the
1399 system. This workaround adds a DSB instruction before the
1400 relevant cache maintenance functions and sets a specific bit
1401 in the diagnostic control register of the SCU.
1403 config PL310_ERRATA_769419
1404 bool "PL310 errata: no automatic Store Buffer drain"
1405 depends on CACHE_L2X0
1407 On revisions of the PL310 prior to r3p2, the Store Buffer does
1408 not automatically drain. This can cause normal, non-cacheable
1409 writes to be retained when the memory system is idle, leading
1410 to suboptimal I/O performance for drivers using coherent DMA.
1411 This option adds a write barrier to the cpu_idle loop so that,
1412 on systems with an outer cache, the store buffer is drained
1417 source "arch/arm/common/Kconfig"
1427 Find out whether you have ISA slots on your motherboard. ISA is the
1428 name of a bus system, i.e. the way the CPU talks to the other stuff
1429 inside your box. Other bus systems are PCI, EISA, MicroChannel
1430 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1431 newer boards don't support it. If you have ISA, say Y, otherwise N.
1433 # Select ISA DMA controller support
1438 # Select ISA DMA interface
1443 bool "PCI support" if MIGHT_HAVE_PCI
1445 Find out whether you have a PCI motherboard. PCI is the name of a
1446 bus system, i.e. the way the CPU talks to the other stuff inside
1447 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1448 VESA. If you have PCI, say Y, otherwise N.
1454 config PCI_NANOENGINE
1455 bool "BSE nanoEngine PCI support"
1456 depends on SA1100_NANOENGINE
1458 Enable PCI on the BSE nanoEngine board.
1463 # Select the host bridge type
1464 config PCI_HOST_VIA82C505
1466 depends on PCI && ARCH_SHARK
1469 config PCI_HOST_ITE8152
1471 depends on PCI && MACH_ARMCORE
1475 source "drivers/pci/Kconfig"
1477 source "drivers/pcmcia/Kconfig"
1481 menu "Kernel Features"
1486 This option should be selected by machines which have an SMP-
1489 The only effect of this option is to make the SMP-related
1490 options available to the user for configuration.
1493 bool "Symmetric Multi-Processing"
1494 depends on CPU_V6K || CPU_V7
1495 depends on GENERIC_CLOCKEVENTS
1498 select USE_GENERIC_SMP_HELPERS
1499 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1501 This enables support for systems with more than one CPU. If you have
1502 a system with only one CPU, like most personal computers, say N. If
1503 you have a system with more than one CPU, say Y.
1505 If you say N here, the kernel will run on single and multiprocessor
1506 machines, but will use only one CPU of a multiprocessor machine. If
1507 you say Y here, the kernel will run on many, but not all, single
1508 processor machines. On a single processor machine, the kernel will
1509 run faster if you say N here.
1511 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1512 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1513 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1515 If you don't know what to do here, say N.
1518 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1519 depends on EXPERIMENTAL
1520 depends on SMP && !XIP_KERNEL
1523 SMP kernels contain instructions which fail on non-SMP processors.
1524 Enabling this option allows the kernel to modify itself to make
1525 these instructions safe. Disabling it allows about 1K of space
1528 If you don't know what to do here, say Y.
1530 config ARM_CPU_TOPOLOGY
1531 bool "Support cpu topology definition"
1532 depends on SMP && CPU_V7
1535 Support ARM cpu topology definition. The MPIDR register defines
1536 affinity between processors which is then used to describe the cpu
1537 topology of an ARM System.
1540 bool "Multi-core scheduler support"
1541 depends on ARM_CPU_TOPOLOGY
1543 Multi-core scheduler support improves the CPU scheduler's decision
1544 making when dealing with multi-core CPU chips at a cost of slightly
1545 increased overhead in some places. If unsure say N here.
1548 bool "SMT scheduler support"
1549 depends on ARM_CPU_TOPOLOGY
1551 Improves the CPU scheduler's decision making when dealing with
1552 MultiThreading at a cost of slightly increased overhead in some
1553 places. If unsure say N here.
1558 This option enables support for the ARM system coherency unit
1560 config ARM_ARCH_TIMER
1561 bool "Architected timer support"
1564 This option enables support for the ARM architected timer
1570 This options enables support for the ARM timer and watchdog unit
1573 prompt "Memory split"
1576 Select the desired split between kernel and user memory.
1578 If you are not absolutely sure what you are doing, leave this
1582 bool "3G/1G user/kernel split"
1584 bool "2G/2G user/kernel split"
1586 bool "1G/3G user/kernel split"
1591 default 0x40000000 if VMSPLIT_1G
1592 default 0x80000000 if VMSPLIT_2G
1596 int "Maximum number of CPUs (2-32)"
1602 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1603 depends on SMP && HOTPLUG && EXPERIMENTAL
1605 Say Y here to experiment with turning CPUs off and on. CPUs
1606 can be controlled through /sys/devices/system/cpu.
1609 bool "Use local timer interrupts"
1612 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1614 Enable support for local timers on SMP platforms, rather then the
1615 legacy IPI broadcast method. Local timers allows the system
1616 accounting to be spread across the timer interval, preventing a
1617 "thundering herd" at every timer tick.
1621 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1622 default 355 if ARCH_U8500
1623 default 264 if MACH_H4700
1624 default 512 if SOC_OMAP5
1627 Maximum number of GPIOs in the system.
1629 If unsure, leave the default value.
1631 source kernel/Kconfig.preempt
1635 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1636 ARCH_S5PV210 || ARCH_EXYNOS4
1637 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1638 default AT91_TIMER_HZ if ARCH_AT91
1639 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1642 config THUMB2_KERNEL
1643 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1644 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1646 select ARM_ASM_UNIFIED
1649 By enabling this option, the kernel will be compiled in
1650 Thumb-2 mode. A compiler/assembler that understand the unified
1651 ARM-Thumb syntax is needed.
1655 config THUMB2_AVOID_R_ARM_THM_JUMP11
1656 bool "Work around buggy Thumb-2 short branch relocations in gas"
1657 depends on THUMB2_KERNEL && MODULES
1660 Various binutils versions can resolve Thumb-2 branches to
1661 locally-defined, preemptible global symbols as short-range "b.n"
1662 branch instructions.
1664 This is a problem, because there's no guarantee the final
1665 destination of the symbol, or any candidate locations for a
1666 trampoline, are within range of the branch. For this reason, the
1667 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1668 relocation in modules at all, and it makes little sense to add
1671 The symptom is that the kernel fails with an "unsupported
1672 relocation" error when loading some modules.
1674 Until fixed tools are available, passing
1675 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1676 code which hits this problem, at the cost of a bit of extra runtime
1677 stack usage in some cases.
1679 The problem is described in more detail at:
1680 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1682 Only Thumb-2 kernels are affected.
1684 Unless you are sure your tools don't have this problem, say Y.
1686 config ARM_ASM_UNIFIED
1690 bool "Use the ARM EABI to compile the kernel"
1692 This option allows for the kernel to be compiled using the latest
1693 ARM ABI (aka EABI). This is only useful if you are using a user
1694 space environment that is also compiled with EABI.
1696 Since there are major incompatibilities between the legacy ABI and
1697 EABI, especially with regard to structure member alignment, this
1698 option also changes the kernel syscall calling convention to
1699 disambiguate both ABIs and allow for backward compatibility support
1700 (selected with CONFIG_OABI_COMPAT).
1702 To use this you need GCC version 4.0.0 or later.
1705 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1706 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1709 This option preserves the old syscall interface along with the
1710 new (ARM EABI) one. It also provides a compatibility layer to
1711 intercept syscalls that have structure arguments which layout
1712 in memory differs between the legacy ABI and the new ARM EABI
1713 (only for non "thumb" binaries). This option adds a tiny
1714 overhead to all syscalls and produces a slightly larger kernel.
1715 If you know you'll be using only pure EABI user space then you
1716 can say N here. If this option is not selected and you attempt
1717 to execute a legacy ABI binary then the result will be
1718 UNPREDICTABLE (in fact it can be predicted that it won't work
1719 at all). If in doubt say Y.
1721 config ARCH_HAS_HOLES_MEMORYMODEL
1724 config ARCH_SPARSEMEM_ENABLE
1727 config ARCH_SPARSEMEM_DEFAULT
1728 def_bool ARCH_SPARSEMEM_ENABLE
1730 config ARCH_SELECT_MEMORY_MODEL
1731 def_bool ARCH_SPARSEMEM_ENABLE
1733 config HAVE_ARCH_PFN_VALID
1734 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1737 bool "High Memory Support"
1740 The address space of ARM processors is only 4 Gigabytes large
1741 and it has to accommodate user address space, kernel address
1742 space as well as some memory mapped IO. That means that, if you
1743 have a large amount of physical memory and/or IO, not all of the
1744 memory can be "permanently mapped" by the kernel. The physical
1745 memory that is not permanently mapped is called "high memory".
1747 Depending on the selected kernel/user memory split, minimum
1748 vmalloc space and actual amount of RAM, you may not need this
1749 option which should result in a slightly faster kernel.
1754 bool "Allocate 2nd-level pagetables from highmem"
1757 config HW_PERF_EVENTS
1758 bool "Enable hardware performance counter support for perf events"
1759 depends on PERF_EVENTS && CPU_HAS_PMU
1762 Enable hardware performance counter support for perf events. If
1763 disabled, perf events will use software events only.
1767 config FORCE_MAX_ZONEORDER
1768 int "Maximum zone order" if ARCH_SHMOBILE
1769 range 11 64 if ARCH_SHMOBILE
1770 default "9" if SA1111
1773 The kernel memory allocator divides physically contiguous memory
1774 blocks into "zones", where each zone is a power of two number of
1775 pages. This option selects the largest power of two that the kernel
1776 keeps in the memory allocator. If you need to allocate very large
1777 blocks of physically contiguous memory, then you may need to
1778 increase this value.
1780 This config option is actually maximum order plus one. For example,
1781 a value of 11 means that the largest free memory block is 2^10 pages.
1784 bool "Timer and CPU usage LEDs"
1785 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1786 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1787 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1788 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1789 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1790 ARCH_AT91 || ARCH_DAVINCI || \
1791 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1793 If you say Y here, the LEDs on your machine will be used
1794 to provide useful information about your current system status.
1796 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1797 be able to select which LEDs are active using the options below. If
1798 you are compiling a kernel for the EBSA-110 or the LART however, the
1799 red LED will simply flash regularly to indicate that the system is
1800 still functional. It is safe to say Y here if you have a CATS
1801 system, but the driver will do nothing.
1804 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1805 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1806 || MACH_OMAP_PERSEUS2
1808 depends on !GENERIC_CLOCKEVENTS
1809 default y if ARCH_EBSA110
1811 If you say Y here, one of the system LEDs (the green one on the
1812 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1813 will flash regularly to indicate that the system is still
1814 operational. This is mainly useful to kernel hackers who are
1815 debugging unstable kernels.
1817 The LART uses the same LED for both Timer LED and CPU usage LED
1818 functions. You may choose to use both, but the Timer LED function
1819 will overrule the CPU usage LED.
1822 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1824 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1825 || MACH_OMAP_PERSEUS2
1828 If you say Y here, the red LED will be used to give a good real
1829 time indication of CPU usage, by lighting whenever the idle task
1830 is not currently executing.
1832 The LART uses the same LED for both Timer LED and CPU usage LED
1833 functions. You may choose to use both, but the Timer LED function
1834 will overrule the CPU usage LED.
1836 config ALIGNMENT_TRAP
1838 depends on CPU_CP15_MMU
1839 default y if !ARCH_EBSA110
1840 select HAVE_PROC_CPU if PROC_FS
1842 ARM processors cannot fetch/store information which is not
1843 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1844 address divisible by 4. On 32-bit ARM processors, these non-aligned
1845 fetch/store instructions will be emulated in software if you say
1846 here, which has a severe performance impact. This is necessary for
1847 correct operation of some network protocols. With an IP-only
1848 configuration it is safe to say N, otherwise say Y.
1850 config UACCESS_WITH_MEMCPY
1851 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1852 depends on MMU && EXPERIMENTAL
1853 default y if CPU_FEROCEON
1855 Implement faster copy_to_user and clear_user methods for CPU
1856 cores where a 8-word STM instruction give significantly higher
1857 memory write throughput than a sequence of individual 32bit stores.
1859 A possible side effect is a slight increase in scheduling latency
1860 between threads sharing the same address space if they invoke
1861 such copy operations with large buffers.
1863 However, if the CPU data cache is using a write-allocate mode,
1864 this option is unlikely to provide any performance gain.
1868 prompt "Enable seccomp to safely compute untrusted bytecode"
1870 This kernel feature is useful for number crunching applications
1871 that may need to compute untrusted bytecode during their
1872 execution. By using pipes or other transports made available to
1873 the process as file descriptors supporting the read/write
1874 syscalls, it's possible to isolate those applications in
1875 their own address space using seccomp. Once seccomp is
1876 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1877 and the task is only allowed to execute a few safe syscalls
1878 defined by each seccomp mode.
1880 config CC_STACKPROTECTOR
1881 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1882 depends on EXPERIMENTAL
1884 This option turns on the -fstack-protector GCC feature. This
1885 feature puts, at the beginning of functions, a canary value on
1886 the stack just before the return address, and validates
1887 the value just before actually returning. Stack based buffer
1888 overflows (that need to overwrite this return address) now also
1889 overwrite the canary, which gets detected and the attack is then
1890 neutralized via a kernel panic.
1891 This feature requires gcc version 4.2 or above.
1893 config DEPRECATED_PARAM_STRUCT
1894 bool "Provide old way to pass kernel parameters"
1896 This was deprecated in 2001 and announced to live on for 5 years.
1897 Some old boot loaders still use this way.
1904 bool "Flattened Device Tree support"
1906 select OF_EARLY_FLATTREE
1909 Include support for flattened device tree machine descriptions.
1911 # Compressed boot loader in ROM. Yes, we really want to ask about
1912 # TEXT and BSS so we preserve their values in the config files.
1913 config ZBOOT_ROM_TEXT
1914 hex "Compressed ROM boot loader base address"
1917 The physical address at which the ROM-able zImage is to be
1918 placed in the target. Platforms which normally make use of
1919 ROM-able zImage formats normally set this to a suitable
1920 value in their defconfig file.
1922 If ZBOOT_ROM is not enabled, this has no effect.
1924 config ZBOOT_ROM_BSS
1925 hex "Compressed ROM boot loader BSS address"
1928 The base address of an area of read/write memory in the target
1929 for the ROM-able zImage which must be available while the
1930 decompressor is running. It must be large enough to hold the
1931 entire decompressed kernel plus an additional 128 KiB.
1932 Platforms which normally make use of ROM-able zImage formats
1933 normally set this to a suitable value in their defconfig file.
1935 If ZBOOT_ROM is not enabled, this has no effect.
1938 bool "Compressed boot loader in ROM/flash"
1939 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1941 Say Y here if you intend to execute your compressed kernel image
1942 (zImage) directly from ROM or flash. If unsure, say N.
1945 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1946 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1947 default ZBOOT_ROM_NONE
1949 Include experimental SD/MMC loading code in the ROM-able zImage.
1950 With this enabled it is possible to write the ROM-able zImage
1951 kernel image to an MMC or SD card and boot the kernel straight
1952 from the reset vector. At reset the processor Mask ROM will load
1953 the first part of the ROM-able zImage which in turn loads the
1954 rest the kernel image to RAM.
1956 config ZBOOT_ROM_NONE
1957 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1959 Do not load image from SD or MMC
1961 config ZBOOT_ROM_MMCIF
1962 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1964 Load image from MMCIF hardware block.
1966 config ZBOOT_ROM_SH_MOBILE_SDHI
1967 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1969 Load image from SDHI hardware block
1973 config ARM_APPENDED_DTB
1974 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1975 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1977 With this option, the boot code will look for a device tree binary
1978 (DTB) appended to zImage
1979 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1981 This is meant as a backward compatibility convenience for those
1982 systems with a bootloader that can't be upgraded to accommodate
1983 the documented boot protocol using a device tree.
1985 Beware that there is very little in terms of protection against
1986 this option being confused by leftover garbage in memory that might
1987 look like a DTB header after a reboot if no actual DTB is appended
1988 to zImage. Do not leave this option active in a production kernel
1989 if you don't intend to always append a DTB. Proper passing of the
1990 location into r2 of a bootloader provided DTB is always preferable
1993 config ARM_ATAG_DTB_COMPAT
1994 bool "Supplement the appended DTB with traditional ATAG information"
1995 depends on ARM_APPENDED_DTB
1997 Some old bootloaders can't be updated to a DTB capable one, yet
1998 they provide ATAGs with memory configuration, the ramdisk address,
1999 the kernel cmdline string, etc. Such information is dynamically
2000 provided by the bootloader and can't always be stored in a static
2001 DTB. To allow a device tree enabled kernel to be used with such
2002 bootloaders, this option allows zImage to extract the information
2003 from the ATAG list and store it at run time into the appended DTB.
2006 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2007 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2009 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2010 bool "Use bootloader kernel arguments if available"
2012 Uses the command-line options passed by the boot loader instead of
2013 the device tree bootargs property. If the boot loader doesn't provide
2014 any, the device tree bootargs property will be used.
2016 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2017 bool "Extend with bootloader kernel arguments"
2019 The command-line arguments provided by the boot loader will be
2020 appended to the the device tree bootargs property.
2025 string "Default kernel command string"
2028 On some architectures (EBSA110 and CATS), there is currently no way
2029 for the boot loader to pass arguments to the kernel. For these
2030 architectures, you should supply some command-line options at build
2031 time by entering them here. As a minimum, you should specify the
2032 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2035 prompt "Kernel command line type" if CMDLINE != ""
2036 default CMDLINE_FROM_BOOTLOADER
2038 config CMDLINE_FROM_BOOTLOADER
2039 bool "Use bootloader kernel arguments if available"
2041 Uses the command-line options passed by the boot loader. If
2042 the boot loader doesn't provide any, the default kernel command
2043 string provided in CMDLINE will be used.
2045 config CMDLINE_EXTEND
2046 bool "Extend bootloader kernel arguments"
2048 The command-line arguments provided by the boot loader will be
2049 appended to the default kernel command string.
2051 config CMDLINE_FORCE
2052 bool "Always use the default kernel command string"
2054 Always use the default kernel command string, even if the boot
2055 loader passes other arguments to the kernel.
2056 This is useful if you cannot or don't want to change the
2057 command-line options your boot loader passes to the kernel.
2061 bool "Kernel Execute-In-Place from ROM"
2062 depends on !ZBOOT_ROM && !ARM_LPAE
2064 Execute-In-Place allows the kernel to run from non-volatile storage
2065 directly addressable by the CPU, such as NOR flash. This saves RAM
2066 space since the text section of the kernel is not loaded from flash
2067 to RAM. Read-write sections, such as the data section and stack,
2068 are still copied to RAM. The XIP kernel is not compressed since
2069 it has to run directly from flash, so it will take more space to
2070 store it. The flash address used to link the kernel object files,
2071 and for storing it, is configuration dependent. Therefore, if you
2072 say Y here, you must know the proper physical address where to
2073 store the kernel image depending on your own flash memory usage.
2075 Also note that the make target becomes "make xipImage" rather than
2076 "make zImage" or "make Image". The final kernel binary to put in
2077 ROM memory will be arch/arm/boot/xipImage.
2081 config XIP_PHYS_ADDR
2082 hex "XIP Kernel Physical Location"
2083 depends on XIP_KERNEL
2084 default "0x00080000"
2086 This is the physical address in your flash memory the kernel will
2087 be linked for and stored to. This address is dependent on your
2091 bool "Kexec system call (EXPERIMENTAL)"
2092 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2094 kexec is a system call that implements the ability to shutdown your
2095 current kernel, and to start another kernel. It is like a reboot
2096 but it is independent of the system firmware. And like a reboot
2097 you can start any kernel with it, not just Linux.
2099 It is an ongoing process to be certain the hardware in a machine
2100 is properly shutdown, so do not be surprised if this code does not
2101 initially work for you. It may help to enable device hotplugging
2105 bool "Export atags in procfs"
2109 Should the atags used to boot the kernel be exported in an "atags"
2110 file in procfs. Useful with kexec.
2113 bool "Build kdump crash kernel (EXPERIMENTAL)"
2114 depends on EXPERIMENTAL
2116 Generate crash dump after being started by kexec. This should
2117 be normally only set in special crash dump kernels which are
2118 loaded in the main kernel with kexec-tools into a specially
2119 reserved region and then later executed after a crash by
2120 kdump/kexec. The crash dump kernel must be compiled to a
2121 memory address not used by the main kernel
2123 For more details see Documentation/kdump/kdump.txt
2125 config AUTO_ZRELADDR
2126 bool "Auto calculation of the decompressed kernel image address"
2127 depends on !ZBOOT_ROM && !ARCH_U300
2129 ZRELADDR is the physical address where the decompressed kernel
2130 image will be placed. If AUTO_ZRELADDR is selected, the address
2131 will be determined at run-time by masking the current IP with
2132 0xf8000000. This assumes the zImage being placed in the first 128MB
2133 from start of memory.
2137 menu "CPU Power Management"
2141 source "drivers/cpufreq/Kconfig"
2144 tristate "CPUfreq driver for i.MX CPUs"
2145 depends on ARCH_MXC && CPU_FREQ
2146 select CPU_FREQ_TABLE
2148 This enables the CPUfreq driver for i.MX CPUs.
2150 config CPU_FREQ_SA1100
2153 config CPU_FREQ_SA1110
2156 config CPU_FREQ_INTEGRATOR
2157 tristate "CPUfreq driver for ARM Integrator CPUs"
2158 depends on ARCH_INTEGRATOR && CPU_FREQ
2161 This enables the CPUfreq driver for ARM Integrator CPUs.
2163 For details, take a look at <file:Documentation/cpu-freq>.
2169 depends on CPU_FREQ && ARCH_PXA && PXA25x
2171 select CPU_FREQ_TABLE
2172 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2177 Internal configuration node for common cpufreq on Samsung SoC
2179 config CPU_FREQ_S3C24XX
2180 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2181 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2184 This enables the CPUfreq driver for the Samsung S3C24XX family
2187 For details, take a look at <file:Documentation/cpu-freq>.
2191 config CPU_FREQ_S3C24XX_PLL
2192 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2193 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2195 Compile in support for changing the PLL frequency from the
2196 S3C24XX series CPUfreq driver. The PLL takes time to settle
2197 after a frequency change, so by default it is not enabled.
2199 This also means that the PLL tables for the selected CPU(s) will
2200 be built which may increase the size of the kernel image.
2202 config CPU_FREQ_S3C24XX_DEBUG
2203 bool "Debug CPUfreq Samsung driver core"
2204 depends on CPU_FREQ_S3C24XX
2206 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2208 config CPU_FREQ_S3C24XX_IODEBUG
2209 bool "Debug CPUfreq Samsung driver IO timing"
2210 depends on CPU_FREQ_S3C24XX
2212 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2214 config CPU_FREQ_S3C24XX_DEBUGFS
2215 bool "Export debugfs for CPUFreq"
2216 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2218 Export status information via debugfs.
2222 source "drivers/cpuidle/Kconfig"
2226 menu "Floating point emulation"
2228 comment "At least one emulation must be selected"
2231 bool "NWFPE math emulation"
2232 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2234 Say Y to include the NWFPE floating point emulator in the kernel.
2235 This is necessary to run most binaries. Linux does not currently
2236 support floating point hardware so you need to say Y here even if
2237 your machine has an FPA or floating point co-processor podule.
2239 You may say N here if you are going to load the Acorn FPEmulator
2240 early in the bootup.
2243 bool "Support extended precision"
2244 depends on FPE_NWFPE
2246 Say Y to include 80-bit support in the kernel floating-point
2247 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2248 Note that gcc does not generate 80-bit operations by default,
2249 so in most cases this option only enlarges the size of the
2250 floating point emulator without any good reason.
2252 You almost surely want to say N here.
2255 bool "FastFPE math emulation (EXPERIMENTAL)"
2256 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2258 Say Y here to include the FAST floating point emulator in the kernel.
2259 This is an experimental much faster emulator which now also has full
2260 precision for the mantissa. It does not support any exceptions.
2261 It is very simple, and approximately 3-6 times faster than NWFPE.
2263 It should be sufficient for most programs. It may be not suitable
2264 for scientific calculations, but you have to check this for yourself.
2265 If you do not feel you need a faster FP emulation you should better
2269 bool "VFP-format floating point maths"
2270 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2272 Say Y to include VFP support code in the kernel. This is needed
2273 if your hardware includes a VFP unit.
2275 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2276 release notes and additional status information.
2278 Say N if your target does not have VFP hardware.
2286 bool "Advanced SIMD (NEON) Extension support"
2287 depends on VFPv3 && CPU_V7
2289 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2294 menu "Userspace binary formats"
2296 source "fs/Kconfig.binfmt"
2299 tristate "RISC OS personality"
2302 Say Y here to include the kernel code necessary if you want to run
2303 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2304 experimental; if this sounds frightening, say N and sleep in peace.
2305 You can also say M here to compile this support as a module (which
2306 will be called arthur).
2310 menu "Power management options"
2312 source "kernel/power/Kconfig"
2314 config ARCH_SUSPEND_POSSIBLE
2315 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2316 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2317 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2320 config ARM_CPU_SUSPEND
2325 source "net/Kconfig"
2327 source "drivers/Kconfig"
2331 source "arch/arm/Kconfig.debug"
2333 source "security/Kconfig"
2335 source "crypto/Kconfig"
2337 source "lib/Kconfig"