4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_KERNEL_THREAD
16 select GENERIC_KERNEL_EXECVE
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
70 config NEED_SG_DMA_LENGTH
73 config ARM_DMA_USE_IOMMU
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
84 config SYS_SUPPORTS_APM_EMULATION
92 select GENERIC_ALLOCATOR
103 The Extended Industry Standard Architecture (EISA) bus was
104 developed as an open alternative to the IBM MicroChannel bus.
106 The EISA bus provided some of the features of the IBM MicroChannel
107 bus while maintaining backward compatibility with cards made for
108 the older ISA bus. The EISA bus saw limited use between 1988 and
109 1995 when it was made obsolete by the PCI bus.
111 Say Y here if you are building a kernel for an EISA-based machine.
118 config STACKTRACE_SUPPORT
122 config HAVE_LATENCYTOP_SUPPORT
127 config LOCKDEP_SUPPORT
131 config TRACE_IRQFLAGS_SUPPORT
135 config RWSEM_GENERIC_SPINLOCK
139 config RWSEM_XCHGADD_ALGORITHM
142 config ARCH_HAS_ILOG2_U32
145 config ARCH_HAS_ILOG2_U64
148 config ARCH_HAS_CPUFREQ
151 Internal node to signify that the ARCH has CPUFREQ support
152 and that the relevant menu configurations are displayed for
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config ARCH_HAS_DMA_SET_COHERENT_MASK
175 config GENERIC_ISA_DMA
181 config NEED_RET_TO_USER
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime" if EMBEDDED
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary.
208 Only disable this option if you know that you do not require
209 this feature (eg, building a kernel for a single machine) and
210 you need to shrink the kernel to the minimal size.
212 config NEED_MACH_GPIO_H
215 Select this when mach/gpio.h is required to provide special
216 definitions for this platform. The need for mach/gpio.h should
217 be avoided when possible.
219 config NEED_MACH_IO_H
222 Select this when mach/io.h is required to provide special
223 definitions for this platform. The need for mach/io.h should
224 be avoided when possible.
226 config NEED_MACH_MEMORY_H
229 Select this when mach/memory.h is required to provide special
230 definitions for this platform. The need for mach/memory.h should
231 be avoided when possible.
234 hex "Physical address of main memory" if MMU
235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236 default DRAM_BASE if !MMU
238 Please provide the physical address corresponding to the
239 location of main memory in your system.
245 source "init/Kconfig"
247 source "kernel/Kconfig.freezer"
252 bool "MMU-based Paged Memory Management Support"
255 Select if you want MMU-based virtualised addressing space
256 support by paged memory management. If unsure, say 'Y'.
259 # The "ARM system type" choice list is ordered alphabetically by option
260 # text. Please add new entries in the option alphabetic order.
263 prompt "ARM system type"
264 default ARCH_MULTIPLATFORM
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
269 select ARM_PATCH_PHYS_VIRT
272 select MULTI_IRQ_HANDLER
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
288 select PLAT_VERSATILE_FPGA_IRQ
291 Support for ARM's Integrator platform.
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select ARM_TIMER_SP804
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select PLAT_VERSATILE_FPGA_IRQ
324 This enables support for ARM Ltd Versatile board.
328 select ARCH_REQUIRE_GPIOLIB
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
335 This enables support for systems based on Atmel
336 AT91RM9200 and AT91SAM9* processors.
339 bool "Broadcom BCM2835 family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_ERRATA_411920
343 select ARM_TIMER_SP804
347 select GENERIC_CLOCKEVENTS
348 select MULTI_IRQ_HANDLER
352 This enables support for the Broadcom BCM2835 SoC. This SoC is
353 use in the Raspberry Pi, and Roku 2 devices.
356 bool "Cavium Networks CNS3XXX family"
359 select GENERIC_CLOCKEVENTS
360 select MIGHT_HAVE_CACHE_L2X0
361 select MIGHT_HAVE_PCI
362 select PCI_DOMAINS if PCI
364 Support for Cavium Networks CNS3XXX platform.
367 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
368 select ARCH_USES_GETTIMEOFFSET
372 select NEED_MACH_MEMORY_H
374 Support for Cirrus Logic 711x/721x/731x based boards.
377 bool "Cortina Systems Gemini"
378 select ARCH_REQUIRE_GPIOLIB
379 select ARCH_USES_GETTIMEOFFSET
382 Support for the Cortina Systems Gemini family SoCs
386 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
389 select GENERIC_IRQ_CHIP
390 select MIGHT_HAVE_CACHE_L2X0
396 Support for CSR SiRFprimaII/Marco/Polo platforms
400 select ARCH_USES_GETTIMEOFFSET
403 select NEED_MACH_IO_H
404 select NEED_MACH_MEMORY_H
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 select ARCH_HAS_HOLES_MEMORYMODEL
415 select ARCH_REQUIRE_GPIOLIB
416 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_MEMORY_H
423 This enables support for the Cirrus EP93xx series of CPUs.
425 config ARCH_FOOTBRIDGE
429 select GENERIC_CLOCKEVENTS
431 select NEED_MACH_IO_H if !MMU
432 select NEED_MACH_MEMORY_H
434 Support for systems based on the DC21285 companion chip
435 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
438 bool "Freescale MXC/iMX-based"
439 select ARCH_REQUIRE_GPIOLIB
442 select GENERIC_CLOCKEVENTS
443 select GENERIC_IRQ_CHIP
444 select MULTI_IRQ_HANDLER
448 Support for Freescale MXC/iMX-based family of processors
451 bool "Freescale MXS-based"
452 select ARCH_REQUIRE_GPIOLIB
456 select GENERIC_CLOCKEVENTS
457 select HAVE_CLK_PREPARE
458 select MULTI_IRQ_HANDLER
463 Support for Freescale MXS-based family of processors
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
475 bool "Hynix HMS720x-based"
476 select ARCH_USES_GETTIMEOFFSET
480 This enables support for systems based on the Hynix HMS720x
485 select ARCH_SUPPORTS_MSI
487 select NEED_MACH_MEMORY_H
488 select NEED_RET_TO_USER
493 Support for Intel's IOP13XX (XScale) family of processors.
498 select ARCH_REQUIRE_GPIOLIB
500 select NEED_MACH_GPIO_H
501 select NEED_RET_TO_USER
505 Support for Intel's 80219 and IOP32X (XScale) family of
511 select ARCH_REQUIRE_GPIOLIB
513 select NEED_MACH_GPIO_H
514 select NEED_RET_TO_USER
518 Support for Intel's IOP33X (XScale) family of processors.
523 select ARCH_HAS_DMA_SET_COHERENT_MASK
524 select ARCH_REQUIRE_GPIOLIB
527 select DMABOUNCE if PCI
528 select GENERIC_CLOCKEVENTS
529 select MIGHT_HAVE_PCI
530 select NEED_MACH_IO_H
532 Support for Intel's IXP4XX (XScale) family of processors.
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
539 select MIGHT_HAVE_PCI
540 select PLAT_ORION_LEGACY
541 select USB_ARCH_HAS_EHCI
543 Support for the Marvell Dove SoC 88AP510
546 bool "Marvell Kirkwood"
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Kirkwood series SoCs:
554 88F6180, 88F6192 and 88F6281.
557 bool "Marvell MV78xx0"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
562 select PLAT_ORION_LEGACY
564 Support for the following Marvell MV78xx0 series SoCs:
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
574 select PLAT_ORION_LEGACY
576 Support for the following Marvell Orion 5x series SoCs:
577 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
578 Orion-2 (5281), Orion-1-90 (6183).
581 bool "Marvell PXA168/910/MMP2"
583 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_ALLOCATOR
586 select GENERIC_CLOCKEVENTS
589 select NEED_MACH_GPIO_H
593 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
596 bool "Micrel/Kendin KS8695"
597 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
601 select NEED_MACH_MEMORY_H
603 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
604 System-on-Chip devices.
607 bool "Nuvoton W90X900 CPU"
608 select ARCH_REQUIRE_GPIOLIB
612 select GENERIC_CLOCKEVENTS
614 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
615 At present, the w90x900 has been renamed nuc900, regarding
616 the ARM series product line, you can login the following
617 link address to know more.
619 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
620 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
624 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
632 select USB_ARCH_HAS_OHCI
635 Support for the NXP LPC32XX family of processors
639 select ARCH_HAS_CPUFREQ
643 select GENERIC_CLOCKEVENTS
647 select MIGHT_HAVE_CACHE_L2X0
650 This enables support for NVIDIA Tegra based systems (Tegra APX,
651 Tegra 6xx and Tegra 2 series).
654 bool "PXA2xx/PXA3xx-based"
656 select ARCH_HAS_CPUFREQ
658 select ARCH_REQUIRE_GPIOLIB
659 select ARM_CPU_SUSPEND if PM
663 select GENERIC_CLOCKEVENTS
666 select MULTI_IRQ_HANDLER
667 select NEED_MACH_GPIO_H
671 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
675 select ARCH_REQUIRE_GPIOLIB
677 select GENERIC_CLOCKEVENTS
680 Support for Qualcomm MSM/QSD based systems. This runs on the
681 apps processor of the MSM/QSD and depends on a shared memory
682 interface to the modem processor which runs the baseband
683 stack and controls some vital subsystems
684 (clock and power control, etc).
687 bool "Renesas SH-Mobile / R-Mobile"
689 select GENERIC_CLOCKEVENTS
691 select HAVE_MACH_CLKDEV
693 select MIGHT_HAVE_CACHE_L2X0
694 select MULTI_IRQ_HANDLER
695 select NEED_MACH_MEMORY_H
697 select PM_GENERIC_DOMAINS if PM
700 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
705 select ARCH_MAY_HAVE_PC_FDC
706 select ARCH_SPARSEMEM_ENABLE
707 select ARCH_USES_GETTIMEOFFSET
710 select HAVE_PATA_PLATFORM
712 select NEED_MACH_IO_H
713 select NEED_MACH_MEMORY_H
716 On the Acorn Risc-PC, Linux can support the internal IDE disk and
717 CD-ROM interface, serial and parallel port, and the floppy drive.
721 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
724 select ARCH_SPARSEMEM_ENABLE
729 select GENERIC_CLOCKEVENTS
732 select NEED_MACH_GPIO_H
733 select NEED_MACH_MEMORY_H
736 Support for StrongARM 11x0 based boards.
739 bool "Samsung S3C24XX SoCs"
740 select ARCH_HAS_CPUFREQ
741 select ARCH_USES_GETTIMEOFFSET
745 select HAVE_S3C2410_I2C if I2C
746 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 select HAVE_S3C_RTC if RTC_CLASS
748 select NEED_MACH_GPIO_H
749 select NEED_MACH_IO_H
751 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
752 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
753 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
754 Samsung SMDK2410 development board (and derivatives).
757 bool "Samsung S3C64XX"
758 select ARCH_HAS_CPUFREQ
759 select ARCH_REQUIRE_GPIOLIB
760 select ARCH_USES_GETTIMEOFFSET
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select NEED_MACH_GPIO_H
772 select S3C_GPIO_TRACK
773 select SAMSUNG_CLKSRC
774 select SAMSUNG_GPIOLIB_4BIT
775 select SAMSUNG_IRQ_VIC_TIMER
776 select USB_ARCH_HAS_OHCI
778 Samsung S3C64XX series based systems
781 bool "Samsung S5P6440 S5P6450"
785 select GENERIC_CLOCKEVENTS
788 select HAVE_S3C2410_I2C if I2C
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 select HAVE_S3C_RTC if RTC_CLASS
791 select NEED_MACH_GPIO_H
793 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
797 bool "Samsung S5PC100"
798 select ARCH_USES_GETTIMEOFFSET
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select HAVE_S3C_RTC if RTC_CLASS
806 select NEED_MACH_GPIO_H
808 Samsung S5PC100 series based systems
811 bool "Samsung S5PV210/S5PC110"
812 select ARCH_HAS_CPUFREQ
813 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARCH_SPARSEMEM_ENABLE
818 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select HAVE_S3C_RTC if RTC_CLASS
824 select NEED_MACH_GPIO_H
825 select NEED_MACH_MEMORY_H
827 Samsung S5PV210/S5PC110 series based systems
830 bool "Samsung EXYNOS"
831 select ARCH_HAS_CPUFREQ
832 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARCH_SPARSEMEM_ENABLE
836 select GENERIC_CLOCKEVENTS
839 select HAVE_S3C2410_I2C if I2C
840 select HAVE_S3C2410_WATCHDOG if WATCHDOG
841 select HAVE_S3C_RTC if RTC_CLASS
842 select NEED_MACH_GPIO_H
843 select NEED_MACH_MEMORY_H
845 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
849 select ARCH_USES_GETTIMEOFFSET
853 select NEED_MACH_MEMORY_H
857 Support for the StrongARM based Digital DNARD machine, also known
858 as "Shark" (<http://www.shark-linux.de/shark.html>).
861 bool "ST-Ericsson U300 Series"
863 select ARCH_REQUIRE_GPIOLIB
865 select ARM_PATCH_PHYS_VIRT
871 select GENERIC_CLOCKEVENTS
876 Support for ST-Ericsson U300 series mobile platforms.
879 bool "ST-Ericsson U8500 Series"
881 select ARCH_HAS_CPUFREQ
882 select ARCH_REQUIRE_GPIOLIB
886 select GENERIC_CLOCKEVENTS
888 select MIGHT_HAVE_CACHE_L2X0
890 Support for ST-Ericsson's Ux500 architecture
893 bool "STMicroelectronics Nomadik"
894 select ARCH_REQUIRE_GPIOLIB
899 select GENERIC_CLOCKEVENTS
900 select MIGHT_HAVE_CACHE_L2X0
902 select PINCTRL_STN8815
904 Support for the Nomadik platform by ST-Ericsson
908 select ARCH_REQUIRE_GPIOLIB
913 select GENERIC_CLOCKEVENTS
916 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
920 select ARCH_HAS_HOLES_MEMORYMODEL
921 select ARCH_REQUIRE_GPIOLIB
923 select GENERIC_ALLOCATOR
924 select GENERIC_CLOCKEVENTS
925 select GENERIC_IRQ_CHIP
927 select NEED_MACH_GPIO_H
930 Support for TI's DaVinci platform.
935 select ARCH_HAS_CPUFREQ
936 select ARCH_HAS_HOLES_MEMORYMODEL
937 select ARCH_REQUIRE_GPIOLIB
939 select GENERIC_CLOCKEVENTS
941 select NEED_MACH_GPIO_H
943 Support for TI's OMAP platform (OMAP1/2/3/4).
946 bool "VIA/WonderMedia 85xx"
947 select ARCH_HAS_CPUFREQ
948 select ARCH_REQUIRE_GPIOLIB
952 select GENERIC_CLOCKEVENTS
957 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
960 bool "Xilinx Zynq ARM Cortex A9 Platform"
964 select GENERIC_CLOCKEVENTS
966 select MIGHT_HAVE_CACHE_L2X0
969 Support for Xilinx Zynq ARM Cortex A9 Platform
972 menu "Multiple platform selection"
973 depends on ARCH_MULTIPLATFORM
975 comment "CPU Core family selection"
978 bool "ARMv4 based platforms (FA526, StrongARM)"
979 depends on !ARCH_MULTI_V6_V7
980 select ARCH_MULTI_V4_V5
982 config ARCH_MULTI_V4T
983 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
984 depends on !ARCH_MULTI_V6_V7
985 select ARCH_MULTI_V4_V5
988 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
989 depends on !ARCH_MULTI_V6_V7
990 select ARCH_MULTI_V4_V5
992 config ARCH_MULTI_V4_V5
996 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
997 select ARCH_MULTI_V6_V7
1000 config ARCH_MULTI_V7
1001 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1003 select ARCH_MULTI_V6_V7
1004 select ARCH_VEXPRESS
1007 config ARCH_MULTI_V6_V7
1010 config ARCH_MULTI_CPU_AUTO
1011 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1012 select ARCH_MULTI_V5
1017 # This is sorted alphabetically by mach-* pathname. However, plat-*
1018 # Kconfigs may be included either alphabetically (according to the
1019 # plat- suffix) or along side the corresponding mach-* source.
1021 source "arch/arm/mach-mvebu/Kconfig"
1023 source "arch/arm/mach-at91/Kconfig"
1025 source "arch/arm/mach-clps711x/Kconfig"
1027 source "arch/arm/mach-cns3xxx/Kconfig"
1029 source "arch/arm/mach-davinci/Kconfig"
1031 source "arch/arm/mach-dove/Kconfig"
1033 source "arch/arm/mach-ep93xx/Kconfig"
1035 source "arch/arm/mach-footbridge/Kconfig"
1037 source "arch/arm/mach-gemini/Kconfig"
1039 source "arch/arm/mach-h720x/Kconfig"
1041 source "arch/arm/mach-highbank/Kconfig"
1043 source "arch/arm/mach-integrator/Kconfig"
1045 source "arch/arm/mach-iop32x/Kconfig"
1047 source "arch/arm/mach-iop33x/Kconfig"
1049 source "arch/arm/mach-iop13xx/Kconfig"
1051 source "arch/arm/mach-ixp4xx/Kconfig"
1053 source "arch/arm/mach-kirkwood/Kconfig"
1055 source "arch/arm/mach-ks8695/Kconfig"
1057 source "arch/arm/mach-msm/Kconfig"
1059 source "arch/arm/mach-mv78xx0/Kconfig"
1061 source "arch/arm/plat-mxc/Kconfig"
1063 source "arch/arm/mach-mxs/Kconfig"
1065 source "arch/arm/mach-netx/Kconfig"
1067 source "arch/arm/mach-nomadik/Kconfig"
1068 source "arch/arm/plat-nomadik/Kconfig"
1070 source "arch/arm/plat-omap/Kconfig"
1072 source "arch/arm/mach-omap1/Kconfig"
1074 source "arch/arm/mach-omap2/Kconfig"
1076 source "arch/arm/mach-orion5x/Kconfig"
1078 source "arch/arm/mach-picoxcell/Kconfig"
1080 source "arch/arm/mach-pxa/Kconfig"
1081 source "arch/arm/plat-pxa/Kconfig"
1083 source "arch/arm/mach-mmp/Kconfig"
1085 source "arch/arm/mach-realview/Kconfig"
1087 source "arch/arm/mach-sa1100/Kconfig"
1089 source "arch/arm/plat-samsung/Kconfig"
1090 source "arch/arm/plat-s3c24xx/Kconfig"
1092 source "arch/arm/mach-socfpga/Kconfig"
1094 source "arch/arm/plat-spear/Kconfig"
1096 source "arch/arm/mach-s3c24xx/Kconfig"
1098 source "arch/arm/mach-s3c2412/Kconfig"
1099 source "arch/arm/mach-s3c2440/Kconfig"
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-prima2/Kconfig"
1118 source "arch/arm/mach-tegra/Kconfig"
1120 source "arch/arm/mach-u300/Kconfig"
1122 source "arch/arm/mach-ux500/Kconfig"
1124 source "arch/arm/mach-versatile/Kconfig"
1126 source "arch/arm/mach-vexpress/Kconfig"
1127 source "arch/arm/plat-versatile/Kconfig"
1129 source "arch/arm/mach-w90x900/Kconfig"
1131 # Definitions to make life easier
1137 select GENERIC_CLOCKEVENTS
1143 select GENERIC_IRQ_CHIP
1146 config PLAT_ORION_LEGACY
1153 config PLAT_VERSATILE
1156 config ARM_TIMER_SP804
1159 select HAVE_SCHED_CLOCK
1161 source arch/arm/mm/Kconfig
1165 default 16 if ARCH_EP93XX
1169 bool "Enable iWMMXt support"
1170 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1171 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1173 Enable support for iWMMXt context switching at run time if
1174 running on a CPU that supports it.
1178 depends on CPU_XSCALE
1181 config MULTI_IRQ_HANDLER
1184 Allow each machine to specify it's own IRQ handler at run time.
1187 source "arch/arm/Kconfig-nommu"
1190 config ARM_ERRATA_326103
1191 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1194 Executing a SWP instruction to read-only memory does not set bit 11
1195 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1196 treat the access as a read, preventing a COW from occurring and
1197 causing the faulting task to livelock.
1199 config ARM_ERRATA_411920
1200 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1201 depends on CPU_V6 || CPU_V6K
1203 Invalidation of the Instruction Cache operation can
1204 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1205 It does not affect the MPCore. This option enables the ARM Ltd.
1206 recommended workaround.
1208 config ARM_ERRATA_430973
1209 bool "ARM errata: Stale prediction on replaced interworking branch"
1212 This option enables the workaround for the 430973 Cortex-A8
1213 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1214 interworking branch is replaced with another code sequence at the
1215 same virtual address, whether due to self-modifying code or virtual
1216 to physical address re-mapping, Cortex-A8 does not recover from the
1217 stale interworking branch prediction. This results in Cortex-A8
1218 executing the new code sequence in the incorrect ARM or Thumb state.
1219 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1220 and also flushes the branch target cache at every context switch.
1221 Note that setting specific bits in the ACTLR register may not be
1222 available in non-secure mode.
1224 config ARM_ERRATA_458693
1225 bool "ARM errata: Processor deadlock when a false hazard is created"
1228 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1229 erratum. For very specific sequences of memory operations, it is
1230 possible for a hazard condition intended for a cache line to instead
1231 be incorrectly associated with a different cache line. This false
1232 hazard might then cause a processor deadlock. The workaround enables
1233 the L1 caching of the NEON accesses and disables the PLD instruction
1234 in the ACTLR register. Note that setting specific bits in the ACTLR
1235 register may not be available in non-secure mode.
1237 config ARM_ERRATA_460075
1238 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1241 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1242 erratum. Any asynchronous access to the L2 cache may encounter a
1243 situation in which recent store transactions to the L2 cache are lost
1244 and overwritten with stale memory contents from external memory. The
1245 workaround disables the write-allocate mode for the L2 cache via the
1246 ACTLR register. Note that setting specific bits in the ACTLR register
1247 may not be available in non-secure mode.
1249 config ARM_ERRATA_742230
1250 bool "ARM errata: DMB operation may be faulty"
1251 depends on CPU_V7 && SMP
1253 This option enables the workaround for the 742230 Cortex-A9
1254 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1255 between two write operations may not ensure the correct visibility
1256 ordering of the two writes. This workaround sets a specific bit in
1257 the diagnostic register of the Cortex-A9 which causes the DMB
1258 instruction to behave as a DSB, ensuring the correct behaviour of
1261 config ARM_ERRATA_742231
1262 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1263 depends on CPU_V7 && SMP
1265 This option enables the workaround for the 742231 Cortex-A9
1266 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1267 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1268 accessing some data located in the same cache line, may get corrupted
1269 data due to bad handling of the address hazard when the line gets
1270 replaced from one of the CPUs at the same time as another CPU is
1271 accessing it. This workaround sets specific bits in the diagnostic
1272 register of the Cortex-A9 which reduces the linefill issuing
1273 capabilities of the processor.
1275 config PL310_ERRATA_588369
1276 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1277 depends on CACHE_L2X0
1279 The PL310 L2 cache controller implements three types of Clean &
1280 Invalidate maintenance operations: by Physical Address
1281 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1282 They are architecturally defined to behave as the execution of a
1283 clean operation followed immediately by an invalidate operation,
1284 both performing to the same memory location. This functionality
1285 is not correctly implemented in PL310 as clean lines are not
1286 invalidated as a result of these operations.
1288 config ARM_ERRATA_720789
1289 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1292 This option enables the workaround for the 720789 Cortex-A9 (prior to
1293 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1294 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1295 As a consequence of this erratum, some TLB entries which should be
1296 invalidated are not, resulting in an incoherency in the system page
1297 tables. The workaround changes the TLB flushing routines to invalidate
1298 entries regardless of the ASID.
1300 config PL310_ERRATA_727915
1301 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1302 depends on CACHE_L2X0
1304 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1305 operation (offset 0x7FC). This operation runs in background so that
1306 PL310 can handle normal accesses while it is in progress. Under very
1307 rare circumstances, due to this erratum, write data can be lost when
1308 PL310 treats a cacheable write transaction during a Clean &
1309 Invalidate by Way operation.
1311 config ARM_ERRATA_743622
1312 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1315 This option enables the workaround for the 743622 Cortex-A9
1316 (r2p*) erratum. Under very rare conditions, a faulty
1317 optimisation in the Cortex-A9 Store Buffer may lead to data
1318 corruption. This workaround sets a specific bit in the diagnostic
1319 register of the Cortex-A9 which disables the Store Buffer
1320 optimisation, preventing the defect from occurring. This has no
1321 visible impact on the overall performance or power consumption of the
1324 config ARM_ERRATA_751472
1325 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1328 This option enables the workaround for the 751472 Cortex-A9 (prior
1329 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1330 completion of a following broadcasted operation if the second
1331 operation is received by a CPU before the ICIALLUIS has completed,
1332 potentially leading to corrupted entries in the cache or TLB.
1334 config PL310_ERRATA_753970
1335 bool "PL310 errata: cache sync operation may be faulty"
1336 depends on CACHE_PL310
1338 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1340 Under some condition the effect of cache sync operation on
1341 the store buffer still remains when the operation completes.
1342 This means that the store buffer is always asked to drain and
1343 this prevents it from merging any further writes. The workaround
1344 is to replace the normal offset of cache sync operation (0x730)
1345 by another offset targeting an unmapped PL310 register 0x740.
1346 This has the same effect as the cache sync operation: store buffer
1347 drain and waiting for all buffers empty.
1349 config ARM_ERRATA_754322
1350 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1353 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1354 r3p*) erratum. A speculative memory access may cause a page table walk
1355 which starts prior to an ASID switch but completes afterwards. This
1356 can populate the micro-TLB with a stale entry which may be hit with
1357 the new ASID. This workaround places two dsb instructions in the mm
1358 switching code so that no page table walks can cross the ASID switch.
1360 config ARM_ERRATA_754327
1361 bool "ARM errata: no automatic Store Buffer drain"
1362 depends on CPU_V7 && SMP
1364 This option enables the workaround for the 754327 Cortex-A9 (prior to
1365 r2p0) erratum. The Store Buffer does not have any automatic draining
1366 mechanism and therefore a livelock may occur if an external agent
1367 continuously polls a memory location waiting to observe an update.
1368 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1369 written polling loops from denying visibility of updates to memory.
1371 config ARM_ERRATA_364296
1372 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1373 depends on CPU_V6 && !SMP
1375 This options enables the workaround for the 364296 ARM1136
1376 r0p2 erratum (possible cache data corruption with
1377 hit-under-miss enabled). It sets the undocumented bit 31 in
1378 the auxiliary control register and the FI bit in the control
1379 register, thus disabling hit-under-miss without putting the
1380 processor into full low interrupt latency mode. ARM11MPCore
1383 config ARM_ERRATA_764369
1384 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1385 depends on CPU_V7 && SMP
1387 This option enables the workaround for erratum 764369
1388 affecting Cortex-A9 MPCore with two or more processors (all
1389 current revisions). Under certain timing circumstances, a data
1390 cache line maintenance operation by MVA targeting an Inner
1391 Shareable memory region may fail to proceed up to either the
1392 Point of Coherency or to the Point of Unification of the
1393 system. This workaround adds a DSB instruction before the
1394 relevant cache maintenance functions and sets a specific bit
1395 in the diagnostic control register of the SCU.
1397 config PL310_ERRATA_769419
1398 bool "PL310 errata: no automatic Store Buffer drain"
1399 depends on CACHE_L2X0
1401 On revisions of the PL310 prior to r3p2, the Store Buffer does
1402 not automatically drain. This can cause normal, non-cacheable
1403 writes to be retained when the memory system is idle, leading
1404 to suboptimal I/O performance for drivers using coherent DMA.
1405 This option adds a write barrier to the cpu_idle loop so that,
1406 on systems with an outer cache, the store buffer is drained
1409 config ARM_ERRATA_775420
1410 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1413 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1414 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1415 operation aborts with MMU exception, it might cause the processor
1416 to deadlock. This workaround puts DSB before executing ISB if
1417 an abort may occur on cache maintenance.
1421 source "arch/arm/common/Kconfig"
1431 Find out whether you have ISA slots on your motherboard. ISA is the
1432 name of a bus system, i.e. the way the CPU talks to the other stuff
1433 inside your box. Other bus systems are PCI, EISA, MicroChannel
1434 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1435 newer boards don't support it. If you have ISA, say Y, otherwise N.
1437 # Select ISA DMA controller support
1442 # Select ISA DMA interface
1447 bool "PCI support" if MIGHT_HAVE_PCI
1449 Find out whether you have a PCI motherboard. PCI is the name of a
1450 bus system, i.e. the way the CPU talks to the other stuff inside
1451 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1452 VESA. If you have PCI, say Y, otherwise N.
1458 config PCI_NANOENGINE
1459 bool "BSE nanoEngine PCI support"
1460 depends on SA1100_NANOENGINE
1462 Enable PCI on the BSE nanoEngine board.
1467 # Select the host bridge type
1468 config PCI_HOST_VIA82C505
1470 depends on PCI && ARCH_SHARK
1473 config PCI_HOST_ITE8152
1475 depends on PCI && MACH_ARMCORE
1479 source "drivers/pci/Kconfig"
1481 source "drivers/pcmcia/Kconfig"
1485 menu "Kernel Features"
1490 This option should be selected by machines which have an SMP-
1493 The only effect of this option is to make the SMP-related
1494 options available to the user for configuration.
1497 bool "Symmetric Multi-Processing"
1498 depends on CPU_V6K || CPU_V7
1499 depends on GENERIC_CLOCKEVENTS
1502 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1503 select USE_GENERIC_SMP_HELPERS
1505 This enables support for systems with more than one CPU. If you have
1506 a system with only one CPU, like most personal computers, say N. If
1507 you have a system with more than one CPU, say Y.
1509 If you say N here, the kernel will run on single and multiprocessor
1510 machines, but will use only one CPU of a multiprocessor machine. If
1511 you say Y here, the kernel will run on many, but not all, single
1512 processor machines. On a single processor machine, the kernel will
1513 run faster if you say N here.
1515 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1516 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1517 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1519 If you don't know what to do here, say N.
1522 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1523 depends on EXPERIMENTAL
1524 depends on SMP && !XIP_KERNEL
1527 SMP kernels contain instructions which fail on non-SMP processors.
1528 Enabling this option allows the kernel to modify itself to make
1529 these instructions safe. Disabling it allows about 1K of space
1532 If you don't know what to do here, say Y.
1534 config ARM_CPU_TOPOLOGY
1535 bool "Support cpu topology definition"
1536 depends on SMP && CPU_V7
1539 Support ARM cpu topology definition. The MPIDR register defines
1540 affinity between processors which is then used to describe the cpu
1541 topology of an ARM System.
1544 bool "Multi-core scheduler support"
1545 depends on ARM_CPU_TOPOLOGY
1547 Multi-core scheduler support improves the CPU scheduler's decision
1548 making when dealing with multi-core CPU chips at a cost of slightly
1549 increased overhead in some places. If unsure say N here.
1552 bool "SMT scheduler support"
1553 depends on ARM_CPU_TOPOLOGY
1555 Improves the CPU scheduler's decision making when dealing with
1556 MultiThreading at a cost of slightly increased overhead in some
1557 places. If unsure say N here.
1562 This option enables support for the ARM system coherency unit
1564 config ARM_ARCH_TIMER
1565 bool "Architected timer support"
1568 This option enables support for the ARM architected timer
1574 This options enables support for the ARM timer and watchdog unit
1577 prompt "Memory split"
1580 Select the desired split between kernel and user memory.
1582 If you are not absolutely sure what you are doing, leave this
1586 bool "3G/1G user/kernel split"
1588 bool "2G/2G user/kernel split"
1590 bool "1G/3G user/kernel split"
1595 default 0x40000000 if VMSPLIT_1G
1596 default 0x80000000 if VMSPLIT_2G
1600 int "Maximum number of CPUs (2-32)"
1606 bool "Support for hot-pluggable CPUs"
1607 depends on SMP && HOTPLUG
1609 Say Y here to experiment with turning CPUs off and on. CPUs
1610 can be controlled through /sys/devices/system/cpu.
1613 bool "Use local timer interrupts"
1616 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1618 Enable support for local timers on SMP platforms, rather then the
1619 legacy IPI broadcast method. Local timers allows the system
1620 accounting to be spread across the timer interval, preventing a
1621 "thundering herd" at every timer tick.
1625 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1626 default 355 if ARCH_U8500
1627 default 264 if MACH_H4700
1628 default 512 if SOC_OMAP5
1629 default 288 if ARCH_VT8500
1632 Maximum number of GPIOs in the system.
1634 If unsure, leave the default value.
1636 source kernel/Kconfig.preempt
1640 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1641 ARCH_S5PV210 || ARCH_EXYNOS4
1642 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1643 default AT91_TIMER_HZ if ARCH_AT91
1644 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1647 config THUMB2_KERNEL
1648 bool "Compile the kernel in Thumb-2 mode"
1649 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1651 select ARM_ASM_UNIFIED
1654 By enabling this option, the kernel will be compiled in
1655 Thumb-2 mode. A compiler/assembler that understand the unified
1656 ARM-Thumb syntax is needed.
1660 config THUMB2_AVOID_R_ARM_THM_JUMP11
1661 bool "Work around buggy Thumb-2 short branch relocations in gas"
1662 depends on THUMB2_KERNEL && MODULES
1665 Various binutils versions can resolve Thumb-2 branches to
1666 locally-defined, preemptible global symbols as short-range "b.n"
1667 branch instructions.
1669 This is a problem, because there's no guarantee the final
1670 destination of the symbol, or any candidate locations for a
1671 trampoline, are within range of the branch. For this reason, the
1672 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1673 relocation in modules at all, and it makes little sense to add
1676 The symptom is that the kernel fails with an "unsupported
1677 relocation" error when loading some modules.
1679 Until fixed tools are available, passing
1680 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1681 code which hits this problem, at the cost of a bit of extra runtime
1682 stack usage in some cases.
1684 The problem is described in more detail at:
1685 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1687 Only Thumb-2 kernels are affected.
1689 Unless you are sure your tools don't have this problem, say Y.
1691 config ARM_ASM_UNIFIED
1695 bool "Use the ARM EABI to compile the kernel"
1697 This option allows for the kernel to be compiled using the latest
1698 ARM ABI (aka EABI). This is only useful if you are using a user
1699 space environment that is also compiled with EABI.
1701 Since there are major incompatibilities between the legacy ABI and
1702 EABI, especially with regard to structure member alignment, this
1703 option also changes the kernel syscall calling convention to
1704 disambiguate both ABIs and allow for backward compatibility support
1705 (selected with CONFIG_OABI_COMPAT).
1707 To use this you need GCC version 4.0.0 or later.
1710 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1711 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1714 This option preserves the old syscall interface along with the
1715 new (ARM EABI) one. It also provides a compatibility layer to
1716 intercept syscalls that have structure arguments which layout
1717 in memory differs between the legacy ABI and the new ARM EABI
1718 (only for non "thumb" binaries). This option adds a tiny
1719 overhead to all syscalls and produces a slightly larger kernel.
1720 If you know you'll be using only pure EABI user space then you
1721 can say N here. If this option is not selected and you attempt
1722 to execute a legacy ABI binary then the result will be
1723 UNPREDICTABLE (in fact it can be predicted that it won't work
1724 at all). If in doubt say Y.
1726 config ARCH_HAS_HOLES_MEMORYMODEL
1729 config ARCH_SPARSEMEM_ENABLE
1732 config ARCH_SPARSEMEM_DEFAULT
1733 def_bool ARCH_SPARSEMEM_ENABLE
1735 config ARCH_SELECT_MEMORY_MODEL
1736 def_bool ARCH_SPARSEMEM_ENABLE
1738 config HAVE_ARCH_PFN_VALID
1739 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1742 bool "High Memory Support"
1745 The address space of ARM processors is only 4 Gigabytes large
1746 and it has to accommodate user address space, kernel address
1747 space as well as some memory mapped IO. That means that, if you
1748 have a large amount of physical memory and/or IO, not all of the
1749 memory can be "permanently mapped" by the kernel. The physical
1750 memory that is not permanently mapped is called "high memory".
1752 Depending on the selected kernel/user memory split, minimum
1753 vmalloc space and actual amount of RAM, you may not need this
1754 option which should result in a slightly faster kernel.
1759 bool "Allocate 2nd-level pagetables from highmem"
1762 config HW_PERF_EVENTS
1763 bool "Enable hardware performance counter support for perf events"
1764 depends on PERF_EVENTS
1767 Enable hardware performance counter support for perf events. If
1768 disabled, perf events will use software events only.
1772 config FORCE_MAX_ZONEORDER
1773 int "Maximum zone order" if ARCH_SHMOBILE
1774 range 11 64 if ARCH_SHMOBILE
1775 default "12" if SOC_AM33XX
1776 default "9" if SA1111
1779 The kernel memory allocator divides physically contiguous memory
1780 blocks into "zones", where each zone is a power of two number of
1781 pages. This option selects the largest power of two that the kernel
1782 keeps in the memory allocator. If you need to allocate very large
1783 blocks of physically contiguous memory, then you may need to
1784 increase this value.
1786 This config option is actually maximum order plus one. For example,
1787 a value of 11 means that the largest free memory block is 2^10 pages.
1789 config ALIGNMENT_TRAP
1791 depends on CPU_CP15_MMU
1792 default y if !ARCH_EBSA110
1793 select HAVE_PROC_CPU if PROC_FS
1795 ARM processors cannot fetch/store information which is not
1796 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1797 address divisible by 4. On 32-bit ARM processors, these non-aligned
1798 fetch/store instructions will be emulated in software if you say
1799 here, which has a severe performance impact. This is necessary for
1800 correct operation of some network protocols. With an IP-only
1801 configuration it is safe to say N, otherwise say Y.
1803 config UACCESS_WITH_MEMCPY
1804 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1806 default y if CPU_FEROCEON
1808 Implement faster copy_to_user and clear_user methods for CPU
1809 cores where a 8-word STM instruction give significantly higher
1810 memory write throughput than a sequence of individual 32bit stores.
1812 A possible side effect is a slight increase in scheduling latency
1813 between threads sharing the same address space if they invoke
1814 such copy operations with large buffers.
1816 However, if the CPU data cache is using a write-allocate mode,
1817 this option is unlikely to provide any performance gain.
1821 prompt "Enable seccomp to safely compute untrusted bytecode"
1823 This kernel feature is useful for number crunching applications
1824 that may need to compute untrusted bytecode during their
1825 execution. By using pipes or other transports made available to
1826 the process as file descriptors supporting the read/write
1827 syscalls, it's possible to isolate those applications in
1828 their own address space using seccomp. Once seccomp is
1829 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1830 and the task is only allowed to execute a few safe syscalls
1831 defined by each seccomp mode.
1833 config CC_STACKPROTECTOR
1834 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1835 depends on EXPERIMENTAL
1837 This option turns on the -fstack-protector GCC feature. This
1838 feature puts, at the beginning of functions, a canary value on
1839 the stack just before the return address, and validates
1840 the value just before actually returning. Stack based buffer
1841 overflows (that need to overwrite this return address) now also
1842 overwrite the canary, which gets detected and the attack is then
1843 neutralized via a kernel panic.
1844 This feature requires gcc version 4.2 or above.
1851 bool "Xen guest support on ARM (EXPERIMENTAL)"
1852 depends on EXPERIMENTAL && ARM && OF
1853 depends on CPU_V7 && !CPU_V6
1855 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1862 bool "Flattened Device Tree support"
1865 select OF_EARLY_FLATTREE
1867 Include support for flattened device tree machine descriptions.
1870 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1873 This is the traditional way of passing data to the kernel at boot
1874 time. If you are solely relying on the flattened device tree (or
1875 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1876 to remove ATAGS support from your kernel binary. If unsure,
1879 config DEPRECATED_PARAM_STRUCT
1880 bool "Provide old way to pass kernel parameters"
1883 This was deprecated in 2001 and announced to live on for 5 years.
1884 Some old boot loaders still use this way.
1886 # Compressed boot loader in ROM. Yes, we really want to ask about
1887 # TEXT and BSS so we preserve their values in the config files.
1888 config ZBOOT_ROM_TEXT
1889 hex "Compressed ROM boot loader base address"
1892 The physical address at which the ROM-able zImage is to be
1893 placed in the target. Platforms which normally make use of
1894 ROM-able zImage formats normally set this to a suitable
1895 value in their defconfig file.
1897 If ZBOOT_ROM is not enabled, this has no effect.
1899 config ZBOOT_ROM_BSS
1900 hex "Compressed ROM boot loader BSS address"
1903 The base address of an area of read/write memory in the target
1904 for the ROM-able zImage which must be available while the
1905 decompressor is running. It must be large enough to hold the
1906 entire decompressed kernel plus an additional 128 KiB.
1907 Platforms which normally make use of ROM-able zImage formats
1908 normally set this to a suitable value in their defconfig file.
1910 If ZBOOT_ROM is not enabled, this has no effect.
1913 bool "Compressed boot loader in ROM/flash"
1914 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1916 Say Y here if you intend to execute your compressed kernel image
1917 (zImage) directly from ROM or flash. If unsure, say N.
1920 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1921 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1922 default ZBOOT_ROM_NONE
1924 Include experimental SD/MMC loading code in the ROM-able zImage.
1925 With this enabled it is possible to write the ROM-able zImage
1926 kernel image to an MMC or SD card and boot the kernel straight
1927 from the reset vector. At reset the processor Mask ROM will load
1928 the first part of the ROM-able zImage which in turn loads the
1929 rest the kernel image to RAM.
1931 config ZBOOT_ROM_NONE
1932 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1934 Do not load image from SD or MMC
1936 config ZBOOT_ROM_MMCIF
1937 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1939 Load image from MMCIF hardware block.
1941 config ZBOOT_ROM_SH_MOBILE_SDHI
1942 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1944 Load image from SDHI hardware block
1948 config ARM_APPENDED_DTB
1949 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1950 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1952 With this option, the boot code will look for a device tree binary
1953 (DTB) appended to zImage
1954 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1956 This is meant as a backward compatibility convenience for those
1957 systems with a bootloader that can't be upgraded to accommodate
1958 the documented boot protocol using a device tree.
1960 Beware that there is very little in terms of protection against
1961 this option being confused by leftover garbage in memory that might
1962 look like a DTB header after a reboot if no actual DTB is appended
1963 to zImage. Do not leave this option active in a production kernel
1964 if you don't intend to always append a DTB. Proper passing of the
1965 location into r2 of a bootloader provided DTB is always preferable
1968 config ARM_ATAG_DTB_COMPAT
1969 bool "Supplement the appended DTB with traditional ATAG information"
1970 depends on ARM_APPENDED_DTB
1972 Some old bootloaders can't be updated to a DTB capable one, yet
1973 they provide ATAGs with memory configuration, the ramdisk address,
1974 the kernel cmdline string, etc. Such information is dynamically
1975 provided by the bootloader and can't always be stored in a static
1976 DTB. To allow a device tree enabled kernel to be used with such
1977 bootloaders, this option allows zImage to extract the information
1978 from the ATAG list and store it at run time into the appended DTB.
1981 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1982 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1985 bool "Use bootloader kernel arguments if available"
1987 Uses the command-line options passed by the boot loader instead of
1988 the device tree bootargs property. If the boot loader doesn't provide
1989 any, the device tree bootargs property will be used.
1991 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1992 bool "Extend with bootloader kernel arguments"
1994 The command-line arguments provided by the boot loader will be
1995 appended to the the device tree bootargs property.
2000 string "Default kernel command string"
2003 On some architectures (EBSA110 and CATS), there is currently no way
2004 for the boot loader to pass arguments to the kernel. For these
2005 architectures, you should supply some command-line options at build
2006 time by entering them here. As a minimum, you should specify the
2007 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2010 prompt "Kernel command line type" if CMDLINE != ""
2011 default CMDLINE_FROM_BOOTLOADER
2014 config CMDLINE_FROM_BOOTLOADER
2015 bool "Use bootloader kernel arguments if available"
2017 Uses the command-line options passed by the boot loader. If
2018 the boot loader doesn't provide any, the default kernel command
2019 string provided in CMDLINE will be used.
2021 config CMDLINE_EXTEND
2022 bool "Extend bootloader kernel arguments"
2024 The command-line arguments provided by the boot loader will be
2025 appended to the default kernel command string.
2027 config CMDLINE_FORCE
2028 bool "Always use the default kernel command string"
2030 Always use the default kernel command string, even if the boot
2031 loader passes other arguments to the kernel.
2032 This is useful if you cannot or don't want to change the
2033 command-line options your boot loader passes to the kernel.
2037 bool "Kernel Execute-In-Place from ROM"
2038 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2040 Execute-In-Place allows the kernel to run from non-volatile storage
2041 directly addressable by the CPU, such as NOR flash. This saves RAM
2042 space since the text section of the kernel is not loaded from flash
2043 to RAM. Read-write sections, such as the data section and stack,
2044 are still copied to RAM. The XIP kernel is not compressed since
2045 it has to run directly from flash, so it will take more space to
2046 store it. The flash address used to link the kernel object files,
2047 and for storing it, is configuration dependent. Therefore, if you
2048 say Y here, you must know the proper physical address where to
2049 store the kernel image depending on your own flash memory usage.
2051 Also note that the make target becomes "make xipImage" rather than
2052 "make zImage" or "make Image". The final kernel binary to put in
2053 ROM memory will be arch/arm/boot/xipImage.
2057 config XIP_PHYS_ADDR
2058 hex "XIP Kernel Physical Location"
2059 depends on XIP_KERNEL
2060 default "0x00080000"
2062 This is the physical address in your flash memory the kernel will
2063 be linked for and stored to. This address is dependent on your
2067 bool "Kexec system call (EXPERIMENTAL)"
2068 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2070 kexec is a system call that implements the ability to shutdown your
2071 current kernel, and to start another kernel. It is like a reboot
2072 but it is independent of the system firmware. And like a reboot
2073 you can start any kernel with it, not just Linux.
2075 It is an ongoing process to be certain the hardware in a machine
2076 is properly shutdown, so do not be surprised if this code does not
2077 initially work for you. It may help to enable device hotplugging
2081 bool "Export atags in procfs"
2082 depends on ATAGS && KEXEC
2085 Should the atags used to boot the kernel be exported in an "atags"
2086 file in procfs. Useful with kexec.
2089 bool "Build kdump crash kernel (EXPERIMENTAL)"
2090 depends on EXPERIMENTAL
2092 Generate crash dump after being started by kexec. This should
2093 be normally only set in special crash dump kernels which are
2094 loaded in the main kernel with kexec-tools into a specially
2095 reserved region and then later executed after a crash by
2096 kdump/kexec. The crash dump kernel must be compiled to a
2097 memory address not used by the main kernel
2099 For more details see Documentation/kdump/kdump.txt
2101 config AUTO_ZRELADDR
2102 bool "Auto calculation of the decompressed kernel image address"
2103 depends on !ZBOOT_ROM && !ARCH_U300
2105 ZRELADDR is the physical address where the decompressed kernel
2106 image will be placed. If AUTO_ZRELADDR is selected, the address
2107 will be determined at run-time by masking the current IP with
2108 0xf8000000. This assumes the zImage being placed in the first 128MB
2109 from start of memory.
2113 menu "CPU Power Management"
2117 source "drivers/cpufreq/Kconfig"
2120 tristate "CPUfreq driver for i.MX CPUs"
2121 depends on ARCH_MXC && CPU_FREQ
2122 select CPU_FREQ_TABLE
2124 This enables the CPUfreq driver for i.MX CPUs.
2126 config CPU_FREQ_SA1100
2129 config CPU_FREQ_SA1110
2132 config CPU_FREQ_INTEGRATOR
2133 tristate "CPUfreq driver for ARM Integrator CPUs"
2134 depends on ARCH_INTEGRATOR && CPU_FREQ
2137 This enables the CPUfreq driver for ARM Integrator CPUs.
2139 For details, take a look at <file:Documentation/cpu-freq>.
2145 depends on CPU_FREQ && ARCH_PXA && PXA25x
2147 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2148 select CPU_FREQ_TABLE
2153 Internal configuration node for common cpufreq on Samsung SoC
2155 config CPU_FREQ_S3C24XX
2156 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2157 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2160 This enables the CPUfreq driver for the Samsung S3C24XX family
2163 For details, take a look at <file:Documentation/cpu-freq>.
2167 config CPU_FREQ_S3C24XX_PLL
2168 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2169 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2171 Compile in support for changing the PLL frequency from the
2172 S3C24XX series CPUfreq driver. The PLL takes time to settle
2173 after a frequency change, so by default it is not enabled.
2175 This also means that the PLL tables for the selected CPU(s) will
2176 be built which may increase the size of the kernel image.
2178 config CPU_FREQ_S3C24XX_DEBUG
2179 bool "Debug CPUfreq Samsung driver core"
2180 depends on CPU_FREQ_S3C24XX
2182 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2184 config CPU_FREQ_S3C24XX_IODEBUG
2185 bool "Debug CPUfreq Samsung driver IO timing"
2186 depends on CPU_FREQ_S3C24XX
2188 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2190 config CPU_FREQ_S3C24XX_DEBUGFS
2191 bool "Export debugfs for CPUFreq"
2192 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2194 Export status information via debugfs.
2198 source "drivers/cpuidle/Kconfig"
2202 menu "Floating point emulation"
2204 comment "At least one emulation must be selected"
2207 bool "NWFPE math emulation"
2208 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2210 Say Y to include the NWFPE floating point emulator in the kernel.
2211 This is necessary to run most binaries. Linux does not currently
2212 support floating point hardware so you need to say Y here even if
2213 your machine has an FPA or floating point co-processor podule.
2215 You may say N here if you are going to load the Acorn FPEmulator
2216 early in the bootup.
2219 bool "Support extended precision"
2220 depends on FPE_NWFPE
2222 Say Y to include 80-bit support in the kernel floating-point
2223 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2224 Note that gcc does not generate 80-bit operations by default,
2225 so in most cases this option only enlarges the size of the
2226 floating point emulator without any good reason.
2228 You almost surely want to say N here.
2231 bool "FastFPE math emulation (EXPERIMENTAL)"
2232 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2234 Say Y here to include the FAST floating point emulator in the kernel.
2235 This is an experimental much faster emulator which now also has full
2236 precision for the mantissa. It does not support any exceptions.
2237 It is very simple, and approximately 3-6 times faster than NWFPE.
2239 It should be sufficient for most programs. It may be not suitable
2240 for scientific calculations, but you have to check this for yourself.
2241 If you do not feel you need a faster FP emulation you should better
2245 bool "VFP-format floating point maths"
2246 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2248 Say Y to include VFP support code in the kernel. This is needed
2249 if your hardware includes a VFP unit.
2251 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2252 release notes and additional status information.
2254 Say N if your target does not have VFP hardware.
2262 bool "Advanced SIMD (NEON) Extension support"
2263 depends on VFPv3 && CPU_V7
2265 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2270 menu "Userspace binary formats"
2272 source "fs/Kconfig.binfmt"
2275 tristate "RISC OS personality"
2278 Say Y here to include the kernel code necessary if you want to run
2279 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2280 experimental; if this sounds frightening, say N and sleep in peace.
2281 You can also say M here to compile this support as a module (which
2282 will be called arthur).
2286 menu "Power management options"
2288 source "kernel/power/Kconfig"
2290 config ARCH_SUSPEND_POSSIBLE
2291 depends on !ARCH_S5PC100
2292 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2293 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2296 config ARM_CPU_SUSPEND
2301 source "net/Kconfig"
2303 source "drivers/Kconfig"
2307 source "arch/arm/Kconfig.debug"
2309 source "security/Kconfig"
2311 source "crypto/Kconfig"
2313 source "lib/Kconfig"