5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
72 select GENERIC_ALLOCATOR
83 The Extended Industry Standard Architecture (EISA) bus was
84 developed as an open alternative to the IBM MicroChannel bus.
86 The EISA bus provided some of the features of the IBM MicroChannel
87 bus while maintaining backward compatibility with cards made for
88 the older ISA bus. The EISA bus saw limited use between 1988 and
89 1995 when it was made obsolete by the PCI bus.
91 Say Y here if you are building a kernel for an EISA-based machine.
101 MicroChannel Architecture is found in some IBM PS/2 machines and
102 laptops. It is a bus system similar to PCI or ISA. See
103 <file:Documentation/mca.txt> (and especially the web page given
104 there) before attempting to build an MCA bus kernel.
106 config STACKTRACE_SUPPORT
110 config HAVE_LATENCYTOP_SUPPORT
115 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
123 config HARDIRQS_SW_RESEND
127 config GENERIC_IRQ_PROBE
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 The base address of exception vectors.
193 config ARM_PATCH_PHYS_VIRT
194 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
195 depends on EXPERIMENTAL
196 depends on !XIP_KERNEL && MMU
197 depends on !ARCH_REALVIEW || !SPARSEMEM
199 Patch phys-to-virt translation functions at runtime according to
200 the position of the kernel in system memory.
202 This can only be used with non-XIP with MMU kernels where
203 the base of physical memory is at a 16MB boundary.
205 config ARM_PATCH_PHYS_VIRT_16BIT
207 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
209 source "init/Kconfig"
211 source "kernel/Kconfig.freezer"
216 bool "MMU-based Paged Memory Management Support"
219 Select if you want MMU-based virtualised addressing space
220 support by paged memory management. If unsure, say 'Y'.
223 # The "ARM system type" choice list is ordered alphabetically by option
224 # text. Please add new entries in the option alphabetic order.
227 prompt "ARM system type"
228 default ARCH_VERSATILE
230 config ARCH_INTEGRATOR
231 bool "ARM Ltd. Integrator family"
233 select ARCH_HAS_CPUFREQ
236 select GENERIC_CLOCKEVENTS
237 select PLAT_VERSATILE
239 Support for ARM's Integrator platform.
242 bool "ARM Ltd. RealView family"
245 select HAVE_SCHED_CLOCK
247 select GENERIC_CLOCKEVENTS
248 select ARCH_WANT_OPTIONAL_GPIOLIB
249 select PLAT_VERSATILE
250 select ARM_TIMER_SP804
251 select GPIO_PL061 if GPIOLIB
253 This enables support for ARM Ltd RealView boards.
255 config ARCH_VERSATILE
256 bool "ARM Ltd. Versatile family"
260 select HAVE_SCHED_CLOCK
262 select GENERIC_CLOCKEVENTS
263 select ARCH_WANT_OPTIONAL_GPIOLIB
264 select PLAT_VERSATILE
265 select ARM_TIMER_SP804
267 This enables support for ARM Ltd Versatile board.
270 bool "ARM Ltd. Versatile Express family"
271 select ARCH_WANT_OPTIONAL_GPIOLIB
273 select ARM_TIMER_SP804
275 select GENERIC_CLOCKEVENTS
277 select HAVE_SCHED_CLOCK
279 select PLAT_VERSATILE
281 This enables support for the ARM Ltd Versatile Express boards.
285 select ARCH_REQUIRE_GPIOLIB
288 This enables support for systems based on the Atmel AT91RM9200,
289 AT91SAM9 and AT91CAP9 processors.
292 bool "Broadcom BCMRING"
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 Support for Broadcom's BCMRing platform.
303 bool "Cirrus Logic CLPS711x/EP721x-based"
305 select ARCH_USES_GETTIMEOFFSET
307 Support for Cirrus Logic 711x/721x based boards.
310 bool "Cavium Networks CNS3XXX family"
312 select GENERIC_CLOCKEVENTS
314 select MIGHT_HAVE_PCI
315 select PCI_DOMAINS if PCI
317 Support for Cavium Networks CNS3XXX platform.
320 bool "Cortina Systems Gemini"
322 select ARCH_REQUIRE_GPIOLIB
323 select ARCH_USES_GETTIMEOFFSET
325 Support for the Cortina Systems Gemini family SoCs
332 select ARCH_USES_GETTIMEOFFSET
334 This is an evaluation board for the StrongARM processor available
335 from Digital. It has limited hardware on-board, including an
336 Ethernet interface, two PCMCIA sockets, two serial ports and a
345 select ARCH_REQUIRE_GPIOLIB
346 select ARCH_HAS_HOLES_MEMORYMODEL
347 select ARCH_USES_GETTIMEOFFSET
349 This enables support for the Cirrus EP93xx series of CPUs.
351 config ARCH_FOOTBRIDGE
355 select GENERIC_CLOCKEVENTS
357 Support for systems based on the DC21285 companion chip
358 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
361 bool "Freescale MXC/iMX-based"
362 select GENERIC_CLOCKEVENTS
363 select ARCH_REQUIRE_GPIOLIB
366 Support for Freescale MXC/iMX-based family of processors
369 bool "Freescale MXS-based"
370 select GENERIC_CLOCKEVENTS
371 select ARCH_REQUIRE_GPIOLIB
374 Support for Freescale MXS-based family of processors
377 bool "Freescale STMP3xxx"
380 select ARCH_REQUIRE_GPIOLIB
381 select GENERIC_CLOCKEVENTS
382 select USB_ARCH_HAS_EHCI
384 Support for systems based on the Freescale 3xxx CPUs.
387 bool "Hilscher NetX based"
390 select GENERIC_CLOCKEVENTS
392 This enables support for systems based on the Hilscher NetX Soc
395 bool "Hynix HMS720x-based"
398 select ARCH_USES_GETTIMEOFFSET
400 This enables support for systems based on the Hynix HMS720x
408 select ARCH_SUPPORTS_MSI
411 Support for Intel's IOP13XX (XScale) family of processors.
419 select ARCH_REQUIRE_GPIOLIB
421 Support for Intel's 80219 and IOP32X (XScale) family of
430 select ARCH_REQUIRE_GPIOLIB
432 Support for Intel's IOP33X (XScale) family of processors.
439 select ARCH_USES_GETTIMEOFFSET
441 Support for Intel's IXP23xx (XScale) family of processors.
444 bool "IXP2400/2800-based"
448 select ARCH_USES_GETTIMEOFFSET
450 Support for Intel's IXP2400/2800 (XScale) family of processors.
457 select GENERIC_CLOCKEVENTS
458 select HAVE_SCHED_CLOCK
459 select MIGHT_HAVE_PCI
460 select DMABOUNCE if PCI
462 Support for Intel's IXP4XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
469 select GENERIC_CLOCKEVENTS
472 Support for the Marvell Dove SoC 88AP510
475 bool "Marvell Kirkwood"
478 select ARCH_REQUIRE_GPIOLIB
479 select GENERIC_CLOCKEVENTS
482 Support for the following Marvell Kirkwood series SoCs:
483 88F6180, 88F6192 and 88F6281.
486 bool "Marvell Loki (88RC8480)"
488 select GENERIC_CLOCKEVENTS
491 Support for the Marvell Loki (88RC8480) SoC.
496 select ARCH_REQUIRE_GPIOLIB
499 select USB_ARCH_HAS_OHCI
502 select GENERIC_CLOCKEVENTS
504 Support for the NXP LPC32XX family of processors
507 bool "Marvell MV78xx0"
510 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
514 Support for the following Marvell MV78xx0 series SoCs:
522 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
526 Support for the following Marvell Orion 5x series SoCs:
527 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
528 Orion-2 (5281), Orion-1-90 (6183).
531 bool "Marvell PXA168/910/MMP2"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
536 select HAVE_SCHED_CLOCK
541 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
544 bool "Micrel/Kendin KS8695"
546 select ARCH_REQUIRE_GPIOLIB
547 select ARCH_USES_GETTIMEOFFSET
549 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
550 System-on-Chip devices.
553 bool "NetSilicon NS9xxx"
556 select GENERIC_CLOCKEVENTS
559 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
562 <http://www.digi.com/products/microprocessors/index.jsp>
565 bool "Nuvoton W90X900 CPU"
567 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
571 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
572 At present, the w90x900 has been renamed nuc900, regarding
573 the ARM series product line, you can login the following
574 link address to know more.
576 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
577 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
580 bool "Nuvoton NUC93X CPU"
584 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
585 low-power and high performance MPEG-4/JPEG multimedia controller chip.
591 select GENERIC_CLOCKEVENTS
594 select HAVE_SCHED_CLOCK
595 select ARCH_HAS_BARRIERS if CACHE_L2X0
596 select ARCH_HAS_CPUFREQ
598 This enables support for NVIDIA Tegra based systems (Tegra APX,
599 Tegra 6xx and Tegra 2 series).
602 bool "Philips Nexperia PNX4008 Mobile"
605 select ARCH_USES_GETTIMEOFFSET
607 This enables support for Philips PNX4008 mobile platform.
610 bool "PXA2xx/PXA3xx-based"
613 select ARCH_HAS_CPUFREQ
615 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
617 select HAVE_SCHED_CLOCK
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
627 select GENERIC_CLOCKEVENTS
628 select ARCH_REQUIRE_GPIOLIB
630 Support for Qualcomm MSM/QSD based systems. This runs on the
631 apps processor of the MSM/QSD and depends on a shared memory
632 interface to the modem processor which runs the baseband
633 stack and controls some vital subsystems
634 (clock and power control, etc).
637 bool "Renesas SH-Mobile / R-Mobile"
640 select GENERIC_CLOCKEVENTS
643 select MULTI_IRQ_HANDLER
645 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
652 select ARCH_MAY_HAVE_PC_FDC
653 select HAVE_PATA_PLATFORM
656 select ARCH_SPARSEMEM_ENABLE
657 select ARCH_USES_GETTIMEOFFSET
659 On the Acorn Risc-PC, Linux can support the internal IDE disk and
660 CD-ROM interface, serial and parallel port, and the floppy drive.
666 select ARCH_SPARSEMEM_ENABLE
668 select ARCH_HAS_CPUFREQ
670 select GENERIC_CLOCKEVENTS
672 select HAVE_SCHED_CLOCK
674 select ARCH_REQUIRE_GPIOLIB
676 Support for StrongARM 11x0 based boards.
679 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
681 select ARCH_HAS_CPUFREQ
683 select ARCH_USES_GETTIMEOFFSET
684 select HAVE_S3C2410_I2C if I2C
686 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
687 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
688 the Samsung SMDK2410 development board (and derivatives).
690 Note, the S3C2416 and the S3C2450 are so close that they even share
691 the same SoC ID code. This means that there is no seperate machine
692 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
695 bool "Samsung S3C64XX"
701 select ARCH_USES_GETTIMEOFFSET
702 select ARCH_HAS_CPUFREQ
703 select ARCH_REQUIRE_GPIOLIB
704 select SAMSUNG_CLKSRC
705 select SAMSUNG_IRQ_VIC_TIMER
706 select SAMSUNG_IRQ_UART
707 select S3C_GPIO_TRACK
708 select S3C_GPIO_PULL_UPDOWN
709 select S3C_GPIO_CFG_S3C24XX
710 select S3C_GPIO_CFG_S3C64XX
712 select USB_ARCH_HAS_OHCI
713 select SAMSUNG_GPIOLIB_4BIT
714 select HAVE_S3C2410_I2C if I2C
715 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 Samsung S3C64XX series based systems
720 bool "Samsung S5P6440 S5P6450"
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select GENERIC_CLOCKEVENTS
726 select HAVE_SCHED_CLOCK
727 select HAVE_S3C2410_I2C if I2C
728 select HAVE_S3C_RTC if RTC_CLASS
730 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
734 bool "Samsung S5P6442"
738 select ARCH_USES_GETTIMEOFFSET
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
741 Samsung S5P6442 CPU based systems
744 bool "Samsung S5PC100"
748 select ARM_L1_CACHE_SHIFT_6
749 select ARCH_USES_GETTIMEOFFSET
750 select HAVE_S3C2410_I2C if I2C
751 select HAVE_S3C_RTC if RTC_CLASS
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754 Samsung S5PC100 series based systems
757 bool "Samsung S5PV210/S5PC110"
759 select ARCH_SPARSEMEM_ENABLE
762 select ARM_L1_CACHE_SHIFT_6
763 select ARCH_HAS_CPUFREQ
764 select GENERIC_CLOCKEVENTS
765 select HAVE_SCHED_CLOCK
766 select HAVE_S3C2410_I2C if I2C
767 select HAVE_S3C_RTC if RTC_CLASS
768 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 Samsung S5PV210/S5PC110 series based systems
773 bool "Samsung EXYNOS4"
775 select ARCH_SPARSEMEM_ENABLE
778 select ARCH_HAS_CPUFREQ
779 select GENERIC_CLOCKEVENTS
780 select HAVE_S3C_RTC if RTC_CLASS
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 Samsung EXYNOS4 series based systems
793 select ARCH_USES_GETTIMEOFFSET
795 Support for the StrongARM based Digital DNARD machine, also known
796 as "Shark" (<http://www.shark-linux.de/shark.html>).
799 bool "Telechips TCC ARM926-based systems"
803 select GENERIC_CLOCKEVENTS
805 Support for Telechips TCC ARM926-based systems.
808 bool "ST-Ericsson U300 Series"
811 select HAVE_SCHED_CLOCK
815 select GENERIC_CLOCKEVENTS
819 Support for ST-Ericsson U300 series mobile platforms.
822 bool "ST-Ericsson U8500 Series"
825 select GENERIC_CLOCKEVENTS
827 select ARCH_REQUIRE_GPIOLIB
828 select ARCH_HAS_CPUFREQ
830 Support for ST-Ericsson's Ux500 architecture
833 bool "STMicroelectronics Nomadik"
838 select GENERIC_CLOCKEVENTS
839 select ARCH_REQUIRE_GPIOLIB
841 Support for the Nomadik platform by ST-Ericsson
845 select GENERIC_CLOCKEVENTS
846 select ARCH_REQUIRE_GPIOLIB
850 select GENERIC_ALLOCATOR
851 select ARCH_HAS_HOLES_MEMORYMODEL
853 Support for TI's DaVinci platform.
858 select ARCH_REQUIRE_GPIOLIB
859 select ARCH_HAS_CPUFREQ
860 select GENERIC_CLOCKEVENTS
861 select HAVE_SCHED_CLOCK
862 select ARCH_HAS_HOLES_MEMORYMODEL
864 Support for TI's OMAP platform (OMAP1/2/3/4).
869 select ARCH_REQUIRE_GPIOLIB
871 select GENERIC_CLOCKEVENTS
874 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
877 bool "VIA/WonderMedia 85xx"
880 select ARCH_HAS_CPUFREQ
881 select GENERIC_CLOCKEVENTS
882 select ARCH_REQUIRE_GPIOLIB
885 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
889 # This is sorted alphabetically by mach-* pathname. However, plat-*
890 # Kconfigs may be included either alphabetically (according to the
891 # plat- suffix) or along side the corresponding mach-* source.
893 source "arch/arm/mach-at91/Kconfig"
895 source "arch/arm/mach-bcmring/Kconfig"
897 source "arch/arm/mach-clps711x/Kconfig"
899 source "arch/arm/mach-cns3xxx/Kconfig"
901 source "arch/arm/mach-davinci/Kconfig"
903 source "arch/arm/mach-dove/Kconfig"
905 source "arch/arm/mach-ep93xx/Kconfig"
907 source "arch/arm/mach-footbridge/Kconfig"
909 source "arch/arm/mach-gemini/Kconfig"
911 source "arch/arm/mach-h720x/Kconfig"
913 source "arch/arm/mach-integrator/Kconfig"
915 source "arch/arm/mach-iop32x/Kconfig"
917 source "arch/arm/mach-iop33x/Kconfig"
919 source "arch/arm/mach-iop13xx/Kconfig"
921 source "arch/arm/mach-ixp4xx/Kconfig"
923 source "arch/arm/mach-ixp2000/Kconfig"
925 source "arch/arm/mach-ixp23xx/Kconfig"
927 source "arch/arm/mach-kirkwood/Kconfig"
929 source "arch/arm/mach-ks8695/Kconfig"
931 source "arch/arm/mach-loki/Kconfig"
933 source "arch/arm/mach-lpc32xx/Kconfig"
935 source "arch/arm/mach-msm/Kconfig"
937 source "arch/arm/mach-mv78xx0/Kconfig"
939 source "arch/arm/plat-mxc/Kconfig"
941 source "arch/arm/mach-mxs/Kconfig"
943 source "arch/arm/mach-netx/Kconfig"
945 source "arch/arm/mach-nomadik/Kconfig"
946 source "arch/arm/plat-nomadik/Kconfig"
948 source "arch/arm/mach-ns9xxx/Kconfig"
950 source "arch/arm/mach-nuc93x/Kconfig"
952 source "arch/arm/plat-omap/Kconfig"
954 source "arch/arm/mach-omap1/Kconfig"
956 source "arch/arm/mach-omap2/Kconfig"
958 source "arch/arm/mach-orion5x/Kconfig"
960 source "arch/arm/mach-pxa/Kconfig"
961 source "arch/arm/plat-pxa/Kconfig"
963 source "arch/arm/mach-mmp/Kconfig"
965 source "arch/arm/mach-realview/Kconfig"
967 source "arch/arm/mach-sa1100/Kconfig"
969 source "arch/arm/plat-samsung/Kconfig"
970 source "arch/arm/plat-s3c24xx/Kconfig"
971 source "arch/arm/plat-s5p/Kconfig"
973 source "arch/arm/plat-spear/Kconfig"
975 source "arch/arm/plat-tcc/Kconfig"
978 source "arch/arm/mach-s3c2400/Kconfig"
979 source "arch/arm/mach-s3c2410/Kconfig"
980 source "arch/arm/mach-s3c2412/Kconfig"
981 source "arch/arm/mach-s3c2416/Kconfig"
982 source "arch/arm/mach-s3c2440/Kconfig"
983 source "arch/arm/mach-s3c2443/Kconfig"
987 source "arch/arm/mach-s3c64xx/Kconfig"
990 source "arch/arm/mach-s5p64x0/Kconfig"
992 source "arch/arm/mach-s5p6442/Kconfig"
994 source "arch/arm/mach-s5pc100/Kconfig"
996 source "arch/arm/mach-s5pv210/Kconfig"
998 source "arch/arm/mach-exynos4/Kconfig"
1000 source "arch/arm/mach-shmobile/Kconfig"
1002 source "arch/arm/plat-stmp3xxx/Kconfig"
1004 source "arch/arm/mach-tegra/Kconfig"
1006 source "arch/arm/mach-u300/Kconfig"
1008 source "arch/arm/mach-ux500/Kconfig"
1010 source "arch/arm/mach-versatile/Kconfig"
1012 source "arch/arm/mach-vexpress/Kconfig"
1014 source "arch/arm/mach-vt8500/Kconfig"
1016 source "arch/arm/mach-w90x900/Kconfig"
1018 # Definitions to make life easier
1024 select GENERIC_CLOCKEVENTS
1025 select HAVE_SCHED_CLOCK
1029 select HAVE_SCHED_CLOCK
1034 config PLAT_VERSATILE
1037 config ARM_TIMER_SP804
1040 source arch/arm/mm/Kconfig
1043 bool "Enable iWMMXt support"
1044 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1045 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1047 Enable support for iWMMXt context switching at run time if
1048 running on a CPU that supports it.
1050 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1053 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1057 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1058 (!ARCH_OMAP3 || OMAP3_EMU)
1062 config MULTI_IRQ_HANDLER
1065 Allow each machine to specify it's own IRQ handler at run time.
1068 source "arch/arm/Kconfig-nommu"
1071 config ARM_ERRATA_411920
1072 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1073 depends on CPU_V6 || CPU_V6K
1075 Invalidation of the Instruction Cache operation can
1076 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1077 It does not affect the MPCore. This option enables the ARM Ltd.
1078 recommended workaround.
1080 config ARM_ERRATA_430973
1081 bool "ARM errata: Stale prediction on replaced interworking branch"
1084 This option enables the workaround for the 430973 Cortex-A8
1085 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1086 interworking branch is replaced with another code sequence at the
1087 same virtual address, whether due to self-modifying code or virtual
1088 to physical address re-mapping, Cortex-A8 does not recover from the
1089 stale interworking branch prediction. This results in Cortex-A8
1090 executing the new code sequence in the incorrect ARM or Thumb state.
1091 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1092 and also flushes the branch target cache at every context switch.
1093 Note that setting specific bits in the ACTLR register may not be
1094 available in non-secure mode.
1096 config ARM_ERRATA_458693
1097 bool "ARM errata: Processor deadlock when a false hazard is created"
1100 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1101 erratum. For very specific sequences of memory operations, it is
1102 possible for a hazard condition intended for a cache line to instead
1103 be incorrectly associated with a different cache line. This false
1104 hazard might then cause a processor deadlock. The workaround enables
1105 the L1 caching of the NEON accesses and disables the PLD instruction
1106 in the ACTLR register. Note that setting specific bits in the ACTLR
1107 register may not be available in non-secure mode.
1109 config ARM_ERRATA_460075
1110 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1113 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1114 erratum. Any asynchronous access to the L2 cache may encounter a
1115 situation in which recent store transactions to the L2 cache are lost
1116 and overwritten with stale memory contents from external memory. The
1117 workaround disables the write-allocate mode for the L2 cache via the
1118 ACTLR register. Note that setting specific bits in the ACTLR register
1119 may not be available in non-secure mode.
1121 config ARM_ERRATA_742230
1122 bool "ARM errata: DMB operation may be faulty"
1123 depends on CPU_V7 && SMP
1125 This option enables the workaround for the 742230 Cortex-A9
1126 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1127 between two write operations may not ensure the correct visibility
1128 ordering of the two writes. This workaround sets a specific bit in
1129 the diagnostic register of the Cortex-A9 which causes the DMB
1130 instruction to behave as a DSB, ensuring the correct behaviour of
1133 config ARM_ERRATA_742231
1134 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1135 depends on CPU_V7 && SMP
1137 This option enables the workaround for the 742231 Cortex-A9
1138 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1139 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1140 accessing some data located in the same cache line, may get corrupted
1141 data due to bad handling of the address hazard when the line gets
1142 replaced from one of the CPUs at the same time as another CPU is
1143 accessing it. This workaround sets specific bits in the diagnostic
1144 register of the Cortex-A9 which reduces the linefill issuing
1145 capabilities of the processor.
1147 config PL310_ERRATA_588369
1148 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1149 depends on CACHE_L2X0
1151 The PL310 L2 cache controller implements three types of Clean &
1152 Invalidate maintenance operations: by Physical Address
1153 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1154 They are architecturally defined to behave as the execution of a
1155 clean operation followed immediately by an invalidate operation,
1156 both performing to the same memory location. This functionality
1157 is not correctly implemented in PL310 as clean lines are not
1158 invalidated as a result of these operations.
1160 config ARM_ERRATA_720789
1161 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1162 depends on CPU_V7 && SMP
1164 This option enables the workaround for the 720789 Cortex-A9 (prior to
1165 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1166 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1167 As a consequence of this erratum, some TLB entries which should be
1168 invalidated are not, resulting in an incoherency in the system page
1169 tables. The workaround changes the TLB flushing routines to invalidate
1170 entries regardless of the ASID.
1172 config PL310_ERRATA_727915
1173 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1174 depends on CACHE_L2X0
1176 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1177 operation (offset 0x7FC). This operation runs in background so that
1178 PL310 can handle normal accesses while it is in progress. Under very
1179 rare circumstances, due to this erratum, write data can be lost when
1180 PL310 treats a cacheable write transaction during a Clean &
1181 Invalidate by Way operation.
1183 config ARM_ERRATA_743622
1184 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1187 This option enables the workaround for the 743622 Cortex-A9
1188 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1189 optimisation in the Cortex-A9 Store Buffer may lead to data
1190 corruption. This workaround sets a specific bit in the diagnostic
1191 register of the Cortex-A9 which disables the Store Buffer
1192 optimisation, preventing the defect from occurring. This has no
1193 visible impact on the overall performance or power consumption of the
1196 config ARM_ERRATA_751472
1197 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1198 depends on CPU_V7 && SMP
1200 This option enables the workaround for the 751472 Cortex-A9 (prior
1201 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1202 completion of a following broadcasted operation if the second
1203 operation is received by a CPU before the ICIALLUIS has completed,
1204 potentially leading to corrupted entries in the cache or TLB.
1206 config ARM_ERRATA_753970
1207 bool "ARM errata: cache sync operation may be faulty"
1208 depends on CACHE_PL310
1210 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1212 Under some condition the effect of cache sync operation on
1213 the store buffer still remains when the operation completes.
1214 This means that the store buffer is always asked to drain and
1215 this prevents it from merging any further writes. The workaround
1216 is to replace the normal offset of cache sync operation (0x730)
1217 by another offset targeting an unmapped PL310 register 0x740.
1218 This has the same effect as the cache sync operation: store buffer
1219 drain and waiting for all buffers empty.
1221 config ARM_ERRATA_754322
1222 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1225 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1226 r3p*) erratum. A speculative memory access may cause a page table walk
1227 which starts prior to an ASID switch but completes afterwards. This
1228 can populate the micro-TLB with a stale entry which may be hit with
1229 the new ASID. This workaround places two dsb instructions in the mm
1230 switching code so that no page table walks can cross the ASID switch.
1232 config ARM_ERRATA_754327
1233 bool "ARM errata: no automatic Store Buffer drain"
1234 depends on CPU_V7 && SMP
1236 This option enables the workaround for the 754327 Cortex-A9 (prior to
1237 r2p0) erratum. The Store Buffer does not have any automatic draining
1238 mechanism and therefore a livelock may occur if an external agent
1239 continuously polls a memory location waiting to observe an update.
1240 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1241 written polling loops from denying visibility of updates to memory.
1245 source "arch/arm/common/Kconfig"
1255 Find out whether you have ISA slots on your motherboard. ISA is the
1256 name of a bus system, i.e. the way the CPU talks to the other stuff
1257 inside your box. Other bus systems are PCI, EISA, MicroChannel
1258 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1259 newer boards don't support it. If you have ISA, say Y, otherwise N.
1261 # Select ISA DMA controller support
1266 # Select ISA DMA interface
1271 bool "PCI support" if MIGHT_HAVE_PCI
1273 Find out whether you have a PCI motherboard. PCI is the name of a
1274 bus system, i.e. the way the CPU talks to the other stuff inside
1275 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1276 VESA. If you have PCI, say Y, otherwise N.
1282 config PCI_NANOENGINE
1283 bool "BSE nanoEngine PCI support"
1284 depends on SA1100_NANOENGINE
1286 Enable PCI on the BSE nanoEngine board.
1291 # Select the host bridge type
1292 config PCI_HOST_VIA82C505
1294 depends on PCI && ARCH_SHARK
1297 config PCI_HOST_ITE8152
1299 depends on PCI && MACH_ARMCORE
1303 source "drivers/pci/Kconfig"
1305 source "drivers/pcmcia/Kconfig"
1309 menu "Kernel Features"
1311 source "kernel/time/Kconfig"
1314 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1315 depends on EXPERIMENTAL
1316 depends on CPU_V6K || CPU_V7
1317 depends on GENERIC_CLOCKEVENTS
1318 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1319 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1320 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1321 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1322 select USE_GENERIC_SMP_HELPERS
1323 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1325 This enables support for systems with more than one CPU. If you have
1326 a system with only one CPU, like most personal computers, say N. If
1327 you have a system with more than one CPU, say Y.
1329 If you say N here, the kernel will run on single and multiprocessor
1330 machines, but will use only one CPU of a multiprocessor machine. If
1331 you say Y here, the kernel will run on many, but not all, single
1332 processor machines. On a single processor machine, the kernel will
1333 run faster if you say N here.
1335 See also <file:Documentation/i386/IO-APIC.txt>,
1336 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1337 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1339 If you don't know what to do here, say N.
1342 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1343 depends on EXPERIMENTAL
1344 depends on SMP && !XIP_KERNEL
1347 SMP kernels contain instructions which fail on non-SMP processors.
1348 Enabling this option allows the kernel to modify itself to make
1349 these instructions safe. Disabling it allows about 1K of space
1352 If you don't know what to do here, say Y.
1358 This option enables support for the ARM system coherency unit
1365 This options enables support for the ARM timer and watchdog unit
1368 prompt "Memory split"
1371 Select the desired split between kernel and user memory.
1373 If you are not absolutely sure what you are doing, leave this
1377 bool "3G/1G user/kernel split"
1379 bool "2G/2G user/kernel split"
1381 bool "1G/3G user/kernel split"
1386 default 0x40000000 if VMSPLIT_1G
1387 default 0x80000000 if VMSPLIT_2G
1391 int "Maximum number of CPUs (2-32)"
1397 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1398 depends on SMP && HOTPLUG && EXPERIMENTAL
1399 depends on !ARCH_MSM
1401 Say Y here to experiment with turning CPUs off and on. CPUs
1402 can be controlled through /sys/devices/system/cpu.
1405 bool "Use local timer interrupts"
1408 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1410 Enable support for local timers on SMP platforms, rather then the
1411 legacy IPI broadcast method. Local timers allows the system
1412 accounting to be spread across the timer interval, preventing a
1413 "thundering herd" at every timer tick.
1415 source kernel/Kconfig.preempt
1419 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1420 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1421 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1422 default AT91_TIMER_HZ if ARCH_AT91
1423 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1426 config THUMB2_KERNEL
1427 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1428 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1430 select ARM_ASM_UNIFIED
1432 By enabling this option, the kernel will be compiled in
1433 Thumb-2 mode. A compiler/assembler that understand the unified
1434 ARM-Thumb syntax is needed.
1438 config THUMB2_AVOID_R_ARM_THM_JUMP11
1439 bool "Work around buggy Thumb-2 short branch relocations in gas"
1440 depends on THUMB2_KERNEL && MODULES
1443 Various binutils versions can resolve Thumb-2 branches to
1444 locally-defined, preemptible global symbols as short-range "b.n"
1445 branch instructions.
1447 This is a problem, because there's no guarantee the final
1448 destination of the symbol, or any candidate locations for a
1449 trampoline, are within range of the branch. For this reason, the
1450 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1451 relocation in modules at all, and it makes little sense to add
1454 The symptom is that the kernel fails with an "unsupported
1455 relocation" error when loading some modules.
1457 Until fixed tools are available, passing
1458 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1459 code which hits this problem, at the cost of a bit of extra runtime
1460 stack usage in some cases.
1462 The problem is described in more detail at:
1463 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1465 Only Thumb-2 kernels are affected.
1467 Unless you are sure your tools don't have this problem, say Y.
1469 config ARM_ASM_UNIFIED
1473 bool "Use the ARM EABI to compile the kernel"
1475 This option allows for the kernel to be compiled using the latest
1476 ARM ABI (aka EABI). This is only useful if you are using a user
1477 space environment that is also compiled with EABI.
1479 Since there are major incompatibilities between the legacy ABI and
1480 EABI, especially with regard to structure member alignment, this
1481 option also changes the kernel syscall calling convention to
1482 disambiguate both ABIs and allow for backward compatibility support
1483 (selected with CONFIG_OABI_COMPAT).
1485 To use this you need GCC version 4.0.0 or later.
1488 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1489 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1492 This option preserves the old syscall interface along with the
1493 new (ARM EABI) one. It also provides a compatibility layer to
1494 intercept syscalls that have structure arguments which layout
1495 in memory differs between the legacy ABI and the new ARM EABI
1496 (only for non "thumb" binaries). This option adds a tiny
1497 overhead to all syscalls and produces a slightly larger kernel.
1498 If you know you'll be using only pure EABI user space then you
1499 can say N here. If this option is not selected and you attempt
1500 to execute a legacy ABI binary then the result will be
1501 UNPREDICTABLE (in fact it can be predicted that it won't work
1502 at all). If in doubt say Y.
1504 config ARCH_HAS_HOLES_MEMORYMODEL
1507 config ARCH_SPARSEMEM_ENABLE
1510 config ARCH_SPARSEMEM_DEFAULT
1511 def_bool ARCH_SPARSEMEM_ENABLE
1513 config ARCH_SELECT_MEMORY_MODEL
1514 def_bool ARCH_SPARSEMEM_ENABLE
1517 bool "High Memory Support (EXPERIMENTAL)"
1518 depends on MMU && EXPERIMENTAL
1520 The address space of ARM processors is only 4 Gigabytes large
1521 and it has to accommodate user address space, kernel address
1522 space as well as some memory mapped IO. That means that, if you
1523 have a large amount of physical memory and/or IO, not all of the
1524 memory can be "permanently mapped" by the kernel. The physical
1525 memory that is not permanently mapped is called "high memory".
1527 Depending on the selected kernel/user memory split, minimum
1528 vmalloc space and actual amount of RAM, you may not need this
1529 option which should result in a slightly faster kernel.
1534 bool "Allocate 2nd-level pagetables from highmem"
1536 depends on !OUTER_CACHE
1538 config HW_PERF_EVENTS
1539 bool "Enable hardware performance counter support for perf events"
1540 depends on PERF_EVENTS && CPU_HAS_PMU
1543 Enable hardware performance counter support for perf events. If
1544 disabled, perf events will use software events only.
1548 config FORCE_MAX_ZONEORDER
1549 int "Maximum zone order" if ARCH_SHMOBILE
1550 range 11 64 if ARCH_SHMOBILE
1551 default "9" if SA1111
1554 The kernel memory allocator divides physically contiguous memory
1555 blocks into "zones", where each zone is a power of two number of
1556 pages. This option selects the largest power of two that the kernel
1557 keeps in the memory allocator. If you need to allocate very large
1558 blocks of physically contiguous memory, then you may need to
1559 increase this value.
1561 This config option is actually maximum order plus one. For example,
1562 a value of 11 means that the largest free memory block is 2^10 pages.
1565 bool "Timer and CPU usage LEDs"
1566 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1567 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1568 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1569 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1570 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1571 ARCH_AT91 || ARCH_DAVINCI || \
1572 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1574 If you say Y here, the LEDs on your machine will be used
1575 to provide useful information about your current system status.
1577 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1578 be able to select which LEDs are active using the options below. If
1579 you are compiling a kernel for the EBSA-110 or the LART however, the
1580 red LED will simply flash regularly to indicate that the system is
1581 still functional. It is safe to say Y here if you have a CATS
1582 system, but the driver will do nothing.
1585 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1586 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1587 || MACH_OMAP_PERSEUS2
1589 depends on !GENERIC_CLOCKEVENTS
1590 default y if ARCH_EBSA110
1592 If you say Y here, one of the system LEDs (the green one on the
1593 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1594 will flash regularly to indicate that the system is still
1595 operational. This is mainly useful to kernel hackers who are
1596 debugging unstable kernels.
1598 The LART uses the same LED for both Timer LED and CPU usage LED
1599 functions. You may choose to use both, but the Timer LED function
1600 will overrule the CPU usage LED.
1603 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1605 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1606 || MACH_OMAP_PERSEUS2
1609 If you say Y here, the red LED will be used to give a good real
1610 time indication of CPU usage, by lighting whenever the idle task
1611 is not currently executing.
1613 The LART uses the same LED for both Timer LED and CPU usage LED
1614 functions. You may choose to use both, but the Timer LED function
1615 will overrule the CPU usage LED.
1617 config ALIGNMENT_TRAP
1619 depends on CPU_CP15_MMU
1620 default y if !ARCH_EBSA110
1621 select HAVE_PROC_CPU if PROC_FS
1623 ARM processors cannot fetch/store information which is not
1624 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1625 address divisible by 4. On 32-bit ARM processors, these non-aligned
1626 fetch/store instructions will be emulated in software if you say
1627 here, which has a severe performance impact. This is necessary for
1628 correct operation of some network protocols. With an IP-only
1629 configuration it is safe to say N, otherwise say Y.
1631 config UACCESS_WITH_MEMCPY
1632 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1633 depends on MMU && EXPERIMENTAL
1634 default y if CPU_FEROCEON
1636 Implement faster copy_to_user and clear_user methods for CPU
1637 cores where a 8-word STM instruction give significantly higher
1638 memory write throughput than a sequence of individual 32bit stores.
1640 A possible side effect is a slight increase in scheduling latency
1641 between threads sharing the same address space if they invoke
1642 such copy operations with large buffers.
1644 However, if the CPU data cache is using a write-allocate mode,
1645 this option is unlikely to provide any performance gain.
1649 prompt "Enable seccomp to safely compute untrusted bytecode"
1651 This kernel feature is useful for number crunching applications
1652 that may need to compute untrusted bytecode during their
1653 execution. By using pipes or other transports made available to
1654 the process as file descriptors supporting the read/write
1655 syscalls, it's possible to isolate those applications in
1656 their own address space using seccomp. Once seccomp is
1657 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1658 and the task is only allowed to execute a few safe syscalls
1659 defined by each seccomp mode.
1661 config CC_STACKPROTECTOR
1662 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1663 depends on EXPERIMENTAL
1665 This option turns on the -fstack-protector GCC feature. This
1666 feature puts, at the beginning of functions, a canary value on
1667 the stack just before the return address, and validates
1668 the value just before actually returning. Stack based buffer
1669 overflows (that need to overwrite this return address) now also
1670 overwrite the canary, which gets detected and the attack is then
1671 neutralized via a kernel panic.
1672 This feature requires gcc version 4.2 or above.
1674 config DEPRECATED_PARAM_STRUCT
1675 bool "Provide old way to pass kernel parameters"
1677 This was deprecated in 2001 and announced to live on for 5 years.
1678 Some old boot loaders still use this way.
1684 # Compressed boot loader in ROM. Yes, we really want to ask about
1685 # TEXT and BSS so we preserve their values in the config files.
1686 config ZBOOT_ROM_TEXT
1687 hex "Compressed ROM boot loader base address"
1690 The physical address at which the ROM-able zImage is to be
1691 placed in the target. Platforms which normally make use of
1692 ROM-able zImage formats normally set this to a suitable
1693 value in their defconfig file.
1695 If ZBOOT_ROM is not enabled, this has no effect.
1697 config ZBOOT_ROM_BSS
1698 hex "Compressed ROM boot loader BSS address"
1701 The base address of an area of read/write memory in the target
1702 for the ROM-able zImage which must be available while the
1703 decompressor is running. It must be large enough to hold the
1704 entire decompressed kernel plus an additional 128 KiB.
1705 Platforms which normally make use of ROM-able zImage formats
1706 normally set this to a suitable value in their defconfig file.
1708 If ZBOOT_ROM is not enabled, this has no effect.
1711 bool "Compressed boot loader in ROM/flash"
1712 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1714 Say Y here if you intend to execute your compressed kernel image
1715 (zImage) directly from ROM or flash. If unsure, say N.
1717 config ZBOOT_ROM_MMCIF
1718 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1719 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1721 Say Y here to include experimental MMCIF loading code in the
1722 ROM-able zImage. With this enabled it is possible to write the
1723 the ROM-able zImage kernel image to an MMC card and boot the
1724 kernel straight from the reset vector. At reset the processor
1725 Mask ROM will load the first part of the the ROM-able zImage
1726 which in turn loads the rest the kernel image to RAM using the
1727 MMCIF hardware block.
1730 string "Default kernel command string"
1733 On some architectures (EBSA110 and CATS), there is currently no way
1734 for the boot loader to pass arguments to the kernel. For these
1735 architectures, you should supply some command-line options at build
1736 time by entering them here. As a minimum, you should specify the
1737 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1739 config CMDLINE_FORCE
1740 bool "Always use the default kernel command string"
1741 depends on CMDLINE != ""
1743 Always use the default kernel command string, even if the boot
1744 loader passes other arguments to the kernel.
1745 This is useful if you cannot or don't want to change the
1746 command-line options your boot loader passes to the kernel.
1751 bool "Kernel Execute-In-Place from ROM"
1752 depends on !ZBOOT_ROM
1754 Execute-In-Place allows the kernel to run from non-volatile storage
1755 directly addressable by the CPU, such as NOR flash. This saves RAM
1756 space since the text section of the kernel is not loaded from flash
1757 to RAM. Read-write sections, such as the data section and stack,
1758 are still copied to RAM. The XIP kernel is not compressed since
1759 it has to run directly from flash, so it will take more space to
1760 store it. The flash address used to link the kernel object files,
1761 and for storing it, is configuration dependent. Therefore, if you
1762 say Y here, you must know the proper physical address where to
1763 store the kernel image depending on your own flash memory usage.
1765 Also note that the make target becomes "make xipImage" rather than
1766 "make zImage" or "make Image". The final kernel binary to put in
1767 ROM memory will be arch/arm/boot/xipImage.
1771 config XIP_PHYS_ADDR
1772 hex "XIP Kernel Physical Location"
1773 depends on XIP_KERNEL
1774 default "0x00080000"
1776 This is the physical address in your flash memory the kernel will
1777 be linked for and stored to. This address is dependent on your
1781 bool "Kexec system call (EXPERIMENTAL)"
1782 depends on EXPERIMENTAL
1784 kexec is a system call that implements the ability to shutdown your
1785 current kernel, and to start another kernel. It is like a reboot
1786 but it is independent of the system firmware. And like a reboot
1787 you can start any kernel with it, not just Linux.
1789 It is an ongoing process to be certain the hardware in a machine
1790 is properly shutdown, so do not be surprised if this code does not
1791 initially work for you. It may help to enable device hotplugging
1795 bool "Export atags in procfs"
1799 Should the atags used to boot the kernel be exported in an "atags"
1800 file in procfs. Useful with kexec.
1803 bool "Build kdump crash kernel (EXPERIMENTAL)"
1804 depends on EXPERIMENTAL
1806 Generate crash dump after being started by kexec. This should
1807 be normally only set in special crash dump kernels which are
1808 loaded in the main kernel with kexec-tools into a specially
1809 reserved region and then later executed after a crash by
1810 kdump/kexec. The crash dump kernel must be compiled to a
1811 memory address not used by the main kernel
1813 For more details see Documentation/kdump/kdump.txt
1815 config AUTO_ZRELADDR
1816 bool "Auto calculation of the decompressed kernel image address"
1817 depends on !ZBOOT_ROM && !ARCH_U300
1819 ZRELADDR is the physical address where the decompressed kernel
1820 image will be placed. If AUTO_ZRELADDR is selected, the address
1821 will be determined at run-time by masking the current IP with
1822 0xf8000000. This assumes the zImage being placed in the first 128MB
1823 from start of memory.
1827 menu "CPU Power Management"
1831 source "drivers/cpufreq/Kconfig"
1834 tristate "CPUfreq driver for i.MX CPUs"
1835 depends on ARCH_MXC && CPU_FREQ
1837 This enables the CPUfreq driver for i.MX CPUs.
1839 config CPU_FREQ_SA1100
1842 config CPU_FREQ_SA1110
1845 config CPU_FREQ_INTEGRATOR
1846 tristate "CPUfreq driver for ARM Integrator CPUs"
1847 depends on ARCH_INTEGRATOR && CPU_FREQ
1850 This enables the CPUfreq driver for ARM Integrator CPUs.
1852 For details, take a look at <file:Documentation/cpu-freq>.
1858 depends on CPU_FREQ && ARCH_PXA && PXA25x
1860 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1862 config CPU_FREQ_S3C64XX
1863 bool "CPUfreq support for Samsung S3C64XX CPUs"
1864 depends on CPU_FREQ && CPU_S3C6410
1869 Internal configuration node for common cpufreq on Samsung SoC
1871 config CPU_FREQ_S3C24XX
1872 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1873 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1876 This enables the CPUfreq driver for the Samsung S3C24XX family
1879 For details, take a look at <file:Documentation/cpu-freq>.
1883 config CPU_FREQ_S3C24XX_PLL
1884 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1885 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1887 Compile in support for changing the PLL frequency from the
1888 S3C24XX series CPUfreq driver. The PLL takes time to settle
1889 after a frequency change, so by default it is not enabled.
1891 This also means that the PLL tables for the selected CPU(s) will
1892 be built which may increase the size of the kernel image.
1894 config CPU_FREQ_S3C24XX_DEBUG
1895 bool "Debug CPUfreq Samsung driver core"
1896 depends on CPU_FREQ_S3C24XX
1898 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1900 config CPU_FREQ_S3C24XX_IODEBUG
1901 bool "Debug CPUfreq Samsung driver IO timing"
1902 depends on CPU_FREQ_S3C24XX
1904 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1906 config CPU_FREQ_S3C24XX_DEBUGFS
1907 bool "Export debugfs for CPUFreq"
1908 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1910 Export status information via debugfs.
1914 source "drivers/cpuidle/Kconfig"
1918 menu "Floating point emulation"
1920 comment "At least one emulation must be selected"
1923 bool "NWFPE math emulation"
1924 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1926 Say Y to include the NWFPE floating point emulator in the kernel.
1927 This is necessary to run most binaries. Linux does not currently
1928 support floating point hardware so you need to say Y here even if
1929 your machine has an FPA or floating point co-processor podule.
1931 You may say N here if you are going to load the Acorn FPEmulator
1932 early in the bootup.
1935 bool "Support extended precision"
1936 depends on FPE_NWFPE
1938 Say Y to include 80-bit support in the kernel floating-point
1939 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1940 Note that gcc does not generate 80-bit operations by default,
1941 so in most cases this option only enlarges the size of the
1942 floating point emulator without any good reason.
1944 You almost surely want to say N here.
1947 bool "FastFPE math emulation (EXPERIMENTAL)"
1948 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1950 Say Y here to include the FAST floating point emulator in the kernel.
1951 This is an experimental much faster emulator which now also has full
1952 precision for the mantissa. It does not support any exceptions.
1953 It is very simple, and approximately 3-6 times faster than NWFPE.
1955 It should be sufficient for most programs. It may be not suitable
1956 for scientific calculations, but you have to check this for yourself.
1957 If you do not feel you need a faster FP emulation you should better
1961 bool "VFP-format floating point maths"
1962 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1964 Say Y to include VFP support code in the kernel. This is needed
1965 if your hardware includes a VFP unit.
1967 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1968 release notes and additional status information.
1970 Say N if your target does not have VFP hardware.
1978 bool "Advanced SIMD (NEON) Extension support"
1979 depends on VFPv3 && CPU_V7
1981 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1986 menu "Userspace binary formats"
1988 source "fs/Kconfig.binfmt"
1991 tristate "RISC OS personality"
1994 Say Y here to include the kernel code necessary if you want to run
1995 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1996 experimental; if this sounds frightening, say N and sleep in peace.
1997 You can also say M here to compile this support as a module (which
1998 will be called arthur).
2002 menu "Power management options"
2004 source "kernel/power/Kconfig"
2006 config ARCH_SUSPEND_POSSIBLE
2011 source "net/Kconfig"
2013 source "drivers/Kconfig"
2017 source "arch/arm/Kconfig.debug"
2019 source "security/Kconfig"
2021 source "crypto/Kconfig"
2023 source "lib/Kconfig"