4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT if MMU
11 select CLONE_BACKWARDS
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IDLE_POLL_SETUP
17 select GENERIC_IRQ_PROBE
18 select GENERIC_IRQ_SHOW
19 select GENERIC_PCI_IOMAP
20 select GENERIC_SCHED_CLOCK
21 select GENERIC_SMP_IDLE_THREAD
22 select GENERIC_STRNCPY_FROM_USER
23 select GENERIC_STRNLEN_USER
24 select HARDIRQS_SW_RESEND
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_TRACEHOOK
30 select HAVE_CONTEXT_TRACKING
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_DMA_API_DEBUG
35 select HAVE_DMA_CONTIGUOUS if MMU
36 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
37 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
38 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
39 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
40 select HAVE_GENERIC_DMA_COHERENT
41 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
42 select HAVE_IDE if PCI || ISA || PCMCIA
43 select HAVE_IRQ_TIME_ACCOUNTING
44 select HAVE_KERNEL_GZIP
45 select HAVE_KERNEL_LZ4
46 select HAVE_KERNEL_LZMA
47 select HAVE_KERNEL_LZO
49 select HAVE_KPROBES if !XIP_KERNEL
50 select HAVE_KRETPROBES if (HAVE_KPROBES)
52 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
53 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
54 select HAVE_PERF_EVENTS
56 select HAVE_PERF_USER_STACK_DUMP
57 select HAVE_REGS_AND_STACK_ACCESS_API
58 select HAVE_SYSCALL_TRACEPOINTS
60 select HAVE_VIRT_CPU_ACCOUNTING_GEN
61 select IRQ_FORCED_THREADING
63 select MODULES_USE_ELF_REL
65 select OLD_SIGSUSPEND3
66 select PERF_USE_VMALLOC
68 select SYS_SUPPORTS_APM_EMULATION
69 # Above selects are sorted alphabetically; please add new ones
70 # according to that. Thanks.
72 The ARM series is a line of low-power-consumption RISC chip designs
73 licensed by ARM Ltd and targeted at embedded applications and
74 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
75 manufactured, but legacy ARM-based PC hardware remains popular in
76 Europe. There is an ARM Linux project with a web page at
77 <http://www.arm.linux.org.uk/>.
79 config ARM_HAS_SG_CHAIN
82 config NEED_SG_DMA_LENGTH
85 config ARM_DMA_USE_IOMMU
87 select ARM_HAS_SG_CHAIN
88 select NEED_SG_DMA_LENGTH
92 config ARM_DMA_IOMMU_ALIGNMENT
93 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
97 DMA mapping framework by default aligns all buffers to the smallest
98 PAGE_SIZE order which is greater than or equal to the requested buffer
99 size. This works well for buffers up to a few hundreds kilobytes, but
100 for larger buffers it just a waste of address space. Drivers which has
101 relatively small addressing window (like 64Mib) might run out of
102 virtual space with just a few allocations.
104 With this parameter you can specify the maximum PAGE_SIZE order for
105 DMA IOMMU buffers. Larger buffers will be aligned only to this
106 specified order. The order is expressed as a power of two multiplied
114 config MIGHT_HAVE_PCI
117 config SYS_SUPPORTS_APM_EMULATION
122 select GENERIC_ALLOCATOR
133 The Extended Industry Standard Architecture (EISA) bus was
134 developed as an open alternative to the IBM MicroChannel bus.
136 The EISA bus provided some of the features of the IBM MicroChannel
137 bus while maintaining backward compatibility with cards made for
138 the older ISA bus. The EISA bus saw limited use between 1988 and
139 1995 when it was made obsolete by the PCI bus.
141 Say Y here if you are building a kernel for an EISA-based machine.
148 config STACKTRACE_SUPPORT
152 config HAVE_LATENCYTOP_SUPPORT
157 config LOCKDEP_SUPPORT
161 config TRACE_IRQFLAGS_SUPPORT
165 config RWSEM_GENERIC_SPINLOCK
169 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_CPUFREQ
181 Internal node to signify that the ARCH has CPUFREQ support
182 and that the relevant menu configurations are displayed for
185 config ARCH_HAS_BANDGAP
188 config GENERIC_HWEIGHT
192 config GENERIC_CALIBRATE_DELAY
196 config ARCH_MAY_HAVE_PC_FDC
202 config NEED_DMA_MAP_STATE
205 config ARCH_HAS_DMA_SET_COHERENT_MASK
208 config GENERIC_ISA_DMA
214 config NEED_RET_TO_USER
222 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
223 default DRAM_BASE if REMAP_VECTORS_TO_RAM
226 The base address of exception vectors. This must be two pages
229 config ARM_PATCH_PHYS_VIRT
230 bool "Patch physical to virtual translations at runtime" if EMBEDDED
232 depends on !XIP_KERNEL && MMU
233 depends on !ARCH_REALVIEW || !SPARSEMEM
235 Patch phys-to-virt and virt-to-phys translation functions at
236 boot and module load time according to the position of the
237 kernel in system memory.
239 This can only be used with non-XIP MMU kernels where the base
240 of physical memory is at a 16MB boundary.
242 Only disable this option if you know that you do not require
243 this feature (eg, building a kernel for a single machine) and
244 you need to shrink the kernel to the minimal size.
246 config NEED_MACH_GPIO_H
249 Select this when mach/gpio.h is required to provide special
250 definitions for this platform. The need for mach/gpio.h should
251 be avoided when possible.
253 config NEED_MACH_IO_H
256 Select this when mach/io.h is required to provide special
257 definitions for this platform. The need for mach/io.h should
258 be avoided when possible.
260 config NEED_MACH_MEMORY_H
263 Select this when mach/memory.h is required to provide special
264 definitions for this platform. The need for mach/memory.h should
265 be avoided when possible.
268 hex "Physical address of main memory" if MMU
269 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
270 default DRAM_BASE if !MMU
272 Please provide the physical address corresponding to the
273 location of main memory in your system.
279 source "init/Kconfig"
281 source "kernel/Kconfig.freezer"
286 bool "MMU-based Paged Memory Management Support"
289 Select if you want MMU-based virtualised addressing space
290 support by paged memory management. If unsure, say 'Y'.
293 # The "ARM system type" choice list is ordered alphabetically by option
294 # text. Please add new entries in the option alphabetic order.
297 prompt "ARM system type"
298 default ARCH_VERSATILE if !MMU
299 default ARCH_MULTIPLATFORM if MMU
301 config ARCH_MULTIPLATFORM
302 bool "Allow multiple platforms to be selected"
304 select ARM_PATCH_PHYS_VIRT
307 select MULTI_IRQ_HANDLER
311 config ARCH_INTEGRATOR
312 bool "ARM Ltd. Integrator family"
313 select ARCH_HAS_CPUFREQ
316 select COMMON_CLK_VERSATILE
317 select GENERIC_CLOCKEVENTS
320 select MULTI_IRQ_HANDLER
321 select NEED_MACH_MEMORY_H
322 select PLAT_VERSATILE
325 select VERSATILE_FPGA_IRQ
327 Support for ARM's Integrator platform.
330 bool "ARM Ltd. RealView family"
331 select ARCH_WANT_OPTIONAL_GPIOLIB
333 select ARM_TIMER_SP804
335 select COMMON_CLK_VERSATILE
336 select GENERIC_CLOCKEVENTS
337 select GPIO_PL061 if GPIOLIB
339 select NEED_MACH_MEMORY_H
340 select PLAT_VERSATILE
341 select PLAT_VERSATILE_CLCD
343 This enables support for ARM Ltd RealView boards.
345 config ARCH_VERSATILE
346 bool "ARM Ltd. Versatile family"
347 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
352 select GENERIC_CLOCKEVENTS
353 select HAVE_MACH_CLKDEV
355 select PLAT_VERSATILE
356 select PLAT_VERSATILE_CLCD
357 select PLAT_VERSATILE_CLOCK
358 select VERSATILE_FPGA_IRQ
360 This enables support for ARM Ltd Versatile board.
364 select ARCH_REQUIRE_GPIOLIB
367 select NEED_MACH_GPIO_H
368 select NEED_MACH_IO_H if PCCARD
370 select PINCTRL_AT91 if USE_OF
372 This enables support for systems based on Atmel
373 AT91RM9200 and AT91SAM9* processors.
376 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
377 select ARCH_REQUIRE_GPIOLIB
382 select GENERIC_CLOCKEVENTS
384 select MULTI_IRQ_HANDLER
387 Support for Cirrus Logic 711x/721x/731x based boards.
390 bool "Cortina Systems Gemini"
391 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
396 Support for the Cortina Systems Gemini family SoCs
400 select ARCH_USES_GETTIMEOFFSET
403 select NEED_MACH_IO_H
404 select NEED_MACH_MEMORY_H
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 select ARCH_HAS_HOLES_MEMORYMODEL
415 select ARCH_REQUIRE_GPIOLIB
416 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_MEMORY_H
423 This enables support for the Cirrus EP93xx series of CPUs.
425 config ARCH_FOOTBRIDGE
429 select GENERIC_CLOCKEVENTS
431 select NEED_MACH_IO_H if !MMU
432 select NEED_MACH_MEMORY_H
434 Support for systems based on the DC21285 companion chip
435 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
438 bool "Hilscher NetX based"
442 select GENERIC_CLOCKEVENTS
444 This enables support for systems based on the Hilscher NetX Soc
450 select NEED_MACH_MEMORY_H
451 select NEED_RET_TO_USER
456 Support for Intel's IOP13XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
464 select NEED_RET_TO_USER
468 Support for Intel's 80219 and IOP32X (XScale) family of
474 select ARCH_REQUIRE_GPIOLIB
477 select NEED_RET_TO_USER
481 Support for Intel's IOP33X (XScale) family of processors.
486 select ARCH_HAS_DMA_SET_COHERENT_MASK
487 select ARCH_SUPPORTS_BIG_ENDIAN
488 select ARCH_REQUIRE_GPIOLIB
491 select DMABOUNCE if PCI
492 select GENERIC_CLOCKEVENTS
493 select MIGHT_HAVE_PCI
494 select NEED_MACH_IO_H
495 select USB_EHCI_BIG_ENDIAN_DESC
496 select USB_EHCI_BIG_ENDIAN_MMIO
498 Support for Intel's IXP4XX (XScale) family of processors.
502 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
505 select MIGHT_HAVE_PCI
509 select PLAT_ORION_LEGACY
510 select USB_ARCH_HAS_EHCI
512 Support for the Marvell Dove SoC 88AP510
515 bool "Marvell Kirkwood"
516 select ARCH_HAS_CPUFREQ
517 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
524 select PINCTRL_KIRKWOOD
525 select PLAT_ORION_LEGACY
527 Support for the following Marvell Kirkwood series SoCs:
528 88F6180, 88F6192 and 88F6281.
531 bool "Marvell MV78xx0"
532 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
537 select PLAT_ORION_LEGACY
539 Support for the following Marvell MV78xx0 series SoCs:
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Orion 5x series SoCs:
553 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
554 Orion-2 (5281), Orion-1-90 (6183).
557 bool "Marvell PXA168/910/MMP2"
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_ALLOCATOR
562 select GENERIC_CLOCKEVENTS
565 select MULTI_IRQ_HANDLER
570 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
573 bool "Micrel/Kendin KS8695"
574 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
578 select NEED_MACH_MEMORY_H
580 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
581 System-on-Chip devices.
584 bool "Nuvoton W90X900 CPU"
585 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
591 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
592 At present, the w90x900 has been renamed nuc900, regarding
593 the ARM series product line, you can login the following
594 link address to know more.
596 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
597 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
601 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
609 select USB_ARCH_HAS_OHCI
612 Support for the NXP LPC32XX family of processors
615 bool "PXA2xx/PXA3xx-based"
617 select ARCH_HAS_CPUFREQ
619 select ARCH_REQUIRE_GPIOLIB
620 select ARM_CPU_SUSPEND if PM
624 select GENERIC_CLOCKEVENTS
627 select MULTI_IRQ_HANDLER
631 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
635 select ARCH_REQUIRE_GPIOLIB
636 select CLKSRC_OF if OF
638 select GENERIC_CLOCKEVENTS
640 Support for Qualcomm MSM/QSD based systems. This runs on the
641 apps processor of the MSM/QSD and depends on a shared memory
642 interface to the modem processor which runs the baseband
643 stack and controls some vital subsystems
644 (clock and power control, etc).
647 bool "Renesas SH-Mobile / R-Mobile"
648 select ARM_PATCH_PHYS_VIRT
650 select GENERIC_CLOCKEVENTS
651 select HAVE_ARM_SCU if SMP
652 select HAVE_ARM_TWD if SMP
653 select HAVE_MACH_CLKDEV
655 select MIGHT_HAVE_CACHE_L2X0
656 select MULTI_IRQ_HANDLER
659 select PM_GENERIC_DOMAINS if PM
662 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
667 select ARCH_MAY_HAVE_PC_FDC
668 select ARCH_SPARSEMEM_ENABLE
669 select ARCH_USES_GETTIMEOFFSET
672 select HAVE_PATA_PLATFORM
674 select NEED_MACH_IO_H
675 select NEED_MACH_MEMORY_H
679 On the Acorn Risc-PC, Linux can support the internal IDE disk and
680 CD-ROM interface, serial and parallel port, and the floppy drive.
684 select ARCH_HAS_CPUFREQ
686 select ARCH_REQUIRE_GPIOLIB
687 select ARCH_SPARSEMEM_ENABLE
692 select GENERIC_CLOCKEVENTS
695 select NEED_MACH_MEMORY_H
698 Support for StrongARM 11x0 based boards.
701 bool "Samsung S3C24XX SoCs"
702 select ARCH_HAS_CPUFREQ
703 select ARCH_REQUIRE_GPIOLIB
705 select CLKSRC_SAMSUNG_PWM
706 select GENERIC_CLOCKEVENTS
708 select HAVE_S3C2410_I2C if I2C
709 select HAVE_S3C2410_WATCHDOG if WATCHDOG
710 select HAVE_S3C_RTC if RTC_CLASS
711 select MULTI_IRQ_HANDLER
712 select NEED_MACH_GPIO_H
713 select NEED_MACH_IO_H
716 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
717 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
718 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
719 Samsung SMDK2410 development board (and derivatives).
722 bool "Samsung S3C64XX"
723 select ARCH_HAS_CPUFREQ
724 select ARCH_REQUIRE_GPIOLIB
727 select CLKSRC_SAMSUNG_PWM
730 select GENERIC_CLOCKEVENTS
732 select HAVE_S3C2410_I2C if I2C
733 select HAVE_S3C2410_WATCHDOG if WATCHDOG
735 select NEED_MACH_GPIO_H
738 select PM_GENERIC_DOMAINS
740 select S3C_GPIO_TRACK
742 select SAMSUNG_GPIOLIB_4BIT
743 select SAMSUNG_WAKEMASK
744 select SAMSUNG_WDT_RESET
745 select USB_ARCH_HAS_OHCI
747 Samsung S3C64XX series based systems
750 bool "Samsung S5P6440 S5P6450"
752 select CLKSRC_SAMSUNG_PWM
754 select GENERIC_CLOCKEVENTS
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 select HAVE_S3C_RTC if RTC_CLASS
759 select NEED_MACH_GPIO_H
761 select SAMSUNG_WDT_RESET
763 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
767 bool "Samsung S5PC100"
768 select ARCH_REQUIRE_GPIOLIB
770 select CLKSRC_SAMSUNG_PWM
772 select GENERIC_CLOCKEVENTS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select HAVE_S3C_RTC if RTC_CLASS
777 select NEED_MACH_GPIO_H
779 select SAMSUNG_WDT_RESET
781 Samsung S5PC100 series based systems
784 bool "Samsung S5PV210/S5PC110"
785 select ARCH_HAS_CPUFREQ
786 select ARCH_HAS_HOLES_MEMORYMODEL
787 select ARCH_SPARSEMEM_ENABLE
789 select CLKSRC_SAMSUNG_PWM
791 select GENERIC_CLOCKEVENTS
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 select HAVE_S3C_RTC if RTC_CLASS
796 select NEED_MACH_GPIO_H
797 select NEED_MACH_MEMORY_H
800 Samsung S5PV210/S5PC110 series based systems
803 bool "Samsung EXYNOS"
804 select ARCH_HAS_CPUFREQ
805 select ARCH_HAS_HOLES_MEMORYMODEL
806 select ARCH_REQUIRE_GPIOLIB
807 select ARCH_SPARSEMEM_ENABLE
811 select GENERIC_CLOCKEVENTS
812 select HAVE_S3C2410_I2C if I2C
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
814 select HAVE_S3C_RTC if RTC_CLASS
815 select NEED_MACH_MEMORY_H
819 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
823 select ARCH_HAS_HOLES_MEMORYMODEL
824 select ARCH_REQUIRE_GPIOLIB
826 select GENERIC_ALLOCATOR
827 select GENERIC_CLOCKEVENTS
828 select GENERIC_IRQ_CHIP
834 Support for TI's DaVinci platform.
839 select ARCH_HAS_CPUFREQ
840 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_CLOCKEVENTS
846 select GENERIC_IRQ_CHIP
849 select NEED_MACH_IO_H if PCCARD
850 select NEED_MACH_MEMORY_H
852 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
856 menu "Multiple platform selection"
857 depends on ARCH_MULTIPLATFORM
859 comment "CPU Core family selection"
861 config ARCH_MULTI_V4T
862 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
863 depends on !ARCH_MULTI_V6_V7
864 select ARCH_MULTI_V4_V5
865 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
866 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
867 CPU_ARM925T || CPU_ARM940T)
870 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
871 depends on !ARCH_MULTI_V6_V7
872 select ARCH_MULTI_V4_V5
873 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
874 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
875 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
877 config ARCH_MULTI_V4_V5
881 bool "ARMv6 based platforms (ARM11)"
882 select ARCH_MULTI_V6_V7
886 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
888 select ARCH_MULTI_V6_V7
891 config ARCH_MULTI_V6_V7
894 config ARCH_MULTI_CPU_AUTO
895 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
901 # This is sorted alphabetically by mach-* pathname. However, plat-*
902 # Kconfigs may be included either alphabetically (according to the
903 # plat- suffix) or along side the corresponding mach-* source.
905 source "arch/arm/mach-mvebu/Kconfig"
907 source "arch/arm/mach-at91/Kconfig"
909 source "arch/arm/mach-bcm/Kconfig"
911 source "arch/arm/mach-bcm2835/Kconfig"
913 source "arch/arm/mach-clps711x/Kconfig"
915 source "arch/arm/mach-cns3xxx/Kconfig"
917 source "arch/arm/mach-davinci/Kconfig"
919 source "arch/arm/mach-dove/Kconfig"
921 source "arch/arm/mach-ep93xx/Kconfig"
923 source "arch/arm/mach-footbridge/Kconfig"
925 source "arch/arm/mach-gemini/Kconfig"
927 source "arch/arm/mach-highbank/Kconfig"
929 source "arch/arm/mach-integrator/Kconfig"
931 source "arch/arm/mach-iop32x/Kconfig"
933 source "arch/arm/mach-iop33x/Kconfig"
935 source "arch/arm/mach-iop13xx/Kconfig"
937 source "arch/arm/mach-ixp4xx/Kconfig"
939 source "arch/arm/mach-keystone/Kconfig"
941 source "arch/arm/mach-kirkwood/Kconfig"
943 source "arch/arm/mach-ks8695/Kconfig"
945 source "arch/arm/mach-msm/Kconfig"
947 source "arch/arm/mach-mv78xx0/Kconfig"
949 source "arch/arm/mach-imx/Kconfig"
951 source "arch/arm/mach-mxs/Kconfig"
953 source "arch/arm/mach-netx/Kconfig"
955 source "arch/arm/mach-nomadik/Kconfig"
957 source "arch/arm/mach-nspire/Kconfig"
959 source "arch/arm/plat-omap/Kconfig"
961 source "arch/arm/mach-omap1/Kconfig"
963 source "arch/arm/mach-omap2/Kconfig"
965 source "arch/arm/mach-orion5x/Kconfig"
967 source "arch/arm/mach-picoxcell/Kconfig"
969 source "arch/arm/mach-pxa/Kconfig"
970 source "arch/arm/plat-pxa/Kconfig"
972 source "arch/arm/mach-mmp/Kconfig"
974 source "arch/arm/mach-realview/Kconfig"
976 source "arch/arm/mach-rockchip/Kconfig"
978 source "arch/arm/mach-sa1100/Kconfig"
980 source "arch/arm/plat-samsung/Kconfig"
982 source "arch/arm/mach-socfpga/Kconfig"
984 source "arch/arm/mach-spear/Kconfig"
986 source "arch/arm/mach-sti/Kconfig"
988 source "arch/arm/mach-s3c24xx/Kconfig"
990 source "arch/arm/mach-s3c64xx/Kconfig"
992 source "arch/arm/mach-s5p64x0/Kconfig"
994 source "arch/arm/mach-s5pc100/Kconfig"
996 source "arch/arm/mach-s5pv210/Kconfig"
998 source "arch/arm/mach-exynos/Kconfig"
1000 source "arch/arm/mach-shmobile/Kconfig"
1002 source "arch/arm/mach-sunxi/Kconfig"
1004 source "arch/arm/mach-prima2/Kconfig"
1006 source "arch/arm/mach-tegra/Kconfig"
1008 source "arch/arm/mach-u300/Kconfig"
1010 source "arch/arm/mach-ux500/Kconfig"
1012 source "arch/arm/mach-versatile/Kconfig"
1014 source "arch/arm/mach-vexpress/Kconfig"
1015 source "arch/arm/plat-versatile/Kconfig"
1017 source "arch/arm/mach-virt/Kconfig"
1019 source "arch/arm/mach-vt8500/Kconfig"
1021 source "arch/arm/mach-w90x900/Kconfig"
1023 source "arch/arm/mach-zynq/Kconfig"
1025 # Definitions to make life easier
1031 select GENERIC_CLOCKEVENTS
1037 select GENERIC_IRQ_CHIP
1040 config PLAT_ORION_LEGACY
1047 config PLAT_VERSATILE
1050 config ARM_TIMER_SP804
1053 select CLKSRC_OF if OF
1055 source arch/arm/mm/Kconfig
1059 default 16 if ARCH_EP93XX
1063 bool "Enable iWMMXt support" if !CPU_PJ4
1064 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1065 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1067 Enable support for iWMMXt context switching at run time if
1068 running on a CPU that supports it.
1070 config MULTI_IRQ_HANDLER
1073 Allow each machine to specify it's own IRQ handler at run time.
1076 source "arch/arm/Kconfig-nommu"
1079 config PJ4B_ERRATA_4742
1080 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1081 depends on CPU_PJ4B && MACH_ARMADA_370
1084 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1085 Event (WFE) IDLE states, a specific timing sensitivity exists between
1086 the retiring WFI/WFE instructions and the newly issued subsequent
1087 instructions. This sensitivity can result in a CPU hang scenario.
1089 The software must insert either a Data Synchronization Barrier (DSB)
1090 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1093 config ARM_ERRATA_326103
1094 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1097 Executing a SWP instruction to read-only memory does not set bit 11
1098 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1099 treat the access as a read, preventing a COW from occurring and
1100 causing the faulting task to livelock.
1102 config ARM_ERRATA_411920
1103 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1104 depends on CPU_V6 || CPU_V6K
1106 Invalidation of the Instruction Cache operation can
1107 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1108 It does not affect the MPCore. This option enables the ARM Ltd.
1109 recommended workaround.
1111 config ARM_ERRATA_430973
1112 bool "ARM errata: Stale prediction on replaced interworking branch"
1115 This option enables the workaround for the 430973 Cortex-A8
1116 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1117 interworking branch is replaced with another code sequence at the
1118 same virtual address, whether due to self-modifying code or virtual
1119 to physical address re-mapping, Cortex-A8 does not recover from the
1120 stale interworking branch prediction. This results in Cortex-A8
1121 executing the new code sequence in the incorrect ARM or Thumb state.
1122 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1123 and also flushes the branch target cache at every context switch.
1124 Note that setting specific bits in the ACTLR register may not be
1125 available in non-secure mode.
1127 config ARM_ERRATA_458693
1128 bool "ARM errata: Processor deadlock when a false hazard is created"
1130 depends on !ARCH_MULTIPLATFORM
1132 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1133 erratum. For very specific sequences of memory operations, it is
1134 possible for a hazard condition intended for a cache line to instead
1135 be incorrectly associated with a different cache line. This false
1136 hazard might then cause a processor deadlock. The workaround enables
1137 the L1 caching of the NEON accesses and disables the PLD instruction
1138 in the ACTLR register. Note that setting specific bits in the ACTLR
1139 register may not be available in non-secure mode.
1141 config ARM_ERRATA_460075
1142 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1144 depends on !ARCH_MULTIPLATFORM
1146 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1147 erratum. Any asynchronous access to the L2 cache may encounter a
1148 situation in which recent store transactions to the L2 cache are lost
1149 and overwritten with stale memory contents from external memory. The
1150 workaround disables the write-allocate mode for the L2 cache via the
1151 ACTLR register. Note that setting specific bits in the ACTLR register
1152 may not be available in non-secure mode.
1154 config ARM_ERRATA_742230
1155 bool "ARM errata: DMB operation may be faulty"
1156 depends on CPU_V7 && SMP
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 742230 Cortex-A9
1160 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1161 between two write operations may not ensure the correct visibility
1162 ordering of the two writes. This workaround sets a specific bit in
1163 the diagnostic register of the Cortex-A9 which causes the DMB
1164 instruction to behave as a DSB, ensuring the correct behaviour of
1167 config ARM_ERRATA_742231
1168 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1169 depends on CPU_V7 && SMP
1170 depends on !ARCH_MULTIPLATFORM
1172 This option enables the workaround for the 742231 Cortex-A9
1173 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1174 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1175 accessing some data located in the same cache line, may get corrupted
1176 data due to bad handling of the address hazard when the line gets
1177 replaced from one of the CPUs at the same time as another CPU is
1178 accessing it. This workaround sets specific bits in the diagnostic
1179 register of the Cortex-A9 which reduces the linefill issuing
1180 capabilities of the processor.
1182 config PL310_ERRATA_588369
1183 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1184 depends on CACHE_L2X0
1186 The PL310 L2 cache controller implements three types of Clean &
1187 Invalidate maintenance operations: by Physical Address
1188 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1189 They are architecturally defined to behave as the execution of a
1190 clean operation followed immediately by an invalidate operation,
1191 both performing to the same memory location. This functionality
1192 is not correctly implemented in PL310 as clean lines are not
1193 invalidated as a result of these operations.
1195 config ARM_ERRATA_643719
1196 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1197 depends on CPU_V7 && SMP
1199 This option enables the workaround for the 643719 Cortex-A9 (prior to
1200 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1201 register returns zero when it should return one. The workaround
1202 corrects this value, ensuring cache maintenance operations which use
1203 it behave as intended and avoiding data corruption.
1205 config ARM_ERRATA_720789
1206 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1209 This option enables the workaround for the 720789 Cortex-A9 (prior to
1210 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1211 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1212 As a consequence of this erratum, some TLB entries which should be
1213 invalidated are not, resulting in an incoherency in the system page
1214 tables. The workaround changes the TLB flushing routines to invalidate
1215 entries regardless of the ASID.
1217 config PL310_ERRATA_727915
1218 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1219 depends on CACHE_L2X0
1221 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1222 operation (offset 0x7FC). This operation runs in background so that
1223 PL310 can handle normal accesses while it is in progress. Under very
1224 rare circumstances, due to this erratum, write data can be lost when
1225 PL310 treats a cacheable write transaction during a Clean &
1226 Invalidate by Way operation.
1228 config ARM_ERRATA_743622
1229 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1231 depends on !ARCH_MULTIPLATFORM
1233 This option enables the workaround for the 743622 Cortex-A9
1234 (r2p*) erratum. Under very rare conditions, a faulty
1235 optimisation in the Cortex-A9 Store Buffer may lead to data
1236 corruption. This workaround sets a specific bit in the diagnostic
1237 register of the Cortex-A9 which disables the Store Buffer
1238 optimisation, preventing the defect from occurring. This has no
1239 visible impact on the overall performance or power consumption of the
1242 config ARM_ERRATA_751472
1243 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1245 depends on !ARCH_MULTIPLATFORM
1247 This option enables the workaround for the 751472 Cortex-A9 (prior
1248 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1249 completion of a following broadcasted operation if the second
1250 operation is received by a CPU before the ICIALLUIS has completed,
1251 potentially leading to corrupted entries in the cache or TLB.
1253 config PL310_ERRATA_753970
1254 bool "PL310 errata: cache sync operation may be faulty"
1255 depends on CACHE_PL310
1257 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1259 Under some condition the effect of cache sync operation on
1260 the store buffer still remains when the operation completes.
1261 This means that the store buffer is always asked to drain and
1262 this prevents it from merging any further writes. The workaround
1263 is to replace the normal offset of cache sync operation (0x730)
1264 by another offset targeting an unmapped PL310 register 0x740.
1265 This has the same effect as the cache sync operation: store buffer
1266 drain and waiting for all buffers empty.
1268 config ARM_ERRATA_754322
1269 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1272 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1273 r3p*) erratum. A speculative memory access may cause a page table walk
1274 which starts prior to an ASID switch but completes afterwards. This
1275 can populate the micro-TLB with a stale entry which may be hit with
1276 the new ASID. This workaround places two dsb instructions in the mm
1277 switching code so that no page table walks can cross the ASID switch.
1279 config ARM_ERRATA_754327
1280 bool "ARM errata: no automatic Store Buffer drain"
1281 depends on CPU_V7 && SMP
1283 This option enables the workaround for the 754327 Cortex-A9 (prior to
1284 r2p0) erratum. The Store Buffer does not have any automatic draining
1285 mechanism and therefore a livelock may occur if an external agent
1286 continuously polls a memory location waiting to observe an update.
1287 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1288 written polling loops from denying visibility of updates to memory.
1290 config ARM_ERRATA_364296
1291 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1294 This options enables the workaround for the 364296 ARM1136
1295 r0p2 erratum (possible cache data corruption with
1296 hit-under-miss enabled). It sets the undocumented bit 31 in
1297 the auxiliary control register and the FI bit in the control
1298 register, thus disabling hit-under-miss without putting the
1299 processor into full low interrupt latency mode. ARM11MPCore
1302 config ARM_ERRATA_764369
1303 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1304 depends on CPU_V7 && SMP
1306 This option enables the workaround for erratum 764369
1307 affecting Cortex-A9 MPCore with two or more processors (all
1308 current revisions). Under certain timing circumstances, a data
1309 cache line maintenance operation by MVA targeting an Inner
1310 Shareable memory region may fail to proceed up to either the
1311 Point of Coherency or to the Point of Unification of the
1312 system. This workaround adds a DSB instruction before the
1313 relevant cache maintenance functions and sets a specific bit
1314 in the diagnostic control register of the SCU.
1316 config PL310_ERRATA_769419
1317 bool "PL310 errata: no automatic Store Buffer drain"
1318 depends on CACHE_L2X0
1320 On revisions of the PL310 prior to r3p2, the Store Buffer does
1321 not automatically drain. This can cause normal, non-cacheable
1322 writes to be retained when the memory system is idle, leading
1323 to suboptimal I/O performance for drivers using coherent DMA.
1324 This option adds a write barrier to the cpu_idle loop so that,
1325 on systems with an outer cache, the store buffer is drained
1328 config ARM_ERRATA_775420
1329 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1332 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1333 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1334 operation aborts with MMU exception, it might cause the processor
1335 to deadlock. This workaround puts DSB before executing ISB if
1336 an abort may occur on cache maintenance.
1338 config ARM_ERRATA_798181
1339 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1340 depends on CPU_V7 && SMP
1342 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1343 adequately shooting down all use of the old entries. This
1344 option enables the Linux kernel workaround for this erratum
1345 which sends an IPI to the CPUs that are running the same ASID
1346 as the one being invalidated.
1348 config ARM_ERRATA_773022
1349 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1352 This option enables the workaround for the 773022 Cortex-A15
1353 (up to r0p4) erratum. In certain rare sequences of code, the
1354 loop buffer may deliver incorrect instructions. This
1355 workaround disables the loop buffer to avoid the erratum.
1359 source "arch/arm/common/Kconfig"
1369 Find out whether you have ISA slots on your motherboard. ISA is the
1370 name of a bus system, i.e. the way the CPU talks to the other stuff
1371 inside your box. Other bus systems are PCI, EISA, MicroChannel
1372 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1373 newer boards don't support it. If you have ISA, say Y, otherwise N.
1375 # Select ISA DMA controller support
1380 # Select ISA DMA interface
1385 bool "PCI support" if MIGHT_HAVE_PCI
1387 Find out whether you have a PCI motherboard. PCI is the name of a
1388 bus system, i.e. the way the CPU talks to the other stuff inside
1389 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1390 VESA. If you have PCI, say Y, otherwise N.
1396 config PCI_NANOENGINE
1397 bool "BSE nanoEngine PCI support"
1398 depends on SA1100_NANOENGINE
1400 Enable PCI on the BSE nanoEngine board.
1405 config PCI_HOST_ITE8152
1407 depends on PCI && MACH_ARMCORE
1411 source "drivers/pci/Kconfig"
1412 source "drivers/pci/pcie/Kconfig"
1414 source "drivers/pcmcia/Kconfig"
1418 menu "Kernel Features"
1423 This option should be selected by machines which have an SMP-
1426 The only effect of this option is to make the SMP-related
1427 options available to the user for configuration.
1430 bool "Symmetric Multi-Processing"
1431 depends on CPU_V6K || CPU_V7
1432 depends on GENERIC_CLOCKEVENTS
1434 depends on MMU || ARM_MPU
1435 select USE_GENERIC_SMP_HELPERS
1437 This enables support for systems with more than one CPU. If you have
1438 a system with only one CPU, like most personal computers, say N. If
1439 you have a system with more than one CPU, say Y.
1441 If you say N here, the kernel will run on single and multiprocessor
1442 machines, but will use only one CPU of a multiprocessor machine. If
1443 you say Y here, the kernel will run on many, but not all, single
1444 processor machines. On a single processor machine, the kernel will
1445 run faster if you say N here.
1447 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1448 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1449 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1451 If you don't know what to do here, say N.
1454 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1455 depends on SMP && !XIP_KERNEL && MMU
1458 SMP kernels contain instructions which fail on non-SMP processors.
1459 Enabling this option allows the kernel to modify itself to make
1460 these instructions safe. Disabling it allows about 1K of space
1463 If you don't know what to do here, say Y.
1465 config ARM_CPU_TOPOLOGY
1466 bool "Support cpu topology definition"
1467 depends on SMP && CPU_V7
1470 Support ARM cpu topology definition. The MPIDR register defines
1471 affinity between processors which is then used to describe the cpu
1472 topology of an ARM System.
1475 bool "Multi-core scheduler support"
1476 depends on ARM_CPU_TOPOLOGY
1478 Multi-core scheduler support improves the CPU scheduler's decision
1479 making when dealing with multi-core CPU chips at a cost of slightly
1480 increased overhead in some places. If unsure say N here.
1483 bool "SMT scheduler support"
1484 depends on ARM_CPU_TOPOLOGY
1486 Improves the CPU scheduler's decision making when dealing with
1487 MultiThreading at a cost of slightly increased overhead in some
1488 places. If unsure say N here.
1493 This option enables support for the ARM system coherency unit
1495 config HAVE_ARM_ARCH_TIMER
1496 bool "Architected timer support"
1498 select ARM_ARCH_TIMER
1499 select GENERIC_CLOCKEVENTS
1501 This option enables support for the ARM architected timer
1506 select CLKSRC_OF if OF
1508 This options enables support for the ARM timer and watchdog unit
1511 bool "Multi-Cluster Power Management"
1512 depends on CPU_V7 && SMP
1514 This option provides the common power management infrastructure
1515 for (multi-)cluster based systems, such as big.LITTLE based
1519 bool "big.LITTLE support (Experimental)"
1520 depends on CPU_V7 && SMP
1523 This option enables support selections for the big.LITTLE
1524 system architecture.
1527 bool "big.LITTLE switcher support"
1528 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1530 select ARM_CPU_SUSPEND
1532 The big.LITTLE "switcher" provides the core functionality to
1533 transparently handle transition between a cluster of A15's
1534 and a cluster of A7's in a big.LITTLE system.
1536 config BL_SWITCHER_DUMMY_IF
1537 tristate "Simple big.LITTLE switcher user interface"
1538 depends on BL_SWITCHER && DEBUG_KERNEL
1540 This is a simple and dummy char dev interface to control
1541 the big.LITTLE switcher core code. It is meant for
1542 debugging purposes only.
1545 prompt "Memory split"
1548 Select the desired split between kernel and user memory.
1550 If you are not absolutely sure what you are doing, leave this
1554 bool "3G/1G user/kernel split"
1556 bool "2G/2G user/kernel split"
1558 bool "1G/3G user/kernel split"
1563 default 0x40000000 if VMSPLIT_1G
1564 default 0x80000000 if VMSPLIT_2G
1568 int "Maximum number of CPUs (2-32)"
1574 bool "Support for hot-pluggable CPUs"
1577 Say Y here to experiment with turning CPUs off and on. CPUs
1578 can be controlled through /sys/devices/system/cpu.
1581 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1584 Say Y here if you want Linux to communicate with system firmware
1585 implementing the PSCI specification for CPU-centric power
1586 management operations described in ARM document number ARM DEN
1587 0022A ("Power State Coordination Interface System Software on
1590 # The GPIO number here must be sorted by descending number. In case of
1591 # a multiplatform kernel, we just want the highest value required by the
1592 # selected platforms.
1595 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1596 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1597 default 392 if ARCH_U8500
1598 default 352 if ARCH_VT8500
1599 default 288 if ARCH_SUNXI
1600 default 264 if MACH_H4700
1603 Maximum number of GPIOs in the system.
1605 If unsure, leave the default value.
1607 source kernel/Kconfig.preempt
1611 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1612 ARCH_S5PV210 || ARCH_EXYNOS4
1613 default AT91_TIMER_HZ if ARCH_AT91
1614 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1618 depends on HZ_FIXED = 0
1619 prompt "Timer frequency"
1643 default HZ_FIXED if HZ_FIXED != 0
1644 default 100 if HZ_100
1645 default 200 if HZ_200
1646 default 250 if HZ_250
1647 default 300 if HZ_300
1648 default 500 if HZ_500
1652 def_bool HIGH_RES_TIMERS
1655 def_bool HIGH_RES_TIMERS
1657 config THUMB2_KERNEL
1658 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1659 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1660 default y if CPU_THUMBONLY
1662 select ARM_ASM_UNIFIED
1665 By enabling this option, the kernel will be compiled in
1666 Thumb-2 mode. A compiler/assembler that understand the unified
1667 ARM-Thumb syntax is needed.
1671 config THUMB2_AVOID_R_ARM_THM_JUMP11
1672 bool "Work around buggy Thumb-2 short branch relocations in gas"
1673 depends on THUMB2_KERNEL && MODULES
1676 Various binutils versions can resolve Thumb-2 branches to
1677 locally-defined, preemptible global symbols as short-range "b.n"
1678 branch instructions.
1680 This is a problem, because there's no guarantee the final
1681 destination of the symbol, or any candidate locations for a
1682 trampoline, are within range of the branch. For this reason, the
1683 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1684 relocation in modules at all, and it makes little sense to add
1687 The symptom is that the kernel fails with an "unsupported
1688 relocation" error when loading some modules.
1690 Until fixed tools are available, passing
1691 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1692 code which hits this problem, at the cost of a bit of extra runtime
1693 stack usage in some cases.
1695 The problem is described in more detail at:
1696 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1698 Only Thumb-2 kernels are affected.
1700 Unless you are sure your tools don't have this problem, say Y.
1702 config ARM_ASM_UNIFIED
1706 bool "Use the ARM EABI to compile the kernel"
1708 This option allows for the kernel to be compiled using the latest
1709 ARM ABI (aka EABI). This is only useful if you are using a user
1710 space environment that is also compiled with EABI.
1712 Since there are major incompatibilities between the legacy ABI and
1713 EABI, especially with regard to structure member alignment, this
1714 option also changes the kernel syscall calling convention to
1715 disambiguate both ABIs and allow for backward compatibility support
1716 (selected with CONFIG_OABI_COMPAT).
1718 To use this you need GCC version 4.0.0 or later.
1721 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1722 depends on AEABI && !THUMB2_KERNEL
1724 This option preserves the old syscall interface along with the
1725 new (ARM EABI) one. It also provides a compatibility layer to
1726 intercept syscalls that have structure arguments which layout
1727 in memory differs between the legacy ABI and the new ARM EABI
1728 (only for non "thumb" binaries). This option adds a tiny
1729 overhead to all syscalls and produces a slightly larger kernel.
1731 The seccomp filter system will not be available when this is
1732 selected, since there is no way yet to sensibly distinguish
1733 between calling conventions during filtering.
1735 If you know you'll be using only pure EABI user space then you
1736 can say N here. If this option is not selected and you attempt
1737 to execute a legacy ABI binary then the result will be
1738 UNPREDICTABLE (in fact it can be predicted that it won't work
1739 at all). If in doubt say N.
1741 config ARCH_HAS_HOLES_MEMORYMODEL
1744 config ARCH_SPARSEMEM_ENABLE
1747 config ARCH_SPARSEMEM_DEFAULT
1748 def_bool ARCH_SPARSEMEM_ENABLE
1750 config ARCH_SELECT_MEMORY_MODEL
1751 def_bool ARCH_SPARSEMEM_ENABLE
1753 config HAVE_ARCH_PFN_VALID
1754 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1757 bool "High Memory Support"
1760 The address space of ARM processors is only 4 Gigabytes large
1761 and it has to accommodate user address space, kernel address
1762 space as well as some memory mapped IO. That means that, if you
1763 have a large amount of physical memory and/or IO, not all of the
1764 memory can be "permanently mapped" by the kernel. The physical
1765 memory that is not permanently mapped is called "high memory".
1767 Depending on the selected kernel/user memory split, minimum
1768 vmalloc space and actual amount of RAM, you may not need this
1769 option which should result in a slightly faster kernel.
1774 bool "Allocate 2nd-level pagetables from highmem"
1777 config HW_PERF_EVENTS
1778 bool "Enable hardware performance counter support for perf events"
1779 depends on PERF_EVENTS
1782 Enable hardware performance counter support for perf events. If
1783 disabled, perf events will use software events only.
1785 config SYS_SUPPORTS_HUGETLBFS
1789 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1793 config ARCH_WANT_GENERAL_HUGETLB
1798 config FORCE_MAX_ZONEORDER
1799 int "Maximum zone order" if ARCH_SHMOBILE
1800 range 11 64 if ARCH_SHMOBILE
1801 default "12" if SOC_AM33XX
1802 default "9" if SA1111
1805 The kernel memory allocator divides physically contiguous memory
1806 blocks into "zones", where each zone is a power of two number of
1807 pages. This option selects the largest power of two that the kernel
1808 keeps in the memory allocator. If you need to allocate very large
1809 blocks of physically contiguous memory, then you may need to
1810 increase this value.
1812 This config option is actually maximum order plus one. For example,
1813 a value of 11 means that the largest free memory block is 2^10 pages.
1815 config ALIGNMENT_TRAP
1817 depends on CPU_CP15_MMU
1818 default y if !ARCH_EBSA110
1819 select HAVE_PROC_CPU if PROC_FS
1821 ARM processors cannot fetch/store information which is not
1822 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1823 address divisible by 4. On 32-bit ARM processors, these non-aligned
1824 fetch/store instructions will be emulated in software if you say
1825 here, which has a severe performance impact. This is necessary for
1826 correct operation of some network protocols. With an IP-only
1827 configuration it is safe to say N, otherwise say Y.
1829 config UACCESS_WITH_MEMCPY
1830 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1832 default y if CPU_FEROCEON
1834 Implement faster copy_to_user and clear_user methods for CPU
1835 cores where a 8-word STM instruction give significantly higher
1836 memory write throughput than a sequence of individual 32bit stores.
1838 A possible side effect is a slight increase in scheduling latency
1839 between threads sharing the same address space if they invoke
1840 such copy operations with large buffers.
1842 However, if the CPU data cache is using a write-allocate mode,
1843 this option is unlikely to provide any performance gain.
1847 prompt "Enable seccomp to safely compute untrusted bytecode"
1849 This kernel feature is useful for number crunching applications
1850 that may need to compute untrusted bytecode during their
1851 execution. By using pipes or other transports made available to
1852 the process as file descriptors supporting the read/write
1853 syscalls, it's possible to isolate those applications in
1854 their own address space using seccomp. Once seccomp is
1855 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1856 and the task is only allowed to execute a few safe syscalls
1857 defined by each seccomp mode.
1859 config CC_STACKPROTECTOR
1860 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1862 This option turns on the -fstack-protector GCC feature. This
1863 feature puts, at the beginning of functions, a canary value on
1864 the stack just before the return address, and validates
1865 the value just before actually returning. Stack based buffer
1866 overflows (that need to overwrite this return address) now also
1867 overwrite the canary, which gets detected and the attack is then
1868 neutralized via a kernel panic.
1869 This feature requires gcc version 4.2 or above.
1876 bool "Xen guest support on ARM (EXPERIMENTAL)"
1877 depends on ARM && AEABI && OF
1878 depends on CPU_V7 && !CPU_V6
1879 depends on !GENERIC_ATOMIC64
1882 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1889 bool "Flattened Device Tree support"
1892 select OF_EARLY_FLATTREE
1894 Include support for flattened device tree machine descriptions.
1897 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1900 This is the traditional way of passing data to the kernel at boot
1901 time. If you are solely relying on the flattened device tree (or
1902 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1903 to remove ATAGS support from your kernel binary. If unsure,
1906 config DEPRECATED_PARAM_STRUCT
1907 bool "Provide old way to pass kernel parameters"
1910 This was deprecated in 2001 and announced to live on for 5 years.
1911 Some old boot loaders still use this way.
1913 # Compressed boot loader in ROM. Yes, we really want to ask about
1914 # TEXT and BSS so we preserve their values in the config files.
1915 config ZBOOT_ROM_TEXT
1916 hex "Compressed ROM boot loader base address"
1919 The physical address at which the ROM-able zImage is to be
1920 placed in the target. Platforms which normally make use of
1921 ROM-able zImage formats normally set this to a suitable
1922 value in their defconfig file.
1924 If ZBOOT_ROM is not enabled, this has no effect.
1926 config ZBOOT_ROM_BSS
1927 hex "Compressed ROM boot loader BSS address"
1930 The base address of an area of read/write memory in the target
1931 for the ROM-able zImage which must be available while the
1932 decompressor is running. It must be large enough to hold the
1933 entire decompressed kernel plus an additional 128 KiB.
1934 Platforms which normally make use of ROM-able zImage formats
1935 normally set this to a suitable value in their defconfig file.
1937 If ZBOOT_ROM is not enabled, this has no effect.
1940 bool "Compressed boot loader in ROM/flash"
1941 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1943 Say Y here if you intend to execute your compressed kernel image
1944 (zImage) directly from ROM or flash. If unsure, say N.
1947 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1948 depends on ZBOOT_ROM && ARCH_SH7372
1949 default ZBOOT_ROM_NONE
1951 Include experimental SD/MMC loading code in the ROM-able zImage.
1952 With this enabled it is possible to write the ROM-able zImage
1953 kernel image to an MMC or SD card and boot the kernel straight
1954 from the reset vector. At reset the processor Mask ROM will load
1955 the first part of the ROM-able zImage which in turn loads the
1956 rest the kernel image to RAM.
1958 config ZBOOT_ROM_NONE
1959 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1961 Do not load image from SD or MMC
1963 config ZBOOT_ROM_MMCIF
1964 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1966 Load image from MMCIF hardware block.
1968 config ZBOOT_ROM_SH_MOBILE_SDHI
1969 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1971 Load image from SDHI hardware block
1975 config ARM_APPENDED_DTB
1976 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1977 depends on OF && !ZBOOT_ROM
1979 With this option, the boot code will look for a device tree binary
1980 (DTB) appended to zImage
1981 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1983 This is meant as a backward compatibility convenience for those
1984 systems with a bootloader that can't be upgraded to accommodate
1985 the documented boot protocol using a device tree.
1987 Beware that there is very little in terms of protection against
1988 this option being confused by leftover garbage in memory that might
1989 look like a DTB header after a reboot if no actual DTB is appended
1990 to zImage. Do not leave this option active in a production kernel
1991 if you don't intend to always append a DTB. Proper passing of the
1992 location into r2 of a bootloader provided DTB is always preferable
1995 config ARM_ATAG_DTB_COMPAT
1996 bool "Supplement the appended DTB with traditional ATAG information"
1997 depends on ARM_APPENDED_DTB
1999 Some old bootloaders can't be updated to a DTB capable one, yet
2000 they provide ATAGs with memory configuration, the ramdisk address,
2001 the kernel cmdline string, etc. Such information is dynamically
2002 provided by the bootloader and can't always be stored in a static
2003 DTB. To allow a device tree enabled kernel to be used with such
2004 bootloaders, this option allows zImage to extract the information
2005 from the ATAG list and store it at run time into the appended DTB.
2008 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2009 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2011 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2012 bool "Use bootloader kernel arguments if available"
2014 Uses the command-line options passed by the boot loader instead of
2015 the device tree bootargs property. If the boot loader doesn't provide
2016 any, the device tree bootargs property will be used.
2018 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2019 bool "Extend with bootloader kernel arguments"
2021 The command-line arguments provided by the boot loader will be
2022 appended to the the device tree bootargs property.
2027 string "Default kernel command string"
2030 On some architectures (EBSA110 and CATS), there is currently no way
2031 for the boot loader to pass arguments to the kernel. For these
2032 architectures, you should supply some command-line options at build
2033 time by entering them here. As a minimum, you should specify the
2034 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2037 prompt "Kernel command line type" if CMDLINE != ""
2038 default CMDLINE_FROM_BOOTLOADER
2041 config CMDLINE_FROM_BOOTLOADER
2042 bool "Use bootloader kernel arguments if available"
2044 Uses the command-line options passed by the boot loader. If
2045 the boot loader doesn't provide any, the default kernel command
2046 string provided in CMDLINE will be used.
2048 config CMDLINE_EXTEND
2049 bool "Extend bootloader kernel arguments"
2051 The command-line arguments provided by the boot loader will be
2052 appended to the default kernel command string.
2054 config CMDLINE_FORCE
2055 bool "Always use the default kernel command string"
2057 Always use the default kernel command string, even if the boot
2058 loader passes other arguments to the kernel.
2059 This is useful if you cannot or don't want to change the
2060 command-line options your boot loader passes to the kernel.
2064 bool "Kernel Execute-In-Place from ROM"
2065 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2067 Execute-In-Place allows the kernel to run from non-volatile storage
2068 directly addressable by the CPU, such as NOR flash. This saves RAM
2069 space since the text section of the kernel is not loaded from flash
2070 to RAM. Read-write sections, such as the data section and stack,
2071 are still copied to RAM. The XIP kernel is not compressed since
2072 it has to run directly from flash, so it will take more space to
2073 store it. The flash address used to link the kernel object files,
2074 and for storing it, is configuration dependent. Therefore, if you
2075 say Y here, you must know the proper physical address where to
2076 store the kernel image depending on your own flash memory usage.
2078 Also note that the make target becomes "make xipImage" rather than
2079 "make zImage" or "make Image". The final kernel binary to put in
2080 ROM memory will be arch/arm/boot/xipImage.
2084 config XIP_PHYS_ADDR
2085 hex "XIP Kernel Physical Location"
2086 depends on XIP_KERNEL
2087 default "0x00080000"
2089 This is the physical address in your flash memory the kernel will
2090 be linked for and stored to. This address is dependent on your
2094 bool "Kexec system call (EXPERIMENTAL)"
2095 depends on (!SMP || PM_SLEEP_SMP)
2097 kexec is a system call that implements the ability to shutdown your
2098 current kernel, and to start another kernel. It is like a reboot
2099 but it is independent of the system firmware. And like a reboot
2100 you can start any kernel with it, not just Linux.
2102 It is an ongoing process to be certain the hardware in a machine
2103 is properly shutdown, so do not be surprised if this code does not
2104 initially work for you.
2107 bool "Export atags in procfs"
2108 depends on ATAGS && KEXEC
2111 Should the atags used to boot the kernel be exported in an "atags"
2112 file in procfs. Useful with kexec.
2115 bool "Build kdump crash kernel (EXPERIMENTAL)"
2117 Generate crash dump after being started by kexec. This should
2118 be normally only set in special crash dump kernels which are
2119 loaded in the main kernel with kexec-tools into a specially
2120 reserved region and then later executed after a crash by
2121 kdump/kexec. The crash dump kernel must be compiled to a
2122 memory address not used by the main kernel
2124 For more details see Documentation/kdump/kdump.txt
2126 config AUTO_ZRELADDR
2127 bool "Auto calculation of the decompressed kernel image address"
2128 depends on !ZBOOT_ROM
2130 ZRELADDR is the physical address where the decompressed kernel
2131 image will be placed. If AUTO_ZRELADDR is selected, the address
2132 will be determined at run-time by masking the current IP with
2133 0xf8000000. This assumes the zImage being placed in the first 128MB
2134 from start of memory.
2138 menu "CPU Power Management"
2141 source "drivers/cpufreq/Kconfig"
2144 source "drivers/cpuidle/Kconfig"
2148 menu "Floating point emulation"
2150 comment "At least one emulation must be selected"
2153 bool "NWFPE math emulation"
2154 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2156 Say Y to include the NWFPE floating point emulator in the kernel.
2157 This is necessary to run most binaries. Linux does not currently
2158 support floating point hardware so you need to say Y here even if
2159 your machine has an FPA or floating point co-processor podule.
2161 You may say N here if you are going to load the Acorn FPEmulator
2162 early in the bootup.
2165 bool "Support extended precision"
2166 depends on FPE_NWFPE
2168 Say Y to include 80-bit support in the kernel floating-point
2169 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2170 Note that gcc does not generate 80-bit operations by default,
2171 so in most cases this option only enlarges the size of the
2172 floating point emulator without any good reason.
2174 You almost surely want to say N here.
2177 bool "FastFPE math emulation (EXPERIMENTAL)"
2178 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2180 Say Y here to include the FAST floating point emulator in the kernel.
2181 This is an experimental much faster emulator which now also has full
2182 precision for the mantissa. It does not support any exceptions.
2183 It is very simple, and approximately 3-6 times faster than NWFPE.
2185 It should be sufficient for most programs. It may be not suitable
2186 for scientific calculations, but you have to check this for yourself.
2187 If you do not feel you need a faster FP emulation you should better
2191 bool "VFP-format floating point maths"
2192 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2194 Say Y to include VFP support code in the kernel. This is needed
2195 if your hardware includes a VFP unit.
2197 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2198 release notes and additional status information.
2200 Say N if your target does not have VFP hardware.
2208 bool "Advanced SIMD (NEON) Extension support"
2209 depends on VFPv3 && CPU_V7
2211 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2214 config KERNEL_MODE_NEON
2215 bool "Support for NEON in kernel mode"
2216 depends on NEON && AEABI
2218 Say Y to include support for NEON in kernel mode.
2222 menu "Userspace binary formats"
2224 source "fs/Kconfig.binfmt"
2227 tristate "RISC OS personality"
2230 Say Y here to include the kernel code necessary if you want to run
2231 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2232 experimental; if this sounds frightening, say N and sleep in peace.
2233 You can also say M here to compile this support as a module (which
2234 will be called arthur).
2238 menu "Power management options"
2240 source "kernel/power/Kconfig"
2242 config ARCH_SUSPEND_POSSIBLE
2243 depends on !ARCH_S5PC100
2244 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2245 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2248 config ARM_CPU_SUSPEND
2253 source "net/Kconfig"
2255 source "drivers/Kconfig"
2259 source "arch/arm/Kconfig.debug"
2261 source "security/Kconfig"
2263 source "crypto/Kconfig"
2265 source "lib/Kconfig"
2267 source "arch/arm/kvm/Kconfig"