4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_KERNEL_THREAD
16 select GENERIC_KERNEL_EXECVE
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
61 The ARM series is a line of low-power-consumption RISC chip designs
62 licensed by ARM Ltd and targeted at embedded applications and
63 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
64 manufactured, but legacy ARM-based PC hardware remains popular in
65 Europe. There is an ARM Linux project with a web page at
66 <http://www.arm.linux.org.uk/>.
68 config ARM_HAS_SG_CHAIN
71 config NEED_SG_DMA_LENGTH
74 config ARM_DMA_USE_IOMMU
76 select ARM_HAS_SG_CHAIN
77 select NEED_SG_DMA_LENGTH
85 config SYS_SUPPORTS_APM_EMULATION
93 select GENERIC_ALLOCATOR
104 The Extended Industry Standard Architecture (EISA) bus was
105 developed as an open alternative to the IBM MicroChannel bus.
107 The EISA bus provided some of the features of the IBM MicroChannel
108 bus while maintaining backward compatibility with cards made for
109 the older ISA bus. The EISA bus saw limited use between 1988 and
110 1995 when it was made obsolete by the PCI bus.
112 Say Y here if you are building a kernel for an EISA-based machine.
119 config STACKTRACE_SUPPORT
123 config HAVE_LATENCYTOP_SUPPORT
128 config LOCKDEP_SUPPORT
132 config TRACE_IRQFLAGS_SUPPORT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config GENERIC_HWEIGHT
160 config GENERIC_CALIBRATE_DELAY
164 config ARCH_MAY_HAVE_PC_FDC
170 config NEED_DMA_MAP_STATE
173 config ARCH_HAS_DMA_SET_COHERENT_MASK
176 config GENERIC_ISA_DMA
182 config NEED_RET_TO_USER
190 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
191 default DRAM_BASE if REMAP_VECTORS_TO_RAM
194 The base address of exception vectors.
196 config ARM_PATCH_PHYS_VIRT
197 bool "Patch physical to virtual translations at runtime" if EMBEDDED
199 depends on !XIP_KERNEL && MMU
200 depends on !ARCH_REALVIEW || !SPARSEMEM
202 Patch phys-to-virt and virt-to-phys translation functions at
203 boot and module load time according to the position of the
204 kernel in system memory.
206 This can only be used with non-XIP MMU kernels where the base
207 of physical memory is at a 16MB boundary.
209 Only disable this option if you know that you do not require
210 this feature (eg, building a kernel for a single machine) and
211 you need to shrink the kernel to the minimal size.
213 config NEED_MACH_GPIO_H
216 Select this when mach/gpio.h is required to provide special
217 definitions for this platform. The need for mach/gpio.h should
218 be avoided when possible.
220 config NEED_MACH_IO_H
223 Select this when mach/io.h is required to provide special
224 definitions for this platform. The need for mach/io.h should
225 be avoided when possible.
227 config NEED_MACH_MEMORY_H
230 Select this when mach/memory.h is required to provide special
231 definitions for this platform. The need for mach/memory.h should
232 be avoided when possible.
235 hex "Physical address of main memory" if MMU
236 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
237 default DRAM_BASE if !MMU
239 Please provide the physical address corresponding to the
240 location of main memory in your system.
246 source "init/Kconfig"
248 source "kernel/Kconfig.freezer"
253 bool "MMU-based Paged Memory Management Support"
256 Select if you want MMU-based virtualised addressing space
257 support by paged memory management. If unsure, say 'Y'.
260 # The "ARM system type" choice list is ordered alphabetically by option
261 # text. Please add new entries in the option alphabetic order.
264 prompt "ARM system type"
265 default ARCH_MULTIPLATFORM
267 config ARCH_MULTIPLATFORM
268 bool "Allow multiple platforms to be selected"
270 select ARM_PATCH_PHYS_VIRT
273 select MULTI_IRQ_HANDLER
277 config ARCH_INTEGRATOR
278 bool "ARM Ltd. Integrator family"
279 select ARCH_HAS_CPUFREQ
282 select COMMON_CLK_VERSATILE
283 select GENERIC_CLOCKEVENTS
286 select MULTI_IRQ_HANDLER
287 select NEED_MACH_MEMORY_H
288 select PLAT_VERSATILE
290 select VERSATILE_FPGA_IRQ
292 Support for ARM's Integrator platform.
295 bool "ARM Ltd. RealView family"
296 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select ARM_TIMER_SP804
300 select COMMON_CLK_VERSATILE
301 select GENERIC_CLOCKEVENTS
302 select GPIO_PL061 if GPIOLIB
304 select NEED_MACH_MEMORY_H
305 select PLAT_VERSATILE
306 select PLAT_VERSATILE_CLCD
308 This enables support for ARM Ltd RealView boards.
310 config ARCH_VERSATILE
311 bool "ARM Ltd. Versatile family"
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 select ARM_TIMER_SP804
317 select GENERIC_CLOCKEVENTS
318 select HAVE_MACH_CLKDEV
320 select PLAT_VERSATILE
321 select PLAT_VERSATILE_CLCD
322 select PLAT_VERSATILE_CLOCK
323 select VERSATILE_FPGA_IRQ
325 This enables support for ARM Ltd Versatile board.
329 select ARCH_REQUIRE_GPIOLIB
333 select NEED_MACH_GPIO_H
334 select NEED_MACH_IO_H if PCCARD
336 select PINCTRL_AT91 if USE_OF
338 This enables support for systems based on Atmel
339 AT91RM9200 and AT91SAM9* processors.
342 bool "Broadcom BCM2835 family"
343 select ARCH_REQUIRE_GPIOLIB
345 select ARM_ERRATA_411920
346 select ARM_TIMER_SP804
350 select GENERIC_CLOCKEVENTS
352 select MULTI_IRQ_HANDLER
354 select PINCTRL_BCM2835
358 This enables support for the Broadcom BCM2835 SoC. This SoC is
359 use in the Raspberry Pi, and Roku 2 devices.
362 bool "Cavium Networks CNS3XXX family"
365 select GENERIC_CLOCKEVENTS
366 select MIGHT_HAVE_CACHE_L2X0
367 select MIGHT_HAVE_PCI
368 select PCI_DOMAINS if PCI
370 Support for Cavium Networks CNS3XXX platform.
373 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
374 select ARCH_REQUIRE_GPIOLIB
375 select ARCH_USES_GETTIMEOFFSET
380 select GENERIC_CLOCKEVENTS
381 select MULTI_IRQ_HANDLER
382 select NEED_MACH_MEMORY_H
385 Support for Cirrus Logic 711x/721x/731x based boards.
388 bool "Cortina Systems Gemini"
389 select ARCH_REQUIRE_GPIOLIB
390 select ARCH_USES_GETTIMEOFFSET
393 Support for the Cortina Systems Gemini family SoCs
397 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
400 select GENERIC_IRQ_CHIP
401 select MIGHT_HAVE_CACHE_L2X0
407 Support for CSR SiRFprimaII/Marco/Polo platforms
411 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_IO_H
415 select NEED_MACH_MEMORY_H
418 This is an evaluation board for the StrongARM processor available
419 from Digital. It has limited hardware on-board, including an
420 Ethernet interface, two PCMCIA sockets, two serial ports and a
425 select ARCH_HAS_HOLES_MEMORYMODEL
426 select ARCH_REQUIRE_GPIOLIB
427 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_MEMORY_H
434 This enables support for the Cirrus EP93xx series of CPUs.
436 config ARCH_FOOTBRIDGE
440 select GENERIC_CLOCKEVENTS
442 select NEED_MACH_IO_H if !MMU
443 select NEED_MACH_MEMORY_H
445 Support for systems based on the DC21285 companion chip
446 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
449 bool "Freescale MXS-based"
450 select ARCH_REQUIRE_GPIOLIB
454 select GENERIC_CLOCKEVENTS
455 select HAVE_CLK_PREPARE
456 select MULTI_IRQ_HANDLER
461 Support for Freescale MXS-based family of processors
464 bool "Hilscher NetX based"
468 select GENERIC_CLOCKEVENTS
470 This enables support for systems based on the Hilscher NetX Soc
473 bool "Hynix HMS720x-based"
474 select ARCH_USES_GETTIMEOFFSET
478 This enables support for systems based on the Hynix HMS720x
483 select ARCH_SUPPORTS_MSI
485 select NEED_MACH_MEMORY_H
486 select NEED_RET_TO_USER
491 Support for Intel's IOP13XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
498 select NEED_MACH_GPIO_H
499 select NEED_RET_TO_USER
503 Support for Intel's 80219 and IOP32X (XScale) family of
509 select ARCH_REQUIRE_GPIOLIB
511 select NEED_MACH_GPIO_H
512 select NEED_RET_TO_USER
516 Support for Intel's IOP33X (XScale) family of processors.
521 select ARCH_HAS_DMA_SET_COHERENT_MASK
522 select ARCH_REQUIRE_GPIOLIB
525 select DMABOUNCE if PCI
526 select GENERIC_CLOCKEVENTS
527 select MIGHT_HAVE_PCI
528 select NEED_MACH_IO_H
530 Support for Intel's IXP4XX (XScale) family of processors.
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
537 select MIGHT_HAVE_PCI
538 select PLAT_ORION_LEGACY
539 select USB_ARCH_HAS_EHCI
541 Support for the Marvell Dove SoC 88AP510
544 bool "Marvell Kirkwood"
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
556 bool "Marvell MV78xx0"
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
561 select PLAT_ORION_LEGACY
563 Support for the following Marvell MV78xx0 series SoCs:
569 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
573 select PLAT_ORION_LEGACY
575 Support for the following Marvell Orion 5x series SoCs:
576 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
577 Orion-2 (5281), Orion-1-90 (6183).
580 bool "Marvell PXA168/910/MMP2"
582 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_ALLOCATOR
585 select GENERIC_CLOCKEVENTS
588 select NEED_MACH_GPIO_H
593 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
596 bool "Micrel/Kendin KS8695"
597 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
601 select NEED_MACH_MEMORY_H
603 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
604 System-on-Chip devices.
607 bool "Nuvoton W90X900 CPU"
608 select ARCH_REQUIRE_GPIOLIB
612 select GENERIC_CLOCKEVENTS
614 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
615 At present, the w90x900 has been renamed nuc900, regarding
616 the ARM series product line, you can login the following
617 link address to know more.
619 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
620 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
624 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
632 select USB_ARCH_HAS_OHCI
635 Support for the NXP LPC32XX family of processors
639 select ARCH_HAS_CPUFREQ
643 select GENERIC_CLOCKEVENTS
647 select MIGHT_HAVE_CACHE_L2X0
650 This enables support for NVIDIA Tegra based systems (Tegra APX,
651 Tegra 6xx and Tegra 2 series).
654 bool "PXA2xx/PXA3xx-based"
656 select ARCH_HAS_CPUFREQ
658 select ARCH_REQUIRE_GPIOLIB
659 select ARM_CPU_SUSPEND if PM
663 select GENERIC_CLOCKEVENTS
666 select MULTI_IRQ_HANDLER
667 select NEED_MACH_GPIO_H
671 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
675 select ARCH_REQUIRE_GPIOLIB
677 select GENERIC_CLOCKEVENTS
680 Support for Qualcomm MSM/QSD based systems. This runs on the
681 apps processor of the MSM/QSD and depends on a shared memory
682 interface to the modem processor which runs the baseband
683 stack and controls some vital subsystems
684 (clock and power control, etc).
687 bool "Renesas SH-Mobile / R-Mobile"
689 select GENERIC_CLOCKEVENTS
691 select HAVE_MACH_CLKDEV
693 select MIGHT_HAVE_CACHE_L2X0
694 select MULTI_IRQ_HANDLER
695 select NEED_MACH_MEMORY_H
697 select PM_GENERIC_DOMAINS if PM
700 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
705 select ARCH_MAY_HAVE_PC_FDC
706 select ARCH_SPARSEMEM_ENABLE
707 select ARCH_USES_GETTIMEOFFSET
710 select HAVE_PATA_PLATFORM
712 select NEED_MACH_IO_H
713 select NEED_MACH_MEMORY_H
716 On the Acorn Risc-PC, Linux can support the internal IDE disk and
717 CD-ROM interface, serial and parallel port, and the floppy drive.
721 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
724 select ARCH_SPARSEMEM_ENABLE
729 select GENERIC_CLOCKEVENTS
732 select NEED_MACH_GPIO_H
733 select NEED_MACH_MEMORY_H
736 Support for StrongARM 11x0 based boards.
739 bool "Samsung S3C24XX SoCs"
740 select ARCH_HAS_CPUFREQ
741 select ARCH_USES_GETTIMEOFFSET
745 select HAVE_S3C2410_I2C if I2C
746 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 select HAVE_S3C_RTC if RTC_CLASS
748 select NEED_MACH_GPIO_H
749 select NEED_MACH_IO_H
751 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
752 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
753 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
754 Samsung SMDK2410 development board (and derivatives).
757 bool "Samsung S3C64XX"
758 select ARCH_HAS_CPUFREQ
759 select ARCH_REQUIRE_GPIOLIB
760 select ARCH_USES_GETTIMEOFFSET
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select NEED_MACH_GPIO_H
772 select S3C_GPIO_TRACK
773 select SAMSUNG_CLKSRC
774 select SAMSUNG_GPIOLIB_4BIT
775 select SAMSUNG_IRQ_VIC_TIMER
776 select USB_ARCH_HAS_OHCI
778 Samsung S3C64XX series based systems
781 bool "Samsung S5P6440 S5P6450"
785 select GENERIC_CLOCKEVENTS
788 select HAVE_S3C2410_I2C if I2C
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 select HAVE_S3C_RTC if RTC_CLASS
791 select NEED_MACH_GPIO_H
793 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
797 bool "Samsung S5PC100"
798 select ARCH_USES_GETTIMEOFFSET
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select HAVE_S3C_RTC if RTC_CLASS
806 select NEED_MACH_GPIO_H
808 Samsung S5PC100 series based systems
811 bool "Samsung S5PV210/S5PC110"
812 select ARCH_HAS_CPUFREQ
813 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARCH_SPARSEMEM_ENABLE
818 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select HAVE_S3C_RTC if RTC_CLASS
824 select NEED_MACH_GPIO_H
825 select NEED_MACH_MEMORY_H
827 Samsung S5PV210/S5PC110 series based systems
830 bool "Samsung EXYNOS"
831 select ARCH_HAS_CPUFREQ
832 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARCH_SPARSEMEM_ENABLE
836 select GENERIC_CLOCKEVENTS
839 select HAVE_S3C2410_I2C if I2C
840 select HAVE_S3C2410_WATCHDOG if WATCHDOG
841 select HAVE_S3C_RTC if RTC_CLASS
842 select NEED_MACH_GPIO_H
843 select NEED_MACH_MEMORY_H
845 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
849 select ARCH_USES_GETTIMEOFFSET
853 select NEED_MACH_MEMORY_H
857 Support for the StrongARM based Digital DNARD machine, also known
858 as "Shark" (<http://www.shark-linux.de/shark.html>).
861 bool "ST-Ericsson U300 Series"
863 select ARCH_REQUIRE_GPIOLIB
865 select ARM_PATCH_PHYS_VIRT
871 select GENERIC_CLOCKEVENTS
876 Support for ST-Ericsson U300 series mobile platforms.
879 bool "ST-Ericsson U8500 Series"
881 select ARCH_HAS_CPUFREQ
882 select ARCH_REQUIRE_GPIOLIB
886 select GENERIC_CLOCKEVENTS
888 select MIGHT_HAVE_CACHE_L2X0
890 Support for ST-Ericsson's Ux500 architecture
893 bool "STMicroelectronics Nomadik"
894 select ARCH_REQUIRE_GPIOLIB
899 select GENERIC_CLOCKEVENTS
900 select MIGHT_HAVE_CACHE_L2X0
902 select PINCTRL_STN8815
904 Support for the Nomadik platform by ST-Ericsson
908 select ARCH_HAS_CPUFREQ
909 select ARCH_REQUIRE_GPIOLIB
914 select GENERIC_CLOCKEVENTS
917 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
921 select ARCH_HAS_HOLES_MEMORYMODEL
922 select ARCH_REQUIRE_GPIOLIB
924 select GENERIC_ALLOCATOR
925 select GENERIC_CLOCKEVENTS
926 select GENERIC_IRQ_CHIP
928 select NEED_MACH_GPIO_H
932 Support for TI's DaVinci platform.
937 select ARCH_HAS_CPUFREQ
938 select ARCH_HAS_HOLES_MEMORYMODEL
939 select ARCH_REQUIRE_GPIOLIB
941 select GENERIC_CLOCKEVENTS
944 Support for TI's OMAP platform (OMAP1/2/3/4).
947 bool "VIA/WonderMedia 85xx"
948 select ARCH_HAS_CPUFREQ
949 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_CLOCKEVENTS
958 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
961 bool "Xilinx Zynq ARM Cortex A9 Platform"
965 select GENERIC_CLOCKEVENTS
967 select MIGHT_HAVE_CACHE_L2X0
970 Support for Xilinx Zynq ARM Cortex A9 Platform
973 menu "Multiple platform selection"
974 depends on ARCH_MULTIPLATFORM
976 comment "CPU Core family selection"
979 bool "ARMv4 based platforms (FA526, StrongARM)"
980 depends on !ARCH_MULTI_V6_V7
981 select ARCH_MULTI_V4_V5
983 config ARCH_MULTI_V4T
984 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
985 depends on !ARCH_MULTI_V6_V7
986 select ARCH_MULTI_V4_V5
989 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
990 depends on !ARCH_MULTI_V6_V7
991 select ARCH_MULTI_V4_V5
993 config ARCH_MULTI_V4_V5
997 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
998 select ARCH_MULTI_V6_V7
1001 config ARCH_MULTI_V7
1002 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1004 select ARCH_MULTI_V6_V7
1005 select ARCH_VEXPRESS
1008 config ARCH_MULTI_V6_V7
1011 config ARCH_MULTI_CPU_AUTO
1012 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1013 select ARCH_MULTI_V5
1018 # This is sorted alphabetically by mach-* pathname. However, plat-*
1019 # Kconfigs may be included either alphabetically (according to the
1020 # plat- suffix) or along side the corresponding mach-* source.
1022 source "arch/arm/mach-mvebu/Kconfig"
1024 source "arch/arm/mach-at91/Kconfig"
1026 source "arch/arm/mach-bcm/Kconfig"
1028 source "arch/arm/mach-clps711x/Kconfig"
1030 source "arch/arm/mach-cns3xxx/Kconfig"
1032 source "arch/arm/mach-davinci/Kconfig"
1034 source "arch/arm/mach-dove/Kconfig"
1036 source "arch/arm/mach-ep93xx/Kconfig"
1038 source "arch/arm/mach-footbridge/Kconfig"
1040 source "arch/arm/mach-gemini/Kconfig"
1042 source "arch/arm/mach-h720x/Kconfig"
1044 source "arch/arm/mach-highbank/Kconfig"
1046 source "arch/arm/mach-integrator/Kconfig"
1048 source "arch/arm/mach-iop32x/Kconfig"
1050 source "arch/arm/mach-iop33x/Kconfig"
1052 source "arch/arm/mach-iop13xx/Kconfig"
1054 source "arch/arm/mach-ixp4xx/Kconfig"
1056 source "arch/arm/mach-kirkwood/Kconfig"
1058 source "arch/arm/mach-ks8695/Kconfig"
1060 source "arch/arm/mach-msm/Kconfig"
1062 source "arch/arm/mach-mv78xx0/Kconfig"
1064 source "arch/arm/mach-imx/Kconfig"
1066 source "arch/arm/mach-mxs/Kconfig"
1068 source "arch/arm/mach-netx/Kconfig"
1070 source "arch/arm/mach-nomadik/Kconfig"
1071 source "arch/arm/plat-nomadik/Kconfig"
1073 source "arch/arm/plat-omap/Kconfig"
1075 source "arch/arm/mach-omap1/Kconfig"
1077 source "arch/arm/mach-omap2/Kconfig"
1079 source "arch/arm/mach-orion5x/Kconfig"
1081 source "arch/arm/mach-picoxcell/Kconfig"
1083 source "arch/arm/mach-pxa/Kconfig"
1084 source "arch/arm/plat-pxa/Kconfig"
1086 source "arch/arm/mach-mmp/Kconfig"
1088 source "arch/arm/mach-realview/Kconfig"
1090 source "arch/arm/mach-sa1100/Kconfig"
1092 source "arch/arm/plat-samsung/Kconfig"
1093 source "arch/arm/plat-s3c24xx/Kconfig"
1095 source "arch/arm/mach-socfpga/Kconfig"
1097 source "arch/arm/plat-spear/Kconfig"
1099 source "arch/arm/mach-s3c24xx/Kconfig"
1101 source "arch/arm/mach-s3c2412/Kconfig"
1102 source "arch/arm/mach-s3c2440/Kconfig"
1106 source "arch/arm/mach-s3c64xx/Kconfig"
1109 source "arch/arm/mach-s5p64x0/Kconfig"
1111 source "arch/arm/mach-s5pc100/Kconfig"
1113 source "arch/arm/mach-s5pv210/Kconfig"
1115 source "arch/arm/mach-exynos/Kconfig"
1117 source "arch/arm/mach-shmobile/Kconfig"
1119 source "arch/arm/mach-sunxi/Kconfig"
1121 source "arch/arm/mach-prima2/Kconfig"
1123 source "arch/arm/mach-tegra/Kconfig"
1125 source "arch/arm/mach-u300/Kconfig"
1127 source "arch/arm/mach-ux500/Kconfig"
1129 source "arch/arm/mach-versatile/Kconfig"
1131 source "arch/arm/mach-vexpress/Kconfig"
1132 source "arch/arm/plat-versatile/Kconfig"
1134 source "arch/arm/mach-w90x900/Kconfig"
1136 # Definitions to make life easier
1142 select GENERIC_CLOCKEVENTS
1148 select GENERIC_IRQ_CHIP
1151 config PLAT_ORION_LEGACY
1158 config PLAT_VERSATILE
1161 config ARM_TIMER_SP804
1164 select HAVE_SCHED_CLOCK
1166 source arch/arm/mm/Kconfig
1170 default 16 if ARCH_EP93XX
1174 bool "Enable iWMMXt support"
1175 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1176 default y if PXA27x || PXA3xx || ARCH_MMP
1178 Enable support for iWMMXt context switching at run time if
1179 running on a CPU that supports it.
1183 depends on CPU_XSCALE
1186 config MULTI_IRQ_HANDLER
1189 Allow each machine to specify it's own IRQ handler at run time.
1192 source "arch/arm/Kconfig-nommu"
1195 config ARM_ERRATA_326103
1196 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1199 Executing a SWP instruction to read-only memory does not set bit 11
1200 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1201 treat the access as a read, preventing a COW from occurring and
1202 causing the faulting task to livelock.
1204 config ARM_ERRATA_411920
1205 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1206 depends on CPU_V6 || CPU_V6K
1208 Invalidation of the Instruction Cache operation can
1209 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1210 It does not affect the MPCore. This option enables the ARM Ltd.
1211 recommended workaround.
1213 config ARM_ERRATA_430973
1214 bool "ARM errata: Stale prediction on replaced interworking branch"
1217 This option enables the workaround for the 430973 Cortex-A8
1218 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1219 interworking branch is replaced with another code sequence at the
1220 same virtual address, whether due to self-modifying code or virtual
1221 to physical address re-mapping, Cortex-A8 does not recover from the
1222 stale interworking branch prediction. This results in Cortex-A8
1223 executing the new code sequence in the incorrect ARM or Thumb state.
1224 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1225 and also flushes the branch target cache at every context switch.
1226 Note that setting specific bits in the ACTLR register may not be
1227 available in non-secure mode.
1229 config ARM_ERRATA_458693
1230 bool "ARM errata: Processor deadlock when a false hazard is created"
1233 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1234 erratum. For very specific sequences of memory operations, it is
1235 possible for a hazard condition intended for a cache line to instead
1236 be incorrectly associated with a different cache line. This false
1237 hazard might then cause a processor deadlock. The workaround enables
1238 the L1 caching of the NEON accesses and disables the PLD instruction
1239 in the ACTLR register. Note that setting specific bits in the ACTLR
1240 register may not be available in non-secure mode.
1242 config ARM_ERRATA_460075
1243 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1246 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1247 erratum. Any asynchronous access to the L2 cache may encounter a
1248 situation in which recent store transactions to the L2 cache are lost
1249 and overwritten with stale memory contents from external memory. The
1250 workaround disables the write-allocate mode for the L2 cache via the
1251 ACTLR register. Note that setting specific bits in the ACTLR register
1252 may not be available in non-secure mode.
1254 config ARM_ERRATA_742230
1255 bool "ARM errata: DMB operation may be faulty"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 742230 Cortex-A9
1259 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1260 between two write operations may not ensure the correct visibility
1261 ordering of the two writes. This workaround sets a specific bit in
1262 the diagnostic register of the Cortex-A9 which causes the DMB
1263 instruction to behave as a DSB, ensuring the correct behaviour of
1266 config ARM_ERRATA_742231
1267 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1268 depends on CPU_V7 && SMP
1270 This option enables the workaround for the 742231 Cortex-A9
1271 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1272 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1273 accessing some data located in the same cache line, may get corrupted
1274 data due to bad handling of the address hazard when the line gets
1275 replaced from one of the CPUs at the same time as another CPU is
1276 accessing it. This workaround sets specific bits in the diagnostic
1277 register of the Cortex-A9 which reduces the linefill issuing
1278 capabilities of the processor.
1280 config PL310_ERRATA_588369
1281 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1282 depends on CACHE_L2X0
1284 The PL310 L2 cache controller implements three types of Clean &
1285 Invalidate maintenance operations: by Physical Address
1286 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1287 They are architecturally defined to behave as the execution of a
1288 clean operation followed immediately by an invalidate operation,
1289 both performing to the same memory location. This functionality
1290 is not correctly implemented in PL310 as clean lines are not
1291 invalidated as a result of these operations.
1293 config ARM_ERRATA_720789
1294 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1297 This option enables the workaround for the 720789 Cortex-A9 (prior to
1298 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1299 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1300 As a consequence of this erratum, some TLB entries which should be
1301 invalidated are not, resulting in an incoherency in the system page
1302 tables. The workaround changes the TLB flushing routines to invalidate
1303 entries regardless of the ASID.
1305 config PL310_ERRATA_727915
1306 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1307 depends on CACHE_L2X0
1309 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1310 operation (offset 0x7FC). This operation runs in background so that
1311 PL310 can handle normal accesses while it is in progress. Under very
1312 rare circumstances, due to this erratum, write data can be lost when
1313 PL310 treats a cacheable write transaction during a Clean &
1314 Invalidate by Way operation.
1316 config ARM_ERRATA_743622
1317 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1320 This option enables the workaround for the 743622 Cortex-A9
1321 (r2p*) erratum. Under very rare conditions, a faulty
1322 optimisation in the Cortex-A9 Store Buffer may lead to data
1323 corruption. This workaround sets a specific bit in the diagnostic
1324 register of the Cortex-A9 which disables the Store Buffer
1325 optimisation, preventing the defect from occurring. This has no
1326 visible impact on the overall performance or power consumption of the
1329 config ARM_ERRATA_751472
1330 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1333 This option enables the workaround for the 751472 Cortex-A9 (prior
1334 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1335 completion of a following broadcasted operation if the second
1336 operation is received by a CPU before the ICIALLUIS has completed,
1337 potentially leading to corrupted entries in the cache or TLB.
1339 config PL310_ERRATA_753970
1340 bool "PL310 errata: cache sync operation may be faulty"
1341 depends on CACHE_PL310
1343 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1345 Under some condition the effect of cache sync operation on
1346 the store buffer still remains when the operation completes.
1347 This means that the store buffer is always asked to drain and
1348 this prevents it from merging any further writes. The workaround
1349 is to replace the normal offset of cache sync operation (0x730)
1350 by another offset targeting an unmapped PL310 register 0x740.
1351 This has the same effect as the cache sync operation: store buffer
1352 drain and waiting for all buffers empty.
1354 config ARM_ERRATA_754322
1355 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1358 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1359 r3p*) erratum. A speculative memory access may cause a page table walk
1360 which starts prior to an ASID switch but completes afterwards. This
1361 can populate the micro-TLB with a stale entry which may be hit with
1362 the new ASID. This workaround places two dsb instructions in the mm
1363 switching code so that no page table walks can cross the ASID switch.
1365 config ARM_ERRATA_754327
1366 bool "ARM errata: no automatic Store Buffer drain"
1367 depends on CPU_V7 && SMP
1369 This option enables the workaround for the 754327 Cortex-A9 (prior to
1370 r2p0) erratum. The Store Buffer does not have any automatic draining
1371 mechanism and therefore a livelock may occur if an external agent
1372 continuously polls a memory location waiting to observe an update.
1373 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1374 written polling loops from denying visibility of updates to memory.
1376 config ARM_ERRATA_364296
1377 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1378 depends on CPU_V6 && !SMP
1380 This options enables the workaround for the 364296 ARM1136
1381 r0p2 erratum (possible cache data corruption with
1382 hit-under-miss enabled). It sets the undocumented bit 31 in
1383 the auxiliary control register and the FI bit in the control
1384 register, thus disabling hit-under-miss without putting the
1385 processor into full low interrupt latency mode. ARM11MPCore
1388 config ARM_ERRATA_764369
1389 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1390 depends on CPU_V7 && SMP
1392 This option enables the workaround for erratum 764369
1393 affecting Cortex-A9 MPCore with two or more processors (all
1394 current revisions). Under certain timing circumstances, a data
1395 cache line maintenance operation by MVA targeting an Inner
1396 Shareable memory region may fail to proceed up to either the
1397 Point of Coherency or to the Point of Unification of the
1398 system. This workaround adds a DSB instruction before the
1399 relevant cache maintenance functions and sets a specific bit
1400 in the diagnostic control register of the SCU.
1402 config PL310_ERRATA_769419
1403 bool "PL310 errata: no automatic Store Buffer drain"
1404 depends on CACHE_L2X0
1406 On revisions of the PL310 prior to r3p2, the Store Buffer does
1407 not automatically drain. This can cause normal, non-cacheable
1408 writes to be retained when the memory system is idle, leading
1409 to suboptimal I/O performance for drivers using coherent DMA.
1410 This option adds a write barrier to the cpu_idle loop so that,
1411 on systems with an outer cache, the store buffer is drained
1414 config ARM_ERRATA_775420
1415 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1418 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1419 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1420 operation aborts with MMU exception, it might cause the processor
1421 to deadlock. This workaround puts DSB before executing ISB if
1422 an abort may occur on cache maintenance.
1426 source "arch/arm/common/Kconfig"
1436 Find out whether you have ISA slots on your motherboard. ISA is the
1437 name of a bus system, i.e. the way the CPU talks to the other stuff
1438 inside your box. Other bus systems are PCI, EISA, MicroChannel
1439 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1440 newer boards don't support it. If you have ISA, say Y, otherwise N.
1442 # Select ISA DMA controller support
1447 # Select ISA DMA interface
1452 bool "PCI support" if MIGHT_HAVE_PCI
1454 Find out whether you have a PCI motherboard. PCI is the name of a
1455 bus system, i.e. the way the CPU talks to the other stuff inside
1456 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1457 VESA. If you have PCI, say Y, otherwise N.
1463 config PCI_NANOENGINE
1464 bool "BSE nanoEngine PCI support"
1465 depends on SA1100_NANOENGINE
1467 Enable PCI on the BSE nanoEngine board.
1472 # Select the host bridge type
1473 config PCI_HOST_VIA82C505
1475 depends on PCI && ARCH_SHARK
1478 config PCI_HOST_ITE8152
1480 depends on PCI && MACH_ARMCORE
1484 source "drivers/pci/Kconfig"
1486 source "drivers/pcmcia/Kconfig"
1490 menu "Kernel Features"
1495 This option should be selected by machines which have an SMP-
1498 The only effect of this option is to make the SMP-related
1499 options available to the user for configuration.
1502 bool "Symmetric Multi-Processing"
1503 depends on CPU_V6K || CPU_V7
1504 depends on GENERIC_CLOCKEVENTS
1507 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1508 select USE_GENERIC_SMP_HELPERS
1510 This enables support for systems with more than one CPU. If you have
1511 a system with only one CPU, like most personal computers, say N. If
1512 you have a system with more than one CPU, say Y.
1514 If you say N here, the kernel will run on single and multiprocessor
1515 machines, but will use only one CPU of a multiprocessor machine. If
1516 you say Y here, the kernel will run on many, but not all, single
1517 processor machines. On a single processor machine, the kernel will
1518 run faster if you say N here.
1520 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1521 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1522 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1524 If you don't know what to do here, say N.
1527 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1528 depends on EXPERIMENTAL
1529 depends on SMP && !XIP_KERNEL
1532 SMP kernels contain instructions which fail on non-SMP processors.
1533 Enabling this option allows the kernel to modify itself to make
1534 these instructions safe. Disabling it allows about 1K of space
1537 If you don't know what to do here, say Y.
1539 config ARM_CPU_TOPOLOGY
1540 bool "Support cpu topology definition"
1541 depends on SMP && CPU_V7
1544 Support ARM cpu topology definition. The MPIDR register defines
1545 affinity between processors which is then used to describe the cpu
1546 topology of an ARM System.
1549 bool "Multi-core scheduler support"
1550 depends on ARM_CPU_TOPOLOGY
1552 Multi-core scheduler support improves the CPU scheduler's decision
1553 making when dealing with multi-core CPU chips at a cost of slightly
1554 increased overhead in some places. If unsure say N here.
1557 bool "SMT scheduler support"
1558 depends on ARM_CPU_TOPOLOGY
1560 Improves the CPU scheduler's decision making when dealing with
1561 MultiThreading at a cost of slightly increased overhead in some
1562 places. If unsure say N here.
1567 This option enables support for the ARM system coherency unit
1569 config ARM_ARCH_TIMER
1570 bool "Architected timer support"
1573 This option enables support for the ARM architected timer
1579 This options enables support for the ARM timer and watchdog unit
1582 prompt "Memory split"
1585 Select the desired split between kernel and user memory.
1587 If you are not absolutely sure what you are doing, leave this
1591 bool "3G/1G user/kernel split"
1593 bool "2G/2G user/kernel split"
1595 bool "1G/3G user/kernel split"
1600 default 0x40000000 if VMSPLIT_1G
1601 default 0x80000000 if VMSPLIT_2G
1605 int "Maximum number of CPUs (2-32)"
1611 bool "Support for hot-pluggable CPUs"
1612 depends on SMP && HOTPLUG
1614 Say Y here to experiment with turning CPUs off and on. CPUs
1615 can be controlled through /sys/devices/system/cpu.
1618 bool "Use local timer interrupts"
1621 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1623 Enable support for local timers on SMP platforms, rather then the
1624 legacy IPI broadcast method. Local timers allows the system
1625 accounting to be spread across the timer interval, preventing a
1626 "thundering herd" at every timer tick.
1630 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1631 default 355 if ARCH_U8500
1632 default 264 if MACH_H4700
1633 default 512 if SOC_OMAP5
1634 default 288 if ARCH_VT8500
1637 Maximum number of GPIOs in the system.
1639 If unsure, leave the default value.
1641 source kernel/Kconfig.preempt
1645 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1646 ARCH_S5PV210 || ARCH_EXYNOS4
1647 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1648 default AT91_TIMER_HZ if ARCH_AT91
1649 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1652 config THUMB2_KERNEL
1653 bool "Compile the kernel in Thumb-2 mode"
1654 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1656 select ARM_ASM_UNIFIED
1659 By enabling this option, the kernel will be compiled in
1660 Thumb-2 mode. A compiler/assembler that understand the unified
1661 ARM-Thumb syntax is needed.
1665 config THUMB2_AVOID_R_ARM_THM_JUMP11
1666 bool "Work around buggy Thumb-2 short branch relocations in gas"
1667 depends on THUMB2_KERNEL && MODULES
1670 Various binutils versions can resolve Thumb-2 branches to
1671 locally-defined, preemptible global symbols as short-range "b.n"
1672 branch instructions.
1674 This is a problem, because there's no guarantee the final
1675 destination of the symbol, or any candidate locations for a
1676 trampoline, are within range of the branch. For this reason, the
1677 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1678 relocation in modules at all, and it makes little sense to add
1681 The symptom is that the kernel fails with an "unsupported
1682 relocation" error when loading some modules.
1684 Until fixed tools are available, passing
1685 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1686 code which hits this problem, at the cost of a bit of extra runtime
1687 stack usage in some cases.
1689 The problem is described in more detail at:
1690 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1692 Only Thumb-2 kernels are affected.
1694 Unless you are sure your tools don't have this problem, say Y.
1696 config ARM_ASM_UNIFIED
1700 bool "Use the ARM EABI to compile the kernel"
1702 This option allows for the kernel to be compiled using the latest
1703 ARM ABI (aka EABI). This is only useful if you are using a user
1704 space environment that is also compiled with EABI.
1706 Since there are major incompatibilities between the legacy ABI and
1707 EABI, especially with regard to structure member alignment, this
1708 option also changes the kernel syscall calling convention to
1709 disambiguate both ABIs and allow for backward compatibility support
1710 (selected with CONFIG_OABI_COMPAT).
1712 To use this you need GCC version 4.0.0 or later.
1715 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1716 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1719 This option preserves the old syscall interface along with the
1720 new (ARM EABI) one. It also provides a compatibility layer to
1721 intercept syscalls that have structure arguments which layout
1722 in memory differs between the legacy ABI and the new ARM EABI
1723 (only for non "thumb" binaries). This option adds a tiny
1724 overhead to all syscalls and produces a slightly larger kernel.
1725 If you know you'll be using only pure EABI user space then you
1726 can say N here. If this option is not selected and you attempt
1727 to execute a legacy ABI binary then the result will be
1728 UNPREDICTABLE (in fact it can be predicted that it won't work
1729 at all). If in doubt say Y.
1731 config ARCH_HAS_HOLES_MEMORYMODEL
1734 config ARCH_SPARSEMEM_ENABLE
1737 config ARCH_SPARSEMEM_DEFAULT
1738 def_bool ARCH_SPARSEMEM_ENABLE
1740 config ARCH_SELECT_MEMORY_MODEL
1741 def_bool ARCH_SPARSEMEM_ENABLE
1743 config HAVE_ARCH_PFN_VALID
1744 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1747 bool "High Memory Support"
1750 The address space of ARM processors is only 4 Gigabytes large
1751 and it has to accommodate user address space, kernel address
1752 space as well as some memory mapped IO. That means that, if you
1753 have a large amount of physical memory and/or IO, not all of the
1754 memory can be "permanently mapped" by the kernel. The physical
1755 memory that is not permanently mapped is called "high memory".
1757 Depending on the selected kernel/user memory split, minimum
1758 vmalloc space and actual amount of RAM, you may not need this
1759 option which should result in a slightly faster kernel.
1764 bool "Allocate 2nd-level pagetables from highmem"
1767 config HW_PERF_EVENTS
1768 bool "Enable hardware performance counter support for perf events"
1769 depends on PERF_EVENTS
1772 Enable hardware performance counter support for perf events. If
1773 disabled, perf events will use software events only.
1777 config FORCE_MAX_ZONEORDER
1778 int "Maximum zone order" if ARCH_SHMOBILE
1779 range 11 64 if ARCH_SHMOBILE
1780 default "12" if SOC_AM33XX
1781 default "9" if SA1111
1784 The kernel memory allocator divides physically contiguous memory
1785 blocks into "zones", where each zone is a power of two number of
1786 pages. This option selects the largest power of two that the kernel
1787 keeps in the memory allocator. If you need to allocate very large
1788 blocks of physically contiguous memory, then you may need to
1789 increase this value.
1791 This config option is actually maximum order plus one. For example,
1792 a value of 11 means that the largest free memory block is 2^10 pages.
1794 config ALIGNMENT_TRAP
1796 depends on CPU_CP15_MMU
1797 default y if !ARCH_EBSA110
1798 select HAVE_PROC_CPU if PROC_FS
1800 ARM processors cannot fetch/store information which is not
1801 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1802 address divisible by 4. On 32-bit ARM processors, these non-aligned
1803 fetch/store instructions will be emulated in software if you say
1804 here, which has a severe performance impact. This is necessary for
1805 correct operation of some network protocols. With an IP-only
1806 configuration it is safe to say N, otherwise say Y.
1808 config UACCESS_WITH_MEMCPY
1809 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1811 default y if CPU_FEROCEON
1813 Implement faster copy_to_user and clear_user methods for CPU
1814 cores where a 8-word STM instruction give significantly higher
1815 memory write throughput than a sequence of individual 32bit stores.
1817 A possible side effect is a slight increase in scheduling latency
1818 between threads sharing the same address space if they invoke
1819 such copy operations with large buffers.
1821 However, if the CPU data cache is using a write-allocate mode,
1822 this option is unlikely to provide any performance gain.
1826 prompt "Enable seccomp to safely compute untrusted bytecode"
1828 This kernel feature is useful for number crunching applications
1829 that may need to compute untrusted bytecode during their
1830 execution. By using pipes or other transports made available to
1831 the process as file descriptors supporting the read/write
1832 syscalls, it's possible to isolate those applications in
1833 their own address space using seccomp. Once seccomp is
1834 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1835 and the task is only allowed to execute a few safe syscalls
1836 defined by each seccomp mode.
1838 config CC_STACKPROTECTOR
1839 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1840 depends on EXPERIMENTAL
1842 This option turns on the -fstack-protector GCC feature. This
1843 feature puts, at the beginning of functions, a canary value on
1844 the stack just before the return address, and validates
1845 the value just before actually returning. Stack based buffer
1846 overflows (that need to overwrite this return address) now also
1847 overwrite the canary, which gets detected and the attack is then
1848 neutralized via a kernel panic.
1849 This feature requires gcc version 4.2 or above.
1856 bool "Xen guest support on ARM (EXPERIMENTAL)"
1857 depends on EXPERIMENTAL && ARM && OF
1858 depends on CPU_V7 && !CPU_V6
1860 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1867 bool "Flattened Device Tree support"
1870 select OF_EARLY_FLATTREE
1872 Include support for flattened device tree machine descriptions.
1875 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1878 This is the traditional way of passing data to the kernel at boot
1879 time. If you are solely relying on the flattened device tree (or
1880 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1881 to remove ATAGS support from your kernel binary. If unsure,
1884 config DEPRECATED_PARAM_STRUCT
1885 bool "Provide old way to pass kernel parameters"
1888 This was deprecated in 2001 and announced to live on for 5 years.
1889 Some old boot loaders still use this way.
1891 # Compressed boot loader in ROM. Yes, we really want to ask about
1892 # TEXT and BSS so we preserve their values in the config files.
1893 config ZBOOT_ROM_TEXT
1894 hex "Compressed ROM boot loader base address"
1897 The physical address at which the ROM-able zImage is to be
1898 placed in the target. Platforms which normally make use of
1899 ROM-able zImage formats normally set this to a suitable
1900 value in their defconfig file.
1902 If ZBOOT_ROM is not enabled, this has no effect.
1904 config ZBOOT_ROM_BSS
1905 hex "Compressed ROM boot loader BSS address"
1908 The base address of an area of read/write memory in the target
1909 for the ROM-able zImage which must be available while the
1910 decompressor is running. It must be large enough to hold the
1911 entire decompressed kernel plus an additional 128 KiB.
1912 Platforms which normally make use of ROM-able zImage formats
1913 normally set this to a suitable value in their defconfig file.
1915 If ZBOOT_ROM is not enabled, this has no effect.
1918 bool "Compressed boot loader in ROM/flash"
1919 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1921 Say Y here if you intend to execute your compressed kernel image
1922 (zImage) directly from ROM or flash. If unsure, say N.
1925 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1926 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1927 default ZBOOT_ROM_NONE
1929 Include experimental SD/MMC loading code in the ROM-able zImage.
1930 With this enabled it is possible to write the ROM-able zImage
1931 kernel image to an MMC or SD card and boot the kernel straight
1932 from the reset vector. At reset the processor Mask ROM will load
1933 the first part of the ROM-able zImage which in turn loads the
1934 rest the kernel image to RAM.
1936 config ZBOOT_ROM_NONE
1937 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1939 Do not load image from SD or MMC
1941 config ZBOOT_ROM_MMCIF
1942 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1944 Load image from MMCIF hardware block.
1946 config ZBOOT_ROM_SH_MOBILE_SDHI
1947 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1949 Load image from SDHI hardware block
1953 config ARM_APPENDED_DTB
1954 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1955 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1957 With this option, the boot code will look for a device tree binary
1958 (DTB) appended to zImage
1959 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1961 This is meant as a backward compatibility convenience for those
1962 systems with a bootloader that can't be upgraded to accommodate
1963 the documented boot protocol using a device tree.
1965 Beware that there is very little in terms of protection against
1966 this option being confused by leftover garbage in memory that might
1967 look like a DTB header after a reboot if no actual DTB is appended
1968 to zImage. Do not leave this option active in a production kernel
1969 if you don't intend to always append a DTB. Proper passing of the
1970 location into r2 of a bootloader provided DTB is always preferable
1973 config ARM_ATAG_DTB_COMPAT
1974 bool "Supplement the appended DTB with traditional ATAG information"
1975 depends on ARM_APPENDED_DTB
1977 Some old bootloaders can't be updated to a DTB capable one, yet
1978 they provide ATAGs with memory configuration, the ramdisk address,
1979 the kernel cmdline string, etc. Such information is dynamically
1980 provided by the bootloader and can't always be stored in a static
1981 DTB. To allow a device tree enabled kernel to be used with such
1982 bootloaders, this option allows zImage to extract the information
1983 from the ATAG list and store it at run time into the appended DTB.
1986 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1987 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1989 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1990 bool "Use bootloader kernel arguments if available"
1992 Uses the command-line options passed by the boot loader instead of
1993 the device tree bootargs property. If the boot loader doesn't provide
1994 any, the device tree bootargs property will be used.
1996 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1997 bool "Extend with bootloader kernel arguments"
1999 The command-line arguments provided by the boot loader will be
2000 appended to the the device tree bootargs property.
2005 string "Default kernel command string"
2008 On some architectures (EBSA110 and CATS), there is currently no way
2009 for the boot loader to pass arguments to the kernel. For these
2010 architectures, you should supply some command-line options at build
2011 time by entering them here. As a minimum, you should specify the
2012 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2015 prompt "Kernel command line type" if CMDLINE != ""
2016 default CMDLINE_FROM_BOOTLOADER
2019 config CMDLINE_FROM_BOOTLOADER
2020 bool "Use bootloader kernel arguments if available"
2022 Uses the command-line options passed by the boot loader. If
2023 the boot loader doesn't provide any, the default kernel command
2024 string provided in CMDLINE will be used.
2026 config CMDLINE_EXTEND
2027 bool "Extend bootloader kernel arguments"
2029 The command-line arguments provided by the boot loader will be
2030 appended to the default kernel command string.
2032 config CMDLINE_FORCE
2033 bool "Always use the default kernel command string"
2035 Always use the default kernel command string, even if the boot
2036 loader passes other arguments to the kernel.
2037 This is useful if you cannot or don't want to change the
2038 command-line options your boot loader passes to the kernel.
2042 bool "Kernel Execute-In-Place from ROM"
2043 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2045 Execute-In-Place allows the kernel to run from non-volatile storage
2046 directly addressable by the CPU, such as NOR flash. This saves RAM
2047 space since the text section of the kernel is not loaded from flash
2048 to RAM. Read-write sections, such as the data section and stack,
2049 are still copied to RAM. The XIP kernel is not compressed since
2050 it has to run directly from flash, so it will take more space to
2051 store it. The flash address used to link the kernel object files,
2052 and for storing it, is configuration dependent. Therefore, if you
2053 say Y here, you must know the proper physical address where to
2054 store the kernel image depending on your own flash memory usage.
2056 Also note that the make target becomes "make xipImage" rather than
2057 "make zImage" or "make Image". The final kernel binary to put in
2058 ROM memory will be arch/arm/boot/xipImage.
2062 config XIP_PHYS_ADDR
2063 hex "XIP Kernel Physical Location"
2064 depends on XIP_KERNEL
2065 default "0x00080000"
2067 This is the physical address in your flash memory the kernel will
2068 be linked for and stored to. This address is dependent on your
2072 bool "Kexec system call (EXPERIMENTAL)"
2073 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2075 kexec is a system call that implements the ability to shutdown your
2076 current kernel, and to start another kernel. It is like a reboot
2077 but it is independent of the system firmware. And like a reboot
2078 you can start any kernel with it, not just Linux.
2080 It is an ongoing process to be certain the hardware in a machine
2081 is properly shutdown, so do not be surprised if this code does not
2082 initially work for you. It may help to enable device hotplugging
2086 bool "Export atags in procfs"
2087 depends on ATAGS && KEXEC
2090 Should the atags used to boot the kernel be exported in an "atags"
2091 file in procfs. Useful with kexec.
2094 bool "Build kdump crash kernel (EXPERIMENTAL)"
2095 depends on EXPERIMENTAL
2097 Generate crash dump after being started by kexec. This should
2098 be normally only set in special crash dump kernels which are
2099 loaded in the main kernel with kexec-tools into a specially
2100 reserved region and then later executed after a crash by
2101 kdump/kexec. The crash dump kernel must be compiled to a
2102 memory address not used by the main kernel
2104 For more details see Documentation/kdump/kdump.txt
2106 config AUTO_ZRELADDR
2107 bool "Auto calculation of the decompressed kernel image address"
2108 depends on !ZBOOT_ROM && !ARCH_U300
2110 ZRELADDR is the physical address where the decompressed kernel
2111 image will be placed. If AUTO_ZRELADDR is selected, the address
2112 will be determined at run-time by masking the current IP with
2113 0xf8000000. This assumes the zImage being placed in the first 128MB
2114 from start of memory.
2118 menu "CPU Power Management"
2122 source "drivers/cpufreq/Kconfig"
2125 tristate "CPUfreq driver for i.MX CPUs"
2126 depends on ARCH_MXC && CPU_FREQ
2127 select CPU_FREQ_TABLE
2129 This enables the CPUfreq driver for i.MX CPUs.
2131 config CPU_FREQ_SA1100
2134 config CPU_FREQ_SA1110
2137 config CPU_FREQ_INTEGRATOR
2138 tristate "CPUfreq driver for ARM Integrator CPUs"
2139 depends on ARCH_INTEGRATOR && CPU_FREQ
2142 This enables the CPUfreq driver for ARM Integrator CPUs.
2144 For details, take a look at <file:Documentation/cpu-freq>.
2150 depends on CPU_FREQ && ARCH_PXA && PXA25x
2152 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2153 select CPU_FREQ_TABLE
2158 Internal configuration node for common cpufreq on Samsung SoC
2160 config CPU_FREQ_S3C24XX
2161 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2162 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2165 This enables the CPUfreq driver for the Samsung S3C24XX family
2168 For details, take a look at <file:Documentation/cpu-freq>.
2172 config CPU_FREQ_S3C24XX_PLL
2173 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2174 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2176 Compile in support for changing the PLL frequency from the
2177 S3C24XX series CPUfreq driver. The PLL takes time to settle
2178 after a frequency change, so by default it is not enabled.
2180 This also means that the PLL tables for the selected CPU(s) will
2181 be built which may increase the size of the kernel image.
2183 config CPU_FREQ_S3C24XX_DEBUG
2184 bool "Debug CPUfreq Samsung driver core"
2185 depends on CPU_FREQ_S3C24XX
2187 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2189 config CPU_FREQ_S3C24XX_IODEBUG
2190 bool "Debug CPUfreq Samsung driver IO timing"
2191 depends on CPU_FREQ_S3C24XX
2193 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2195 config CPU_FREQ_S3C24XX_DEBUGFS
2196 bool "Export debugfs for CPUFreq"
2197 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2199 Export status information via debugfs.
2203 source "drivers/cpuidle/Kconfig"
2207 menu "Floating point emulation"
2209 comment "At least one emulation must be selected"
2212 bool "NWFPE math emulation"
2213 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2215 Say Y to include the NWFPE floating point emulator in the kernel.
2216 This is necessary to run most binaries. Linux does not currently
2217 support floating point hardware so you need to say Y here even if
2218 your machine has an FPA or floating point co-processor podule.
2220 You may say N here if you are going to load the Acorn FPEmulator
2221 early in the bootup.
2224 bool "Support extended precision"
2225 depends on FPE_NWFPE
2227 Say Y to include 80-bit support in the kernel floating-point
2228 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2229 Note that gcc does not generate 80-bit operations by default,
2230 so in most cases this option only enlarges the size of the
2231 floating point emulator without any good reason.
2233 You almost surely want to say N here.
2236 bool "FastFPE math emulation (EXPERIMENTAL)"
2237 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2239 Say Y here to include the FAST floating point emulator in the kernel.
2240 This is an experimental much faster emulator which now also has full
2241 precision for the mantissa. It does not support any exceptions.
2242 It is very simple, and approximately 3-6 times faster than NWFPE.
2244 It should be sufficient for most programs. It may be not suitable
2245 for scientific calculations, but you have to check this for yourself.
2246 If you do not feel you need a faster FP emulation you should better
2250 bool "VFP-format floating point maths"
2251 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2253 Say Y to include VFP support code in the kernel. This is needed
2254 if your hardware includes a VFP unit.
2256 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2257 release notes and additional status information.
2259 Say N if your target does not have VFP hardware.
2267 bool "Advanced SIMD (NEON) Extension support"
2268 depends on VFPv3 && CPU_V7
2270 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2275 menu "Userspace binary formats"
2277 source "fs/Kconfig.binfmt"
2280 tristate "RISC OS personality"
2283 Say Y here to include the kernel code necessary if you want to run
2284 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2285 experimental; if this sounds frightening, say N and sleep in peace.
2286 You can also say M here to compile this support as a module (which
2287 will be called arthur).
2291 menu "Power management options"
2293 source "kernel/power/Kconfig"
2295 config ARCH_SUSPEND_POSSIBLE
2296 depends on !ARCH_S5PC100
2297 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2298 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2301 config ARM_CPU_SUSPEND
2306 source "net/Kconfig"
2308 source "drivers/Kconfig"
2312 source "arch/arm/Kconfig.debug"
2314 source "security/Kconfig"
2316 source "crypto/Kconfig"
2318 source "lib/Kconfig"