4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select CPU_PM if (SUSPEND || CPU_IDLE)
9 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
12 select GENERIC_IRQ_PROBE
13 select GENERIC_IRQ_SHOW
14 select GENERIC_KERNEL_THREAD
15 select GENERIC_KERNEL_EXECVE
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_TRACEHOOK
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
59 The ARM series is a line of low-power-consumption RISC chip designs
60 licensed by ARM Ltd and targeted at embedded applications and
61 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
62 manufactured, but legacy ARM-based PC hardware remains popular in
63 Europe. There is an ARM Linux project with a web page at
64 <http://www.arm.linux.org.uk/>.
66 config ARM_HAS_SG_CHAIN
69 config NEED_SG_DMA_LENGTH
72 config ARM_DMA_USE_IOMMU
74 select ARM_HAS_SG_CHAIN
75 select NEED_SG_DMA_LENGTH
83 config SYS_SUPPORTS_APM_EMULATION
91 select GENERIC_ALLOCATOR
102 The Extended Industry Standard Architecture (EISA) bus was
103 developed as an open alternative to the IBM MicroChannel bus.
105 The EISA bus provided some of the features of the IBM MicroChannel
106 bus while maintaining backward compatibility with cards made for
107 the older ISA bus. The EISA bus saw limited use between 1988 and
108 1995 when it was made obsolete by the PCI bus.
110 Say Y here if you are building a kernel for an EISA-based machine.
117 config STACKTRACE_SUPPORT
121 config HAVE_LATENCYTOP_SUPPORT
126 config LOCKDEP_SUPPORT
130 config TRACE_IRQFLAGS_SUPPORT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config GENERIC_HWEIGHT
158 config GENERIC_CALIBRATE_DELAY
162 config ARCH_MAY_HAVE_PC_FDC
168 config NEED_DMA_MAP_STATE
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
174 config GENERIC_ISA_DMA
180 config NEED_RET_TO_USER
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_GPIO_H
214 Select this when mach/gpio.h is required to provide special
215 definitions for this platform. The need for mach/gpio.h should
216 be avoided when possible.
218 config NEED_MACH_IO_H
221 Select this when mach/io.h is required to provide special
222 definitions for this platform. The need for mach/io.h should
223 be avoided when possible.
225 config NEED_MACH_MEMORY_H
228 Select this when mach/memory.h is required to provide special
229 definitions for this platform. The need for mach/memory.h should
230 be avoided when possible.
233 hex "Physical address of main memory" if MMU
234 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
235 default DRAM_BASE if !MMU
237 Please provide the physical address corresponding to the
238 location of main memory in your system.
244 source "init/Kconfig"
246 source "kernel/Kconfig.freezer"
251 bool "MMU-based Paged Memory Management Support"
254 Select if you want MMU-based virtualised addressing space
255 support by paged memory management. If unsure, say 'Y'.
258 # The "ARM system type" choice list is ordered alphabetically by option
259 # text. Please add new entries in the option alphabetic order.
262 prompt "ARM system type"
263 default ARCH_MULTIPLATFORM
265 config ARCH_MULTIPLATFORM
266 bool "Allow multiple platforms to be selected"
268 select ARM_PATCH_PHYS_VIRT
271 select MULTI_IRQ_HANDLER
275 config ARCH_INTEGRATOR
276 bool "ARM Ltd. Integrator family"
277 select ARCH_HAS_CPUFREQ
280 select COMMON_CLK_VERSATILE
281 select GENERIC_CLOCKEVENTS
284 select MULTI_IRQ_HANDLER
285 select NEED_MACH_MEMORY_H
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_FPGA_IRQ
290 Support for ARM's Integrator platform.
293 bool "ARM Ltd. RealView family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select COMMON_CLK_VERSATILE
299 select GENERIC_CLOCKEVENTS
300 select GPIO_PL061 if GPIOLIB
302 select NEED_MACH_MEMORY_H
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
306 This enables support for ARM Ltd RealView boards.
308 config ARCH_VERSATILE
309 bool "ARM Ltd. Versatile family"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select ARM_TIMER_SP804
315 select GENERIC_CLOCKEVENTS
316 select HAVE_MACH_CLKDEV
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLCD
320 select PLAT_VERSATILE_CLOCK
321 select PLAT_VERSATILE_FPGA_IRQ
323 This enables support for ARM Ltd Versatile board.
327 select ARCH_REQUIRE_GPIOLIB
331 select NEED_MACH_GPIO_H
332 select NEED_MACH_IO_H if PCCARD
334 This enables support for systems based on Atmel
335 AT91RM9200 and AT91SAM9* processors.
338 bool "Broadcom BCM2835 family"
339 select ARCH_WANT_OPTIONAL_GPIOLIB
341 select ARM_ERRATA_411920
342 select ARM_TIMER_SP804
346 select GENERIC_CLOCKEVENTS
347 select MULTI_IRQ_HANDLER
351 This enables support for the Broadcom BCM2835 SoC. This SoC is
352 use in the Raspberry Pi, and Roku 2 devices.
355 bool "Cavium Networks CNS3XXX family"
358 select GENERIC_CLOCKEVENTS
359 select MIGHT_HAVE_CACHE_L2X0
360 select MIGHT_HAVE_PCI
361 select PCI_DOMAINS if PCI
363 Support for Cavium Networks CNS3XXX platform.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367 select ARCH_USES_GETTIMEOFFSET
371 select NEED_MACH_MEMORY_H
373 Support for Cirrus Logic 711x/721x/731x based boards.
376 bool "Cortina Systems Gemini"
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_USES_GETTIMEOFFSET
381 Support for the Cortina Systems Gemini family SoCs
385 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
388 select GENERIC_IRQ_CHIP
389 select MIGHT_HAVE_CACHE_L2X0
395 Support for CSR SiRFprimaII/Marco/Polo platforms
399 select ARCH_USES_GETTIMEOFFSET
402 select NEED_MACH_IO_H
403 select NEED_MACH_MEMORY_H
406 This is an evaluation board for the StrongARM processor available
407 from Digital. It has limited hardware on-board, including an
408 Ethernet interface, two PCMCIA sockets, two serial ports and a
413 select ARCH_HAS_HOLES_MEMORYMODEL
414 select ARCH_REQUIRE_GPIOLIB
415 select ARCH_USES_GETTIMEOFFSET
420 select NEED_MACH_MEMORY_H
422 This enables support for the Cirrus EP93xx series of CPUs.
424 config ARCH_FOOTBRIDGE
428 select GENERIC_CLOCKEVENTS
430 select NEED_MACH_IO_H if !MMU
431 select NEED_MACH_MEMORY_H
433 Support for systems based on the DC21285 companion chip
434 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
437 bool "Freescale MXS-based"
438 select ARCH_REQUIRE_GPIOLIB
442 select GENERIC_CLOCKEVENTS
443 select HAVE_CLK_PREPARE
444 select MULTI_IRQ_HANDLER
449 Support for Freescale MXS-based family of processors
452 bool "Hilscher NetX based"
456 select GENERIC_CLOCKEVENTS
458 This enables support for systems based on the Hilscher NetX Soc
461 bool "Hynix HMS720x-based"
462 select ARCH_USES_GETTIMEOFFSET
466 This enables support for systems based on the Hynix HMS720x
471 select ARCH_SUPPORTS_MSI
473 select NEED_MACH_MEMORY_H
474 select NEED_RET_TO_USER
479 Support for Intel's IOP13XX (XScale) family of processors.
484 select ARCH_REQUIRE_GPIOLIB
486 select NEED_MACH_GPIO_H
487 select NEED_RET_TO_USER
491 Support for Intel's 80219 and IOP32X (XScale) family of
497 select ARCH_REQUIRE_GPIOLIB
499 select NEED_MACH_GPIO_H
500 select NEED_RET_TO_USER
504 Support for Intel's IOP33X (XScale) family of processors.
509 select ARCH_HAS_DMA_SET_COHERENT_MASK
510 select ARCH_REQUIRE_GPIOLIB
513 select DMABOUNCE if PCI
514 select GENERIC_CLOCKEVENTS
515 select MIGHT_HAVE_PCI
516 select NEED_MACH_IO_H
518 Support for Intel's IXP4XX (XScale) family of processors.
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
526 select PLAT_ORION_LEGACY
527 select USB_ARCH_HAS_EHCI
529 Support for the Marvell Dove SoC 88AP510
532 bool "Marvell Kirkwood"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
537 select PLAT_ORION_LEGACY
539 Support for the following Marvell Kirkwood series SoCs:
540 88F6180, 88F6192 and 88F6281.
543 bool "Marvell MV78xx0"
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
548 select PLAT_ORION_LEGACY
550 Support for the following Marvell MV78xx0 series SoCs:
556 select ARCH_REQUIRE_GPIOLIB
558 select GENERIC_CLOCKEVENTS
560 select PLAT_ORION_LEGACY
562 Support for the following Marvell Orion 5x series SoCs:
563 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
564 Orion-2 (5281), Orion-1-90 (6183).
567 bool "Marvell PXA168/910/MMP2"
569 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_ALLOCATOR
572 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_GPIO_H
579 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
582 bool "Micrel/Kendin KS8695"
583 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_CLOCKEVENTS
587 select NEED_MACH_MEMORY_H
589 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
590 System-on-Chip devices.
593 bool "Nuvoton W90X900 CPU"
594 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
600 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
601 At present, the w90x900 has been renamed nuc900, regarding
602 the ARM series product line, you can login the following
603 link address to know more.
605 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
606 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
610 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
618 select USB_ARCH_HAS_OHCI
621 Support for the NXP LPC32XX family of processors
625 select ARCH_HAS_CPUFREQ
629 select GENERIC_CLOCKEVENTS
633 select MIGHT_HAVE_CACHE_L2X0
636 This enables support for NVIDIA Tegra based systems (Tegra APX,
637 Tegra 6xx and Tegra 2 series).
640 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_CPU_SUSPEND if PM
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
653 select NEED_MACH_GPIO_H
657 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
661 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
666 Support for Qualcomm MSM/QSD based systems. This runs on the
667 apps processor of the MSM/QSD and depends on a shared memory
668 interface to the modem processor which runs the baseband
669 stack and controls some vital subsystems
670 (clock and power control, etc).
673 bool "Renesas SH-Mobile / R-Mobile"
675 select GENERIC_CLOCKEVENTS
677 select HAVE_MACH_CLKDEV
679 select MIGHT_HAVE_CACHE_L2X0
680 select MULTI_IRQ_HANDLER
681 select NEED_MACH_MEMORY_H
683 select PM_GENERIC_DOMAINS if PM
686 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
691 select ARCH_MAY_HAVE_PC_FDC
692 select ARCH_SPARSEMEM_ENABLE
693 select ARCH_USES_GETTIMEOFFSET
696 select HAVE_PATA_PLATFORM
698 select NEED_MACH_IO_H
699 select NEED_MACH_MEMORY_H
702 On the Acorn Risc-PC, Linux can support the internal IDE disk and
703 CD-ROM interface, serial and parallel port, and the floppy drive.
707 select ARCH_HAS_CPUFREQ
709 select ARCH_REQUIRE_GPIOLIB
710 select ARCH_SPARSEMEM_ENABLE
715 select GENERIC_CLOCKEVENTS
718 select NEED_MACH_GPIO_H
719 select NEED_MACH_MEMORY_H
722 Support for StrongARM 11x0 based boards.
725 bool "Samsung S3C24XX SoCs"
726 select ARCH_HAS_CPUFREQ
727 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_S3C2410_I2C if I2C
732 select HAVE_S3C2410_WATCHDOG if WATCHDOG
733 select HAVE_S3C_RTC if RTC_CLASS
734 select NEED_MACH_GPIO_H
735 select NEED_MACH_IO_H
737 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
738 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
739 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
740 Samsung SMDK2410 development board (and derivatives).
743 bool "Samsung S3C64XX"
744 select ARCH_HAS_CPUFREQ
745 select ARCH_REQUIRE_GPIOLIB
746 select ARCH_USES_GETTIMEOFFSET
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754 select NEED_MACH_GPIO_H
758 select S3C_GPIO_TRACK
759 select SAMSUNG_CLKSRC
760 select SAMSUNG_GPIOLIB_4BIT
761 select SAMSUNG_IRQ_VIC_TIMER
762 select USB_ARCH_HAS_OHCI
764 Samsung S3C64XX series based systems
767 bool "Samsung S5P6440 S5P6450"
771 select GENERIC_CLOCKEVENTS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select HAVE_S3C_RTC if RTC_CLASS
777 select NEED_MACH_GPIO_H
779 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
783 bool "Samsung S5PC100"
784 select ARCH_USES_GETTIMEOFFSET
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C2410_WATCHDOG if WATCHDOG
791 select HAVE_S3C_RTC if RTC_CLASS
792 select NEED_MACH_GPIO_H
794 Samsung S5PC100 series based systems
797 bool "Samsung S5PV210/S5PC110"
798 select ARCH_HAS_CPUFREQ
799 select ARCH_HAS_HOLES_MEMORYMODEL
800 select ARCH_SPARSEMEM_ENABLE
804 select GENERIC_CLOCKEVENTS
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select HAVE_S3C_RTC if RTC_CLASS
810 select NEED_MACH_GPIO_H
811 select NEED_MACH_MEMORY_H
813 Samsung S5PV210/S5PC110 series based systems
816 bool "Samsung EXYNOS"
817 select ARCH_HAS_CPUFREQ
818 select ARCH_HAS_HOLES_MEMORYMODEL
819 select ARCH_SPARSEMEM_ENABLE
822 select GENERIC_CLOCKEVENTS
825 select HAVE_S3C2410_I2C if I2C
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select HAVE_S3C_RTC if RTC_CLASS
828 select NEED_MACH_GPIO_H
829 select NEED_MACH_MEMORY_H
831 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
835 select ARCH_USES_GETTIMEOFFSET
839 select NEED_MACH_MEMORY_H
843 Support for the StrongARM based Digital DNARD machine, also known
844 as "Shark" (<http://www.shark-linux.de/shark.html>).
847 bool "ST-Ericsson U300 Series"
849 select ARCH_REQUIRE_GPIOLIB
851 select ARM_PATCH_PHYS_VIRT
857 select GENERIC_CLOCKEVENTS
862 Support for ST-Ericsson U300 series mobile platforms.
865 bool "ST-Ericsson U8500 Series"
867 select ARCH_HAS_CPUFREQ
868 select ARCH_REQUIRE_GPIOLIB
872 select GENERIC_CLOCKEVENTS
874 select MIGHT_HAVE_CACHE_L2X0
876 Support for ST-Ericsson's Ux500 architecture
879 bool "STMicroelectronics Nomadik"
880 select ARCH_REQUIRE_GPIOLIB
885 select GENERIC_CLOCKEVENTS
886 select MIGHT_HAVE_CACHE_L2X0
888 select PINCTRL_STN8815
890 Support for the Nomadik platform by ST-Ericsson
894 select ARCH_REQUIRE_GPIOLIB
899 select GENERIC_CLOCKEVENTS
902 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
906 select ARCH_HAS_HOLES_MEMORYMODEL
907 select ARCH_REQUIRE_GPIOLIB
909 select GENERIC_ALLOCATOR
910 select GENERIC_CLOCKEVENTS
911 select GENERIC_IRQ_CHIP
913 select NEED_MACH_GPIO_H
916 Support for TI's DaVinci platform.
921 select ARCH_HAS_CPUFREQ
922 select ARCH_HAS_HOLES_MEMORYMODEL
923 select ARCH_REQUIRE_GPIOLIB
925 select GENERIC_CLOCKEVENTS
927 select NEED_MACH_GPIO_H
929 Support for TI's OMAP platform (OMAP1/2/3/4).
932 bool "VIA/WonderMedia 85xx"
933 select ARCH_HAS_CPUFREQ
934 select ARCH_REQUIRE_GPIOLIB
938 select GENERIC_CLOCKEVENTS
943 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
946 bool "Xilinx Zynq ARM Cortex A9 Platform"
951 select GENERIC_CLOCKEVENTS
953 select MIGHT_HAVE_CACHE_L2X0
956 Support for Xilinx Zynq ARM Cortex A9 Platform
959 menu "Multiple platform selection"
960 depends on ARCH_MULTIPLATFORM
962 comment "CPU Core family selection"
965 bool "ARMv4 based platforms (FA526, StrongARM)"
966 depends on !ARCH_MULTI_V6_V7
967 select ARCH_MULTI_V4_V5
969 config ARCH_MULTI_V4T
970 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
971 depends on !ARCH_MULTI_V6_V7
972 select ARCH_MULTI_V4_V5
975 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
976 depends on !ARCH_MULTI_V6_V7
977 select ARCH_MULTI_V4_V5
979 config ARCH_MULTI_V4_V5
983 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
984 select ARCH_MULTI_V6_V7
988 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
990 select ARCH_MULTI_V6_V7
994 config ARCH_MULTI_V6_V7
997 config ARCH_MULTI_CPU_AUTO
998 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1004 # This is sorted alphabetically by mach-* pathname. However, plat-*
1005 # Kconfigs may be included either alphabetically (according to the
1006 # plat- suffix) or along side the corresponding mach-* source.
1008 source "arch/arm/mach-mvebu/Kconfig"
1010 source "arch/arm/mach-at91/Kconfig"
1012 source "arch/arm/mach-clps711x/Kconfig"
1014 source "arch/arm/mach-cns3xxx/Kconfig"
1016 source "arch/arm/mach-davinci/Kconfig"
1018 source "arch/arm/mach-dove/Kconfig"
1020 source "arch/arm/mach-ep93xx/Kconfig"
1022 source "arch/arm/mach-footbridge/Kconfig"
1024 source "arch/arm/mach-gemini/Kconfig"
1026 source "arch/arm/mach-h720x/Kconfig"
1028 source "arch/arm/mach-highbank/Kconfig"
1030 source "arch/arm/mach-integrator/Kconfig"
1032 source "arch/arm/mach-iop32x/Kconfig"
1034 source "arch/arm/mach-iop33x/Kconfig"
1036 source "arch/arm/mach-iop13xx/Kconfig"
1038 source "arch/arm/mach-ixp4xx/Kconfig"
1040 source "arch/arm/mach-kirkwood/Kconfig"
1042 source "arch/arm/mach-ks8695/Kconfig"
1044 source "arch/arm/mach-msm/Kconfig"
1046 source "arch/arm/mach-mv78xx0/Kconfig"
1048 source "arch/arm/mach-imx/Kconfig"
1050 source "arch/arm/mach-mxs/Kconfig"
1052 source "arch/arm/mach-netx/Kconfig"
1054 source "arch/arm/mach-nomadik/Kconfig"
1055 source "arch/arm/plat-nomadik/Kconfig"
1057 source "arch/arm/plat-omap/Kconfig"
1059 source "arch/arm/mach-omap1/Kconfig"
1061 source "arch/arm/mach-omap2/Kconfig"
1063 source "arch/arm/mach-orion5x/Kconfig"
1065 source "arch/arm/mach-picoxcell/Kconfig"
1067 source "arch/arm/mach-pxa/Kconfig"
1068 source "arch/arm/plat-pxa/Kconfig"
1070 source "arch/arm/mach-mmp/Kconfig"
1072 source "arch/arm/mach-realview/Kconfig"
1074 source "arch/arm/mach-sa1100/Kconfig"
1076 source "arch/arm/plat-samsung/Kconfig"
1077 source "arch/arm/plat-s3c24xx/Kconfig"
1079 source "arch/arm/mach-socfpga/Kconfig"
1081 source "arch/arm/plat-spear/Kconfig"
1083 source "arch/arm/mach-s3c24xx/Kconfig"
1085 source "arch/arm/mach-s3c2412/Kconfig"
1086 source "arch/arm/mach-s3c2440/Kconfig"
1090 source "arch/arm/mach-s3c64xx/Kconfig"
1093 source "arch/arm/mach-s5p64x0/Kconfig"
1095 source "arch/arm/mach-s5pc100/Kconfig"
1097 source "arch/arm/mach-s5pv210/Kconfig"
1099 source "arch/arm/mach-exynos/Kconfig"
1101 source "arch/arm/mach-shmobile/Kconfig"
1103 source "arch/arm/mach-prima2/Kconfig"
1105 source "arch/arm/mach-tegra/Kconfig"
1107 source "arch/arm/mach-u300/Kconfig"
1109 source "arch/arm/mach-ux500/Kconfig"
1111 source "arch/arm/mach-versatile/Kconfig"
1113 source "arch/arm/mach-vexpress/Kconfig"
1114 source "arch/arm/plat-versatile/Kconfig"
1116 source "arch/arm/mach-w90x900/Kconfig"
1118 # Definitions to make life easier
1124 select GENERIC_CLOCKEVENTS
1130 select GENERIC_IRQ_CHIP
1133 config PLAT_ORION_LEGACY
1140 config PLAT_VERSATILE
1143 config ARM_TIMER_SP804
1146 select HAVE_SCHED_CLOCK
1148 source arch/arm/mm/Kconfig
1152 default 16 if ARCH_EP93XX
1156 bool "Enable iWMMXt support"
1157 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1158 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1160 Enable support for iWMMXt context switching at run time if
1161 running on a CPU that supports it.
1165 depends on CPU_XSCALE
1168 config MULTI_IRQ_HANDLER
1171 Allow each machine to specify it's own IRQ handler at run time.
1174 source "arch/arm/Kconfig-nommu"
1177 config ARM_ERRATA_326103
1178 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1181 Executing a SWP instruction to read-only memory does not set bit 11
1182 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1183 treat the access as a read, preventing a COW from occurring and
1184 causing the faulting task to livelock.
1186 config ARM_ERRATA_411920
1187 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1188 depends on CPU_V6 || CPU_V6K
1190 Invalidation of the Instruction Cache operation can
1191 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1192 It does not affect the MPCore. This option enables the ARM Ltd.
1193 recommended workaround.
1195 config ARM_ERRATA_430973
1196 bool "ARM errata: Stale prediction on replaced interworking branch"
1199 This option enables the workaround for the 430973 Cortex-A8
1200 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1201 interworking branch is replaced with another code sequence at the
1202 same virtual address, whether due to self-modifying code or virtual
1203 to physical address re-mapping, Cortex-A8 does not recover from the
1204 stale interworking branch prediction. This results in Cortex-A8
1205 executing the new code sequence in the incorrect ARM or Thumb state.
1206 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1207 and also flushes the branch target cache at every context switch.
1208 Note that setting specific bits in the ACTLR register may not be
1209 available in non-secure mode.
1211 config ARM_ERRATA_458693
1212 bool "ARM errata: Processor deadlock when a false hazard is created"
1215 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1216 erratum. For very specific sequences of memory operations, it is
1217 possible for a hazard condition intended for a cache line to instead
1218 be incorrectly associated with a different cache line. This false
1219 hazard might then cause a processor deadlock. The workaround enables
1220 the L1 caching of the NEON accesses and disables the PLD instruction
1221 in the ACTLR register. Note that setting specific bits in the ACTLR
1222 register may not be available in non-secure mode.
1224 config ARM_ERRATA_460075
1225 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1228 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1229 erratum. Any asynchronous access to the L2 cache may encounter a
1230 situation in which recent store transactions to the L2 cache are lost
1231 and overwritten with stale memory contents from external memory. The
1232 workaround disables the write-allocate mode for the L2 cache via the
1233 ACTLR register. Note that setting specific bits in the ACTLR register
1234 may not be available in non-secure mode.
1236 config ARM_ERRATA_742230
1237 bool "ARM errata: DMB operation may be faulty"
1238 depends on CPU_V7 && SMP
1240 This option enables the workaround for the 742230 Cortex-A9
1241 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1242 between two write operations may not ensure the correct visibility
1243 ordering of the two writes. This workaround sets a specific bit in
1244 the diagnostic register of the Cortex-A9 which causes the DMB
1245 instruction to behave as a DSB, ensuring the correct behaviour of
1248 config ARM_ERRATA_742231
1249 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1250 depends on CPU_V7 && SMP
1252 This option enables the workaround for the 742231 Cortex-A9
1253 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1254 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1255 accessing some data located in the same cache line, may get corrupted
1256 data due to bad handling of the address hazard when the line gets
1257 replaced from one of the CPUs at the same time as another CPU is
1258 accessing it. This workaround sets specific bits in the diagnostic
1259 register of the Cortex-A9 which reduces the linefill issuing
1260 capabilities of the processor.
1262 config PL310_ERRATA_588369
1263 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1264 depends on CACHE_L2X0
1266 The PL310 L2 cache controller implements three types of Clean &
1267 Invalidate maintenance operations: by Physical Address
1268 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1269 They are architecturally defined to behave as the execution of a
1270 clean operation followed immediately by an invalidate operation,
1271 both performing to the same memory location. This functionality
1272 is not correctly implemented in PL310 as clean lines are not
1273 invalidated as a result of these operations.
1275 config ARM_ERRATA_720789
1276 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1279 This option enables the workaround for the 720789 Cortex-A9 (prior to
1280 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1281 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1282 As a consequence of this erratum, some TLB entries which should be
1283 invalidated are not, resulting in an incoherency in the system page
1284 tables. The workaround changes the TLB flushing routines to invalidate
1285 entries regardless of the ASID.
1287 config PL310_ERRATA_727915
1288 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1289 depends on CACHE_L2X0
1291 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1292 operation (offset 0x7FC). This operation runs in background so that
1293 PL310 can handle normal accesses while it is in progress. Under very
1294 rare circumstances, due to this erratum, write data can be lost when
1295 PL310 treats a cacheable write transaction during a Clean &
1296 Invalidate by Way operation.
1298 config ARM_ERRATA_743622
1299 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1302 This option enables the workaround for the 743622 Cortex-A9
1303 (r2p*) erratum. Under very rare conditions, a faulty
1304 optimisation in the Cortex-A9 Store Buffer may lead to data
1305 corruption. This workaround sets a specific bit in the diagnostic
1306 register of the Cortex-A9 which disables the Store Buffer
1307 optimisation, preventing the defect from occurring. This has no
1308 visible impact on the overall performance or power consumption of the
1311 config ARM_ERRATA_751472
1312 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1315 This option enables the workaround for the 751472 Cortex-A9 (prior
1316 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1317 completion of a following broadcasted operation if the second
1318 operation is received by a CPU before the ICIALLUIS has completed,
1319 potentially leading to corrupted entries in the cache or TLB.
1321 config PL310_ERRATA_753970
1322 bool "PL310 errata: cache sync operation may be faulty"
1323 depends on CACHE_PL310
1325 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1327 Under some condition the effect of cache sync operation on
1328 the store buffer still remains when the operation completes.
1329 This means that the store buffer is always asked to drain and
1330 this prevents it from merging any further writes. The workaround
1331 is to replace the normal offset of cache sync operation (0x730)
1332 by another offset targeting an unmapped PL310 register 0x740.
1333 This has the same effect as the cache sync operation: store buffer
1334 drain and waiting for all buffers empty.
1336 config ARM_ERRATA_754322
1337 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1340 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1341 r3p*) erratum. A speculative memory access may cause a page table walk
1342 which starts prior to an ASID switch but completes afterwards. This
1343 can populate the micro-TLB with a stale entry which may be hit with
1344 the new ASID. This workaround places two dsb instructions in the mm
1345 switching code so that no page table walks can cross the ASID switch.
1347 config ARM_ERRATA_754327
1348 bool "ARM errata: no automatic Store Buffer drain"
1349 depends on CPU_V7 && SMP
1351 This option enables the workaround for the 754327 Cortex-A9 (prior to
1352 r2p0) erratum. The Store Buffer does not have any automatic draining
1353 mechanism and therefore a livelock may occur if an external agent
1354 continuously polls a memory location waiting to observe an update.
1355 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1356 written polling loops from denying visibility of updates to memory.
1358 config ARM_ERRATA_364296
1359 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1360 depends on CPU_V6 && !SMP
1362 This options enables the workaround for the 364296 ARM1136
1363 r0p2 erratum (possible cache data corruption with
1364 hit-under-miss enabled). It sets the undocumented bit 31 in
1365 the auxiliary control register and the FI bit in the control
1366 register, thus disabling hit-under-miss without putting the
1367 processor into full low interrupt latency mode. ARM11MPCore
1370 config ARM_ERRATA_764369
1371 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1372 depends on CPU_V7 && SMP
1374 This option enables the workaround for erratum 764369
1375 affecting Cortex-A9 MPCore with two or more processors (all
1376 current revisions). Under certain timing circumstances, a data
1377 cache line maintenance operation by MVA targeting an Inner
1378 Shareable memory region may fail to proceed up to either the
1379 Point of Coherency or to the Point of Unification of the
1380 system. This workaround adds a DSB instruction before the
1381 relevant cache maintenance functions and sets a specific bit
1382 in the diagnostic control register of the SCU.
1384 config PL310_ERRATA_769419
1385 bool "PL310 errata: no automatic Store Buffer drain"
1386 depends on CACHE_L2X0
1388 On revisions of the PL310 prior to r3p2, the Store Buffer does
1389 not automatically drain. This can cause normal, non-cacheable
1390 writes to be retained when the memory system is idle, leading
1391 to suboptimal I/O performance for drivers using coherent DMA.
1392 This option adds a write barrier to the cpu_idle loop so that,
1393 on systems with an outer cache, the store buffer is drained
1396 config ARM_ERRATA_775420
1397 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1400 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1401 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1402 operation aborts with MMU exception, it might cause the processor
1403 to deadlock. This workaround puts DSB before executing ISB if
1404 an abort may occur on cache maintenance.
1408 source "arch/arm/common/Kconfig"
1418 Find out whether you have ISA slots on your motherboard. ISA is the
1419 name of a bus system, i.e. the way the CPU talks to the other stuff
1420 inside your box. Other bus systems are PCI, EISA, MicroChannel
1421 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1422 newer boards don't support it. If you have ISA, say Y, otherwise N.
1424 # Select ISA DMA controller support
1429 # Select ISA DMA interface
1434 bool "PCI support" if MIGHT_HAVE_PCI
1436 Find out whether you have a PCI motherboard. PCI is the name of a
1437 bus system, i.e. the way the CPU talks to the other stuff inside
1438 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1439 VESA. If you have PCI, say Y, otherwise N.
1445 config PCI_NANOENGINE
1446 bool "BSE nanoEngine PCI support"
1447 depends on SA1100_NANOENGINE
1449 Enable PCI on the BSE nanoEngine board.
1454 # Select the host bridge type
1455 config PCI_HOST_VIA82C505
1457 depends on PCI && ARCH_SHARK
1460 config PCI_HOST_ITE8152
1462 depends on PCI && MACH_ARMCORE
1466 source "drivers/pci/Kconfig"
1468 source "drivers/pcmcia/Kconfig"
1472 menu "Kernel Features"
1477 This option should be selected by machines which have an SMP-
1480 The only effect of this option is to make the SMP-related
1481 options available to the user for configuration.
1484 bool "Symmetric Multi-Processing"
1485 depends on CPU_V6K || CPU_V7
1486 depends on GENERIC_CLOCKEVENTS
1489 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1490 select USE_GENERIC_SMP_HELPERS
1492 This enables support for systems with more than one CPU. If you have
1493 a system with only one CPU, like most personal computers, say N. If
1494 you have a system with more than one CPU, say Y.
1496 If you say N here, the kernel will run on single and multiprocessor
1497 machines, but will use only one CPU of a multiprocessor machine. If
1498 you say Y here, the kernel will run on many, but not all, single
1499 processor machines. On a single processor machine, the kernel will
1500 run faster if you say N here.
1502 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1503 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1504 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1506 If you don't know what to do here, say N.
1509 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1510 depends on EXPERIMENTAL
1511 depends on SMP && !XIP_KERNEL
1514 SMP kernels contain instructions which fail on non-SMP processors.
1515 Enabling this option allows the kernel to modify itself to make
1516 these instructions safe. Disabling it allows about 1K of space
1519 If you don't know what to do here, say Y.
1521 config ARM_CPU_TOPOLOGY
1522 bool "Support cpu topology definition"
1523 depends on SMP && CPU_V7
1526 Support ARM cpu topology definition. The MPIDR register defines
1527 affinity between processors which is then used to describe the cpu
1528 topology of an ARM System.
1531 bool "Multi-core scheduler support"
1532 depends on ARM_CPU_TOPOLOGY
1534 Multi-core scheduler support improves the CPU scheduler's decision
1535 making when dealing with multi-core CPU chips at a cost of slightly
1536 increased overhead in some places. If unsure say N here.
1539 bool "SMT scheduler support"
1540 depends on ARM_CPU_TOPOLOGY
1542 Improves the CPU scheduler's decision making when dealing with
1543 MultiThreading at a cost of slightly increased overhead in some
1544 places. If unsure say N here.
1549 This option enables support for the ARM system coherency unit
1551 config ARM_ARCH_TIMER
1552 bool "Architected timer support"
1555 This option enables support for the ARM architected timer
1561 This options enables support for the ARM timer and watchdog unit
1564 prompt "Memory split"
1567 Select the desired split between kernel and user memory.
1569 If you are not absolutely sure what you are doing, leave this
1573 bool "3G/1G user/kernel split"
1575 bool "2G/2G user/kernel split"
1577 bool "1G/3G user/kernel split"
1582 default 0x40000000 if VMSPLIT_1G
1583 default 0x80000000 if VMSPLIT_2G
1587 int "Maximum number of CPUs (2-32)"
1593 bool "Support for hot-pluggable CPUs"
1594 depends on SMP && HOTPLUG
1596 Say Y here to experiment with turning CPUs off and on. CPUs
1597 can be controlled through /sys/devices/system/cpu.
1600 bool "Use local timer interrupts"
1603 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1605 Enable support for local timers on SMP platforms, rather then the
1606 legacy IPI broadcast method. Local timers allows the system
1607 accounting to be spread across the timer interval, preventing a
1608 "thundering herd" at every timer tick.
1612 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1613 default 355 if ARCH_U8500
1614 default 264 if MACH_H4700
1615 default 512 if SOC_OMAP5
1616 default 288 if ARCH_VT8500
1619 Maximum number of GPIOs in the system.
1621 If unsure, leave the default value.
1623 source kernel/Kconfig.preempt
1627 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1628 ARCH_S5PV210 || ARCH_EXYNOS4
1629 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1630 default AT91_TIMER_HZ if ARCH_AT91
1631 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1634 config THUMB2_KERNEL
1635 bool "Compile the kernel in Thumb-2 mode"
1636 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1638 select ARM_ASM_UNIFIED
1641 By enabling this option, the kernel will be compiled in
1642 Thumb-2 mode. A compiler/assembler that understand the unified
1643 ARM-Thumb syntax is needed.
1647 config THUMB2_AVOID_R_ARM_THM_JUMP11
1648 bool "Work around buggy Thumb-2 short branch relocations in gas"
1649 depends on THUMB2_KERNEL && MODULES
1652 Various binutils versions can resolve Thumb-2 branches to
1653 locally-defined, preemptible global symbols as short-range "b.n"
1654 branch instructions.
1656 This is a problem, because there's no guarantee the final
1657 destination of the symbol, or any candidate locations for a
1658 trampoline, are within range of the branch. For this reason, the
1659 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1660 relocation in modules at all, and it makes little sense to add
1663 The symptom is that the kernel fails with an "unsupported
1664 relocation" error when loading some modules.
1666 Until fixed tools are available, passing
1667 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1668 code which hits this problem, at the cost of a bit of extra runtime
1669 stack usage in some cases.
1671 The problem is described in more detail at:
1672 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1674 Only Thumb-2 kernels are affected.
1676 Unless you are sure your tools don't have this problem, say Y.
1678 config ARM_ASM_UNIFIED
1682 bool "Use the ARM EABI to compile the kernel"
1684 This option allows for the kernel to be compiled using the latest
1685 ARM ABI (aka EABI). This is only useful if you are using a user
1686 space environment that is also compiled with EABI.
1688 Since there are major incompatibilities between the legacy ABI and
1689 EABI, especially with regard to structure member alignment, this
1690 option also changes the kernel syscall calling convention to
1691 disambiguate both ABIs and allow for backward compatibility support
1692 (selected with CONFIG_OABI_COMPAT).
1694 To use this you need GCC version 4.0.0 or later.
1697 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1698 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1701 This option preserves the old syscall interface along with the
1702 new (ARM EABI) one. It also provides a compatibility layer to
1703 intercept syscalls that have structure arguments which layout
1704 in memory differs between the legacy ABI and the new ARM EABI
1705 (only for non "thumb" binaries). This option adds a tiny
1706 overhead to all syscalls and produces a slightly larger kernel.
1707 If you know you'll be using only pure EABI user space then you
1708 can say N here. If this option is not selected and you attempt
1709 to execute a legacy ABI binary then the result will be
1710 UNPREDICTABLE (in fact it can be predicted that it won't work
1711 at all). If in doubt say Y.
1713 config ARCH_HAS_HOLES_MEMORYMODEL
1716 config ARCH_SPARSEMEM_ENABLE
1719 config ARCH_SPARSEMEM_DEFAULT
1720 def_bool ARCH_SPARSEMEM_ENABLE
1722 config ARCH_SELECT_MEMORY_MODEL
1723 def_bool ARCH_SPARSEMEM_ENABLE
1725 config HAVE_ARCH_PFN_VALID
1726 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1729 bool "High Memory Support"
1732 The address space of ARM processors is only 4 Gigabytes large
1733 and it has to accommodate user address space, kernel address
1734 space as well as some memory mapped IO. That means that, if you
1735 have a large amount of physical memory and/or IO, not all of the
1736 memory can be "permanently mapped" by the kernel. The physical
1737 memory that is not permanently mapped is called "high memory".
1739 Depending on the selected kernel/user memory split, minimum
1740 vmalloc space and actual amount of RAM, you may not need this
1741 option which should result in a slightly faster kernel.
1746 bool "Allocate 2nd-level pagetables from highmem"
1749 config HW_PERF_EVENTS
1750 bool "Enable hardware performance counter support for perf events"
1751 depends on PERF_EVENTS
1754 Enable hardware performance counter support for perf events. If
1755 disabled, perf events will use software events only.
1759 config FORCE_MAX_ZONEORDER
1760 int "Maximum zone order" if ARCH_SHMOBILE
1761 range 11 64 if ARCH_SHMOBILE
1762 default "12" if SOC_AM33XX
1763 default "9" if SA1111
1766 The kernel memory allocator divides physically contiguous memory
1767 blocks into "zones", where each zone is a power of two number of
1768 pages. This option selects the largest power of two that the kernel
1769 keeps in the memory allocator. If you need to allocate very large
1770 blocks of physically contiguous memory, then you may need to
1771 increase this value.
1773 This config option is actually maximum order plus one. For example,
1774 a value of 11 means that the largest free memory block is 2^10 pages.
1776 config ALIGNMENT_TRAP
1778 depends on CPU_CP15_MMU
1779 default y if !ARCH_EBSA110
1780 select HAVE_PROC_CPU if PROC_FS
1782 ARM processors cannot fetch/store information which is not
1783 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1784 address divisible by 4. On 32-bit ARM processors, these non-aligned
1785 fetch/store instructions will be emulated in software if you say
1786 here, which has a severe performance impact. This is necessary for
1787 correct operation of some network protocols. With an IP-only
1788 configuration it is safe to say N, otherwise say Y.
1790 config UACCESS_WITH_MEMCPY
1791 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1793 default y if CPU_FEROCEON
1795 Implement faster copy_to_user and clear_user methods for CPU
1796 cores where a 8-word STM instruction give significantly higher
1797 memory write throughput than a sequence of individual 32bit stores.
1799 A possible side effect is a slight increase in scheduling latency
1800 between threads sharing the same address space if they invoke
1801 such copy operations with large buffers.
1803 However, if the CPU data cache is using a write-allocate mode,
1804 this option is unlikely to provide any performance gain.
1808 prompt "Enable seccomp to safely compute untrusted bytecode"
1810 This kernel feature is useful for number crunching applications
1811 that may need to compute untrusted bytecode during their
1812 execution. By using pipes or other transports made available to
1813 the process as file descriptors supporting the read/write
1814 syscalls, it's possible to isolate those applications in
1815 their own address space using seccomp. Once seccomp is
1816 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1817 and the task is only allowed to execute a few safe syscalls
1818 defined by each seccomp mode.
1820 config CC_STACKPROTECTOR
1821 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1822 depends on EXPERIMENTAL
1824 This option turns on the -fstack-protector GCC feature. This
1825 feature puts, at the beginning of functions, a canary value on
1826 the stack just before the return address, and validates
1827 the value just before actually returning. Stack based buffer
1828 overflows (that need to overwrite this return address) now also
1829 overwrite the canary, which gets detected and the attack is then
1830 neutralized via a kernel panic.
1831 This feature requires gcc version 4.2 or above.
1838 bool "Xen guest support on ARM (EXPERIMENTAL)"
1839 depends on EXPERIMENTAL && ARM && OF
1840 depends on CPU_V7 && !CPU_V6
1842 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1849 bool "Flattened Device Tree support"
1852 select OF_EARLY_FLATTREE
1854 Include support for flattened device tree machine descriptions.
1857 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1860 This is the traditional way of passing data to the kernel at boot
1861 time. If you are solely relying on the flattened device tree (or
1862 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1863 to remove ATAGS support from your kernel binary. If unsure,
1866 config DEPRECATED_PARAM_STRUCT
1867 bool "Provide old way to pass kernel parameters"
1870 This was deprecated in 2001 and announced to live on for 5 years.
1871 Some old boot loaders still use this way.
1873 # Compressed boot loader in ROM. Yes, we really want to ask about
1874 # TEXT and BSS so we preserve their values in the config files.
1875 config ZBOOT_ROM_TEXT
1876 hex "Compressed ROM boot loader base address"
1879 The physical address at which the ROM-able zImage is to be
1880 placed in the target. Platforms which normally make use of
1881 ROM-able zImage formats normally set this to a suitable
1882 value in their defconfig file.
1884 If ZBOOT_ROM is not enabled, this has no effect.
1886 config ZBOOT_ROM_BSS
1887 hex "Compressed ROM boot loader BSS address"
1890 The base address of an area of read/write memory in the target
1891 for the ROM-able zImage which must be available while the
1892 decompressor is running. It must be large enough to hold the
1893 entire decompressed kernel plus an additional 128 KiB.
1894 Platforms which normally make use of ROM-able zImage formats
1895 normally set this to a suitable value in their defconfig file.
1897 If ZBOOT_ROM is not enabled, this has no effect.
1900 bool "Compressed boot loader in ROM/flash"
1901 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1903 Say Y here if you intend to execute your compressed kernel image
1904 (zImage) directly from ROM or flash. If unsure, say N.
1907 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1908 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1909 default ZBOOT_ROM_NONE
1911 Include experimental SD/MMC loading code in the ROM-able zImage.
1912 With this enabled it is possible to write the ROM-able zImage
1913 kernel image to an MMC or SD card and boot the kernel straight
1914 from the reset vector. At reset the processor Mask ROM will load
1915 the first part of the ROM-able zImage which in turn loads the
1916 rest the kernel image to RAM.
1918 config ZBOOT_ROM_NONE
1919 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1921 Do not load image from SD or MMC
1923 config ZBOOT_ROM_MMCIF
1924 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1926 Load image from MMCIF hardware block.
1928 config ZBOOT_ROM_SH_MOBILE_SDHI
1929 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1931 Load image from SDHI hardware block
1935 config ARM_APPENDED_DTB
1936 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1937 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1939 With this option, the boot code will look for a device tree binary
1940 (DTB) appended to zImage
1941 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1943 This is meant as a backward compatibility convenience for those
1944 systems with a bootloader that can't be upgraded to accommodate
1945 the documented boot protocol using a device tree.
1947 Beware that there is very little in terms of protection against
1948 this option being confused by leftover garbage in memory that might
1949 look like a DTB header after a reboot if no actual DTB is appended
1950 to zImage. Do not leave this option active in a production kernel
1951 if you don't intend to always append a DTB. Proper passing of the
1952 location into r2 of a bootloader provided DTB is always preferable
1955 config ARM_ATAG_DTB_COMPAT
1956 bool "Supplement the appended DTB with traditional ATAG information"
1957 depends on ARM_APPENDED_DTB
1959 Some old bootloaders can't be updated to a DTB capable one, yet
1960 they provide ATAGs with memory configuration, the ramdisk address,
1961 the kernel cmdline string, etc. Such information is dynamically
1962 provided by the bootloader and can't always be stored in a static
1963 DTB. To allow a device tree enabled kernel to be used with such
1964 bootloaders, this option allows zImage to extract the information
1965 from the ATAG list and store it at run time into the appended DTB.
1968 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1969 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1971 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1972 bool "Use bootloader kernel arguments if available"
1974 Uses the command-line options passed by the boot loader instead of
1975 the device tree bootargs property. If the boot loader doesn't provide
1976 any, the device tree bootargs property will be used.
1978 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1979 bool "Extend with bootloader kernel arguments"
1981 The command-line arguments provided by the boot loader will be
1982 appended to the the device tree bootargs property.
1987 string "Default kernel command string"
1990 On some architectures (EBSA110 and CATS), there is currently no way
1991 for the boot loader to pass arguments to the kernel. For these
1992 architectures, you should supply some command-line options at build
1993 time by entering them here. As a minimum, you should specify the
1994 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1997 prompt "Kernel command line type" if CMDLINE != ""
1998 default CMDLINE_FROM_BOOTLOADER
2001 config CMDLINE_FROM_BOOTLOADER
2002 bool "Use bootloader kernel arguments if available"
2004 Uses the command-line options passed by the boot loader. If
2005 the boot loader doesn't provide any, the default kernel command
2006 string provided in CMDLINE will be used.
2008 config CMDLINE_EXTEND
2009 bool "Extend bootloader kernel arguments"
2011 The command-line arguments provided by the boot loader will be
2012 appended to the default kernel command string.
2014 config CMDLINE_FORCE
2015 bool "Always use the default kernel command string"
2017 Always use the default kernel command string, even if the boot
2018 loader passes other arguments to the kernel.
2019 This is useful if you cannot or don't want to change the
2020 command-line options your boot loader passes to the kernel.
2024 bool "Kernel Execute-In-Place from ROM"
2025 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2027 Execute-In-Place allows the kernel to run from non-volatile storage
2028 directly addressable by the CPU, such as NOR flash. This saves RAM
2029 space since the text section of the kernel is not loaded from flash
2030 to RAM. Read-write sections, such as the data section and stack,
2031 are still copied to RAM. The XIP kernel is not compressed since
2032 it has to run directly from flash, so it will take more space to
2033 store it. The flash address used to link the kernel object files,
2034 and for storing it, is configuration dependent. Therefore, if you
2035 say Y here, you must know the proper physical address where to
2036 store the kernel image depending on your own flash memory usage.
2038 Also note that the make target becomes "make xipImage" rather than
2039 "make zImage" or "make Image". The final kernel binary to put in
2040 ROM memory will be arch/arm/boot/xipImage.
2044 config XIP_PHYS_ADDR
2045 hex "XIP Kernel Physical Location"
2046 depends on XIP_KERNEL
2047 default "0x00080000"
2049 This is the physical address in your flash memory the kernel will
2050 be linked for and stored to. This address is dependent on your
2054 bool "Kexec system call (EXPERIMENTAL)"
2055 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2057 kexec is a system call that implements the ability to shutdown your
2058 current kernel, and to start another kernel. It is like a reboot
2059 but it is independent of the system firmware. And like a reboot
2060 you can start any kernel with it, not just Linux.
2062 It is an ongoing process to be certain the hardware in a machine
2063 is properly shutdown, so do not be surprised if this code does not
2064 initially work for you. It may help to enable device hotplugging
2068 bool "Export atags in procfs"
2069 depends on ATAGS && KEXEC
2072 Should the atags used to boot the kernel be exported in an "atags"
2073 file in procfs. Useful with kexec.
2076 bool "Build kdump crash kernel (EXPERIMENTAL)"
2077 depends on EXPERIMENTAL
2079 Generate crash dump after being started by kexec. This should
2080 be normally only set in special crash dump kernels which are
2081 loaded in the main kernel with kexec-tools into a specially
2082 reserved region and then later executed after a crash by
2083 kdump/kexec. The crash dump kernel must be compiled to a
2084 memory address not used by the main kernel
2086 For more details see Documentation/kdump/kdump.txt
2088 config AUTO_ZRELADDR
2089 bool "Auto calculation of the decompressed kernel image address"
2090 depends on !ZBOOT_ROM && !ARCH_U300
2092 ZRELADDR is the physical address where the decompressed kernel
2093 image will be placed. If AUTO_ZRELADDR is selected, the address
2094 will be determined at run-time by masking the current IP with
2095 0xf8000000. This assumes the zImage being placed in the first 128MB
2096 from start of memory.
2100 menu "CPU Power Management"
2104 source "drivers/cpufreq/Kconfig"
2107 tristate "CPUfreq driver for i.MX CPUs"
2108 depends on ARCH_MXC && CPU_FREQ
2109 select CPU_FREQ_TABLE
2111 This enables the CPUfreq driver for i.MX CPUs.
2113 config CPU_FREQ_SA1100
2116 config CPU_FREQ_SA1110
2119 config CPU_FREQ_INTEGRATOR
2120 tristate "CPUfreq driver for ARM Integrator CPUs"
2121 depends on ARCH_INTEGRATOR && CPU_FREQ
2124 This enables the CPUfreq driver for ARM Integrator CPUs.
2126 For details, take a look at <file:Documentation/cpu-freq>.
2132 depends on CPU_FREQ && ARCH_PXA && PXA25x
2134 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2135 select CPU_FREQ_TABLE
2140 Internal configuration node for common cpufreq on Samsung SoC
2142 config CPU_FREQ_S3C24XX
2143 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2144 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2147 This enables the CPUfreq driver for the Samsung S3C24XX family
2150 For details, take a look at <file:Documentation/cpu-freq>.
2154 config CPU_FREQ_S3C24XX_PLL
2155 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2156 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2158 Compile in support for changing the PLL frequency from the
2159 S3C24XX series CPUfreq driver. The PLL takes time to settle
2160 after a frequency change, so by default it is not enabled.
2162 This also means that the PLL tables for the selected CPU(s) will
2163 be built which may increase the size of the kernel image.
2165 config CPU_FREQ_S3C24XX_DEBUG
2166 bool "Debug CPUfreq Samsung driver core"
2167 depends on CPU_FREQ_S3C24XX
2169 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2171 config CPU_FREQ_S3C24XX_IODEBUG
2172 bool "Debug CPUfreq Samsung driver IO timing"
2173 depends on CPU_FREQ_S3C24XX
2175 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2177 config CPU_FREQ_S3C24XX_DEBUGFS
2178 bool "Export debugfs for CPUFreq"
2179 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2181 Export status information via debugfs.
2185 source "drivers/cpuidle/Kconfig"
2189 menu "Floating point emulation"
2191 comment "At least one emulation must be selected"
2194 bool "NWFPE math emulation"
2195 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2197 Say Y to include the NWFPE floating point emulator in the kernel.
2198 This is necessary to run most binaries. Linux does not currently
2199 support floating point hardware so you need to say Y here even if
2200 your machine has an FPA or floating point co-processor podule.
2202 You may say N here if you are going to load the Acorn FPEmulator
2203 early in the bootup.
2206 bool "Support extended precision"
2207 depends on FPE_NWFPE
2209 Say Y to include 80-bit support in the kernel floating-point
2210 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2211 Note that gcc does not generate 80-bit operations by default,
2212 so in most cases this option only enlarges the size of the
2213 floating point emulator without any good reason.
2215 You almost surely want to say N here.
2218 bool "FastFPE math emulation (EXPERIMENTAL)"
2219 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2221 Say Y here to include the FAST floating point emulator in the kernel.
2222 This is an experimental much faster emulator which now also has full
2223 precision for the mantissa. It does not support any exceptions.
2224 It is very simple, and approximately 3-6 times faster than NWFPE.
2226 It should be sufficient for most programs. It may be not suitable
2227 for scientific calculations, but you have to check this for yourself.
2228 If you do not feel you need a faster FP emulation you should better
2232 bool "VFP-format floating point maths"
2233 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2235 Say Y to include VFP support code in the kernel. This is needed
2236 if your hardware includes a VFP unit.
2238 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2239 release notes and additional status information.
2241 Say N if your target does not have VFP hardware.
2249 bool "Advanced SIMD (NEON) Extension support"
2250 depends on VFPv3 && CPU_V7
2252 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2257 menu "Userspace binary formats"
2259 source "fs/Kconfig.binfmt"
2262 tristate "RISC OS personality"
2265 Say Y here to include the kernel code necessary if you want to run
2266 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2267 experimental; if this sounds frightening, say N and sleep in peace.
2268 You can also say M here to compile this support as a module (which
2269 will be called arthur).
2273 menu "Power management options"
2275 source "kernel/power/Kconfig"
2277 config ARCH_SUSPEND_POSSIBLE
2278 depends on !ARCH_S5PC100
2279 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2280 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2283 config ARM_CPU_SUSPEND
2288 source "net/Kconfig"
2290 source "drivers/Kconfig"
2294 source "arch/arm/Kconfig.debug"
2296 source "security/Kconfig"
2298 source "crypto/Kconfig"
2300 source "lib/Kconfig"