4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
52 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
53 select MODULES_USE_ELF_REL
55 The ARM series is a line of low-power-consumption RISC chip designs
56 licensed by ARM Ltd and targeted at embedded applications and
57 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
58 manufactured, but legacy ARM-based PC hardware remains popular in
59 Europe. There is an ARM Linux project with a web page at
60 <http://www.arm.linux.org.uk/>.
62 config ARM_HAS_SG_CHAIN
65 config NEED_SG_DMA_LENGTH
68 config ARM_DMA_USE_IOMMU
69 select NEED_SG_DMA_LENGTH
70 select ARM_HAS_SG_CHAIN
79 config SYS_SUPPORTS_APM_EMULATION
87 select GENERIC_ALLOCATOR
98 The Extended Industry Standard Architecture (EISA) bus was
99 developed as an open alternative to the IBM MicroChannel bus.
101 The EISA bus provided some of the features of the IBM MicroChannel
102 bus while maintaining backward compatibility with cards made for
103 the older ISA bus. The EISA bus saw limited use between 1988 and
104 1995 when it was made obsolete by the PCI bus.
106 Say Y here if you are building a kernel for an EISA-based machine.
113 config STACKTRACE_SUPPORT
117 config HAVE_LATENCYTOP_SUPPORT
122 config LOCKDEP_SUPPORT
126 config TRACE_IRQFLAGS_SUPPORT
130 config RWSEM_GENERIC_SPINLOCK
134 config RWSEM_XCHGADD_ALGORITHM
137 config ARCH_HAS_ILOG2_U32
140 config ARCH_HAS_ILOG2_U64
143 config ARCH_HAS_CPUFREQ
146 Internal node to signify that the ARCH has CPUFREQ support
147 and that the relevant menu configurations are displayed for
150 config GENERIC_HWEIGHT
154 config GENERIC_CALIBRATE_DELAY
158 config ARCH_MAY_HAVE_PC_FDC
164 config NEED_DMA_MAP_STATE
167 config ARCH_HAS_DMA_SET_COHERENT_MASK
170 config GENERIC_ISA_DMA
176 config NEED_RET_TO_USER
184 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
185 default DRAM_BASE if REMAP_VECTORS_TO_RAM
188 The base address of exception vectors.
190 config ARM_PATCH_PHYS_VIRT
191 bool "Patch physical to virtual translations at runtime" if EMBEDDED
193 depends on !XIP_KERNEL && MMU
194 depends on !ARCH_REALVIEW || !SPARSEMEM
196 Patch phys-to-virt and virt-to-phys translation functions at
197 boot and module load time according to the position of the
198 kernel in system memory.
200 This can only be used with non-XIP MMU kernels where the base
201 of physical memory is at a 16MB boundary.
203 Only disable this option if you know that you do not require
204 this feature (eg, building a kernel for a single machine) and
205 you need to shrink the kernel to the minimal size.
207 config NEED_MACH_IO_H
210 Select this when mach/io.h is required to provide special
211 definitions for this platform. The need for mach/io.h should
212 be avoided when possible.
214 config NEED_MACH_MEMORY_H
217 Select this when mach/memory.h is required to provide special
218 definitions for this platform. The need for mach/memory.h should
219 be avoided when possible.
222 hex "Physical address of main memory" if MMU
223 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
224 default DRAM_BASE if !MMU
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
240 bool "MMU-based Paged Memory Management Support"
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
251 prompt "ARM system type"
252 default ARCH_VERSATILE
255 bool "Altera SOCFPGA family"
256 select ARCH_WANT_OPTIONAL_GPIOLIB
264 select DW_APB_TIMER_OF
265 select GENERIC_CLOCKEVENTS
266 select GPIO_PL061 if GPIOLIB
271 This enables support for Altera SOCFPGA Cyclone V platform
273 config ARCH_INTEGRATOR
274 bool "ARM Ltd. Integrator family"
276 select ARCH_HAS_CPUFREQ
278 select COMMON_CLK_VERSATILE
281 select GENERIC_CLOCKEVENTS
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_FPGA_IRQ
284 select NEED_MACH_MEMORY_H
286 select MULTI_IRQ_HANDLER
288 Support for ARM's Integrator platform.
291 bool "ARM Ltd. RealView family"
294 select COMMON_CLK_VERSATILE
296 select GENERIC_CLOCKEVENTS
297 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select PLAT_VERSATILE
299 select PLAT_VERSATILE_CLCD
300 select ARM_TIMER_SP804
301 select GPIO_PL061 if GPIOLIB
302 select NEED_MACH_MEMORY_H
304 This enables support for ARM Ltd RealView boards.
306 config ARCH_VERSATILE
307 bool "ARM Ltd. Versatile family"
311 select HAVE_MACH_CLKDEV
313 select GENERIC_CLOCKEVENTS
314 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select PLAT_VERSATILE
316 select PLAT_VERSATILE_CLOCK
317 select PLAT_VERSATILE_CLCD
318 select PLAT_VERSATILE_FPGA_IRQ
319 select ARM_TIMER_SP804
321 This enables support for ARM Ltd Versatile board.
324 bool "ARM Ltd. Versatile Express family"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select ARM_TIMER_SP804
330 select GENERIC_CLOCKEVENTS
332 select HAVE_PATA_PLATFORM
335 select PLAT_VERSATILE
336 select PLAT_VERSATILE_CLCD
337 select REGULATOR_FIXED_VOLTAGE if REGULATOR
339 This enables support for the ARM Ltd Versatile Express boards.
343 select ARCH_REQUIRE_GPIOLIB
347 select NEED_MACH_IO_H if PCCARD
349 This enables support for systems based on Atmel
350 AT91RM9200 and AT91SAM9* processors.
353 bool "Broadcom BCMRING"
357 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select ARCH_WANT_OPTIONAL_GPIOLIB
362 Support for Broadcom's BCMRing platform.
365 bool "Calxeda Highbank-based"
366 select ARCH_WANT_OPTIONAL_GPIOLIB
369 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
380 Support for the Calxeda Highbank SoC based boards.
383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
385 select ARCH_USES_GETTIMEOFFSET
386 select NEED_MACH_MEMORY_H
388 Support for Cirrus Logic 711x/721x/731x based boards.
391 bool "Cavium Networks CNS3XXX family"
393 select GENERIC_CLOCKEVENTS
395 select MIGHT_HAVE_CACHE_L2X0
396 select MIGHT_HAVE_PCI
397 select PCI_DOMAINS if PCI
399 Support for Cavium Networks CNS3XXX platform.
402 bool "Cortina Systems Gemini"
404 select ARCH_REQUIRE_GPIOLIB
405 select ARCH_USES_GETTIMEOFFSET
407 Support for the Cortina Systems Gemini family SoCs
412 select ARCH_REQUIRE_GPIOLIB
413 select GENERIC_CLOCKEVENTS
415 select GENERIC_IRQ_CHIP
416 select MIGHT_HAVE_CACHE_L2X0
421 Support for CSR SiRFprimaII/Marco/Polo platforms
428 select ARCH_USES_GETTIMEOFFSET
429 select NEED_MACH_IO_H
430 select NEED_MACH_MEMORY_H
432 This is an evaluation board for the StrongARM processor available
433 from Digital. It has limited hardware on-board, including an
434 Ethernet interface, two PCMCIA sockets, two serial ports and a
443 select ARCH_REQUIRE_GPIOLIB
444 select ARCH_HAS_HOLES_MEMORYMODEL
445 select ARCH_USES_GETTIMEOFFSET
446 select NEED_MACH_MEMORY_H
448 This enables support for the Cirrus EP93xx series of CPUs.
450 config ARCH_FOOTBRIDGE
454 select GENERIC_CLOCKEVENTS
456 select NEED_MACH_IO_H if !MMU
457 select NEED_MACH_MEMORY_H
459 Support for systems based on the DC21285 companion chip
460 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
463 bool "Freescale MXC/iMX-based"
464 select GENERIC_CLOCKEVENTS
465 select ARCH_REQUIRE_GPIOLIB
468 select GENERIC_IRQ_CHIP
469 select MULTI_IRQ_HANDLER
473 Support for Freescale MXC/iMX-based family of processors
476 bool "Freescale MXS-based"
477 select GENERIC_CLOCKEVENTS
478 select ARCH_REQUIRE_GPIOLIB
482 select HAVE_CLK_PREPARE
486 Support for Freescale MXS-based family of processors
489 bool "Hilscher NetX based"
493 select GENERIC_CLOCKEVENTS
495 This enables support for systems based on the Hilscher NetX Soc
498 bool "Hynix HMS720x-based"
501 select ARCH_USES_GETTIMEOFFSET
503 This enables support for systems based on the Hynix HMS720x
511 select ARCH_SUPPORTS_MSI
513 select NEED_MACH_MEMORY_H
514 select NEED_RET_TO_USER
516 Support for Intel's IOP13XX (XScale) family of processors.
522 select NEED_RET_TO_USER
525 select ARCH_REQUIRE_GPIOLIB
527 Support for Intel's 80219 and IOP32X (XScale) family of
534 select NEED_RET_TO_USER
537 select ARCH_REQUIRE_GPIOLIB
539 Support for Intel's IOP33X (XScale) family of processors.
544 select ARCH_HAS_DMA_SET_COHERENT_MASK
547 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
549 select MIGHT_HAVE_PCI
550 select NEED_MACH_IO_H
551 select DMABOUNCE if PCI
553 Support for Intel's IXP4XX (XScale) family of processors.
556 bool "Marvell SOCs with Device Tree support"
557 select GENERIC_CLOCKEVENTS
558 select MULTI_IRQ_HANDLER
561 select GENERIC_IRQ_CHIP
565 Support for the Marvell SoC Family with device tree support
571 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
575 Support for the Marvell Dove SoC 88AP510
578 bool "Marvell Kirkwood"
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
585 Support for the following Marvell Kirkwood series SoCs:
586 88F6180, 88F6192 and 88F6281.
592 select ARCH_REQUIRE_GPIOLIB
595 select USB_ARCH_HAS_OHCI
597 select GENERIC_CLOCKEVENTS
601 Support for the NXP LPC32XX family of processors
604 bool "Marvell MV78xx0"
607 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
611 Support for the following Marvell MV78xx0 series SoCs:
619 select ARCH_REQUIRE_GPIOLIB
620 select GENERIC_CLOCKEVENTS
623 Support for the following Marvell Orion 5x series SoCs:
624 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
625 Orion-2 (5281), Orion-1-90 (6183).
628 bool "Marvell PXA168/910/MMP2"
630 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
637 select GENERIC_ALLOCATOR
639 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
642 bool "Micrel/Kendin KS8695"
644 select ARCH_REQUIRE_GPIOLIB
645 select NEED_MACH_MEMORY_H
647 select GENERIC_CLOCKEVENTS
649 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
650 System-on-Chip devices.
653 bool "Nuvoton W90X900 CPU"
655 select ARCH_REQUIRE_GPIOLIB
658 select GENERIC_CLOCKEVENTS
660 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
661 At present, the w90x900 has been renamed nuc900, regarding
662 the ARM series product line, you can login the following
663 link address to know more.
665 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
666 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
672 select GENERIC_CLOCKEVENTS
676 select MIGHT_HAVE_CACHE_L2X0
677 select ARCH_HAS_CPUFREQ
681 This enables support for NVIDIA Tegra based systems (Tegra APX,
682 Tegra 6xx and Tegra 2 series).
684 config ARCH_PICOXCELL
685 bool "Picochip picoXcell"
686 select ARCH_REQUIRE_GPIOLIB
687 select ARM_PATCH_PHYS_VIRT
691 select DW_APB_TIMER_OF
692 select GENERIC_CLOCKEVENTS
699 This enables support for systems based on the Picochip picoXcell
700 family of Femtocell devices. The picoxcell support requires device tree
704 bool "PXA2xx/PXA3xx-based"
707 select ARCH_HAS_CPUFREQ
710 select ARCH_REQUIRE_GPIOLIB
711 select GENERIC_CLOCKEVENTS
716 select MULTI_IRQ_HANDLER
717 select ARM_CPU_SUSPEND if PM
720 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
725 select GENERIC_CLOCKEVENTS
726 select ARCH_REQUIRE_GPIOLIB
729 Support for Qualcomm MSM/QSD based systems. This runs on the
730 apps processor of the MSM/QSD and depends on a shared memory
731 interface to the modem processor which runs the baseband
732 stack and controls some vital subsystems
733 (clock and power control, etc).
736 bool "Renesas SH-Mobile / R-Mobile"
739 select HAVE_MACH_CLKDEV
741 select GENERIC_CLOCKEVENTS
742 select MIGHT_HAVE_CACHE_L2X0
745 select MULTI_IRQ_HANDLER
746 select PM_GENERIC_DOMAINS if PM
747 select NEED_MACH_MEMORY_H
749 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
755 select ARCH_MAY_HAVE_PC_FDC
756 select HAVE_PATA_PLATFORM
759 select ARCH_SPARSEMEM_ENABLE
760 select ARCH_USES_GETTIMEOFFSET
762 select NEED_MACH_IO_H
763 select NEED_MACH_MEMORY_H
765 On the Acorn Risc-PC, Linux can support the internal IDE disk and
766 CD-ROM interface, serial and parallel port, and the floppy drive.
773 select ARCH_SPARSEMEM_ENABLE
775 select ARCH_HAS_CPUFREQ
777 select GENERIC_CLOCKEVENTS
779 select ARCH_REQUIRE_GPIOLIB
781 select NEED_MACH_MEMORY_H
784 Support for StrongARM 11x0 based boards.
787 bool "Samsung S3C24XX SoCs"
789 select ARCH_HAS_CPUFREQ
792 select ARCH_USES_GETTIMEOFFSET
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C_RTC if RTC_CLASS
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select NEED_MACH_IO_H
798 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
799 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
800 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
801 Samsung SMDK2410 development board (and derivatives).
804 bool "Samsung S3C64XX"
812 select ARCH_USES_GETTIMEOFFSET
813 select ARCH_HAS_CPUFREQ
814 select ARCH_REQUIRE_GPIOLIB
815 select SAMSUNG_CLKSRC
816 select SAMSUNG_IRQ_VIC_TIMER
817 select S3C_GPIO_TRACK
819 select USB_ARCH_HAS_OHCI
820 select SAMSUNG_GPIOLIB_4BIT
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 Samsung S3C64XX series based systems
827 bool "Samsung S5P6440 S5P6450"
833 select HAVE_S3C2410_WATCHDOG if WATCHDOG
834 select GENERIC_CLOCKEVENTS
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C_RTC if RTC_CLASS
838 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
842 bool "Samsung S5PC100"
847 select ARCH_USES_GETTIMEOFFSET
848 select HAVE_S3C2410_I2C if I2C
849 select HAVE_S3C_RTC if RTC_CLASS
850 select HAVE_S3C2410_WATCHDOG if WATCHDOG
852 Samsung S5PC100 series based systems
855 bool "Samsung S5PV210/S5PC110"
857 select ARCH_SPARSEMEM_ENABLE
858 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_HAS_CPUFREQ
864 select GENERIC_CLOCKEVENTS
865 select HAVE_S3C2410_I2C if I2C
866 select HAVE_S3C_RTC if RTC_CLASS
867 select HAVE_S3C2410_WATCHDOG if WATCHDOG
868 select NEED_MACH_MEMORY_H
870 Samsung S5PV210/S5PC110 series based systems
873 bool "SAMSUNG EXYNOS"
875 select ARCH_SPARSEMEM_ENABLE
876 select ARCH_HAS_HOLES_MEMORYMODEL
880 select ARCH_HAS_CPUFREQ
881 select GENERIC_CLOCKEVENTS
882 select HAVE_S3C_RTC if RTC_CLASS
883 select HAVE_S3C2410_I2C if I2C
884 select HAVE_S3C2410_WATCHDOG if WATCHDOG
885 select NEED_MACH_MEMORY_H
887 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
896 select ARCH_USES_GETTIMEOFFSET
897 select NEED_MACH_MEMORY_H
899 Support for the StrongARM based Digital DNARD machine, also known
900 as "Shark" (<http://www.shark-linux.de/shark.html>).
903 bool "ST-Ericsson U300 Series"
909 select ARM_PATCH_PHYS_VIRT
911 select GENERIC_CLOCKEVENTS
915 select ARCH_REQUIRE_GPIOLIB
918 Support for ST-Ericsson U300 series mobile platforms.
921 bool "ST-Ericsson U8500 Series"
925 select GENERIC_CLOCKEVENTS
927 select ARCH_REQUIRE_GPIOLIB
928 select ARCH_HAS_CPUFREQ
930 select MIGHT_HAVE_CACHE_L2X0
932 Support for ST-Ericsson's Ux500 architecture
935 bool "STMicroelectronics Nomadik"
940 select GENERIC_CLOCKEVENTS
942 select PINCTRL_STN8815
943 select MIGHT_HAVE_CACHE_L2X0
944 select ARCH_REQUIRE_GPIOLIB
946 Support for the Nomadik platform by ST-Ericsson
950 select GENERIC_CLOCKEVENTS
951 select ARCH_REQUIRE_GPIOLIB
955 select GENERIC_ALLOCATOR
956 select GENERIC_IRQ_CHIP
957 select ARCH_HAS_HOLES_MEMORYMODEL
959 Support for TI's DaVinci platform.
965 select ARCH_REQUIRE_GPIOLIB
966 select ARCH_HAS_CPUFREQ
968 select GENERIC_CLOCKEVENTS
969 select ARCH_HAS_HOLES_MEMORYMODEL
971 Support for TI's OMAP platform (OMAP1/2/3/4).
976 select ARCH_REQUIRE_GPIOLIB
980 select GENERIC_CLOCKEVENTS
983 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
986 bool "VIA/WonderMedia 85xx"
989 select ARCH_HAS_CPUFREQ
990 select GENERIC_CLOCKEVENTS
991 select ARCH_REQUIRE_GPIOLIB
993 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
996 bool "Xilinx Zynq ARM Cortex A9 Platform"
998 select GENERIC_CLOCKEVENTS
1003 select MIGHT_HAVE_CACHE_L2X0
1006 Support for Xilinx Zynq ARM Cortex A9 Platform
1010 # This is sorted alphabetically by mach-* pathname. However, plat-*
1011 # Kconfigs may be included either alphabetically (according to the
1012 # plat- suffix) or along side the corresponding mach-* source.
1014 source "arch/arm/mach-mvebu/Kconfig"
1016 source "arch/arm/mach-at91/Kconfig"
1018 source "arch/arm/mach-bcmring/Kconfig"
1020 source "arch/arm/mach-clps711x/Kconfig"
1022 source "arch/arm/mach-cns3xxx/Kconfig"
1024 source "arch/arm/mach-davinci/Kconfig"
1026 source "arch/arm/mach-dove/Kconfig"
1028 source "arch/arm/mach-ep93xx/Kconfig"
1030 source "arch/arm/mach-footbridge/Kconfig"
1032 source "arch/arm/mach-gemini/Kconfig"
1034 source "arch/arm/mach-h720x/Kconfig"
1036 source "arch/arm/mach-integrator/Kconfig"
1038 source "arch/arm/mach-iop32x/Kconfig"
1040 source "arch/arm/mach-iop33x/Kconfig"
1042 source "arch/arm/mach-iop13xx/Kconfig"
1044 source "arch/arm/mach-ixp4xx/Kconfig"
1046 source "arch/arm/mach-kirkwood/Kconfig"
1048 source "arch/arm/mach-ks8695/Kconfig"
1050 source "arch/arm/mach-msm/Kconfig"
1052 source "arch/arm/mach-mv78xx0/Kconfig"
1054 source "arch/arm/plat-mxc/Kconfig"
1056 source "arch/arm/mach-mxs/Kconfig"
1058 source "arch/arm/mach-netx/Kconfig"
1060 source "arch/arm/mach-nomadik/Kconfig"
1061 source "arch/arm/plat-nomadik/Kconfig"
1063 source "arch/arm/plat-omap/Kconfig"
1065 source "arch/arm/mach-omap1/Kconfig"
1067 source "arch/arm/mach-omap2/Kconfig"
1069 source "arch/arm/mach-orion5x/Kconfig"
1071 source "arch/arm/mach-pxa/Kconfig"
1072 source "arch/arm/plat-pxa/Kconfig"
1074 source "arch/arm/mach-mmp/Kconfig"
1076 source "arch/arm/mach-realview/Kconfig"
1078 source "arch/arm/mach-sa1100/Kconfig"
1080 source "arch/arm/plat-samsung/Kconfig"
1081 source "arch/arm/plat-s3c24xx/Kconfig"
1083 source "arch/arm/plat-spear/Kconfig"
1085 source "arch/arm/mach-s3c24xx/Kconfig"
1087 source "arch/arm/mach-s3c2412/Kconfig"
1088 source "arch/arm/mach-s3c2440/Kconfig"
1092 source "arch/arm/mach-s3c64xx/Kconfig"
1095 source "arch/arm/mach-s5p64x0/Kconfig"
1097 source "arch/arm/mach-s5pc100/Kconfig"
1099 source "arch/arm/mach-s5pv210/Kconfig"
1101 source "arch/arm/mach-exynos/Kconfig"
1103 source "arch/arm/mach-shmobile/Kconfig"
1105 source "arch/arm/mach-prima2/Kconfig"
1107 source "arch/arm/mach-tegra/Kconfig"
1109 source "arch/arm/mach-u300/Kconfig"
1111 source "arch/arm/mach-ux500/Kconfig"
1113 source "arch/arm/mach-versatile/Kconfig"
1115 source "arch/arm/mach-vexpress/Kconfig"
1116 source "arch/arm/plat-versatile/Kconfig"
1118 source "arch/arm/mach-vt8500/Kconfig"
1120 source "arch/arm/mach-w90x900/Kconfig"
1122 # Definitions to make life easier
1128 select GENERIC_CLOCKEVENTS
1133 select GENERIC_IRQ_CHIP
1140 config PLAT_VERSATILE
1143 config ARM_TIMER_SP804
1146 select HAVE_SCHED_CLOCK
1148 source arch/arm/mm/Kconfig
1152 default 16 if ARCH_EP93XX
1156 bool "Enable iWMMXt support"
1157 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1158 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1160 Enable support for iWMMXt context switching at run time if
1161 running on a CPU that supports it.
1165 depends on CPU_XSCALE
1168 config MULTI_IRQ_HANDLER
1171 Allow each machine to specify it's own IRQ handler at run time.
1174 source "arch/arm/Kconfig-nommu"
1177 config ARM_ERRATA_326103
1178 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1181 Executing a SWP instruction to read-only memory does not set bit 11
1182 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1183 treat the access as a read, preventing a COW from occurring and
1184 causing the faulting task to livelock.
1186 config ARM_ERRATA_411920
1187 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1188 depends on CPU_V6 || CPU_V6K
1190 Invalidation of the Instruction Cache operation can
1191 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1192 It does not affect the MPCore. This option enables the ARM Ltd.
1193 recommended workaround.
1195 config ARM_ERRATA_430973
1196 bool "ARM errata: Stale prediction on replaced interworking branch"
1199 This option enables the workaround for the 430973 Cortex-A8
1200 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1201 interworking branch is replaced with another code sequence at the
1202 same virtual address, whether due to self-modifying code or virtual
1203 to physical address re-mapping, Cortex-A8 does not recover from the
1204 stale interworking branch prediction. This results in Cortex-A8
1205 executing the new code sequence in the incorrect ARM or Thumb state.
1206 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1207 and also flushes the branch target cache at every context switch.
1208 Note that setting specific bits in the ACTLR register may not be
1209 available in non-secure mode.
1211 config ARM_ERRATA_458693
1212 bool "ARM errata: Processor deadlock when a false hazard is created"
1215 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1216 erratum. For very specific sequences of memory operations, it is
1217 possible for a hazard condition intended for a cache line to instead
1218 be incorrectly associated with a different cache line. This false
1219 hazard might then cause a processor deadlock. The workaround enables
1220 the L1 caching of the NEON accesses and disables the PLD instruction
1221 in the ACTLR register. Note that setting specific bits in the ACTLR
1222 register may not be available in non-secure mode.
1224 config ARM_ERRATA_460075
1225 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1228 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1229 erratum. Any asynchronous access to the L2 cache may encounter a
1230 situation in which recent store transactions to the L2 cache are lost
1231 and overwritten with stale memory contents from external memory. The
1232 workaround disables the write-allocate mode for the L2 cache via the
1233 ACTLR register. Note that setting specific bits in the ACTLR register
1234 may not be available in non-secure mode.
1236 config ARM_ERRATA_742230
1237 bool "ARM errata: DMB operation may be faulty"
1238 depends on CPU_V7 && SMP
1240 This option enables the workaround for the 742230 Cortex-A9
1241 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1242 between two write operations may not ensure the correct visibility
1243 ordering of the two writes. This workaround sets a specific bit in
1244 the diagnostic register of the Cortex-A9 which causes the DMB
1245 instruction to behave as a DSB, ensuring the correct behaviour of
1248 config ARM_ERRATA_742231
1249 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1250 depends on CPU_V7 && SMP
1252 This option enables the workaround for the 742231 Cortex-A9
1253 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1254 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1255 accessing some data located in the same cache line, may get corrupted
1256 data due to bad handling of the address hazard when the line gets
1257 replaced from one of the CPUs at the same time as another CPU is
1258 accessing it. This workaround sets specific bits in the diagnostic
1259 register of the Cortex-A9 which reduces the linefill issuing
1260 capabilities of the processor.
1262 config PL310_ERRATA_588369
1263 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1264 depends on CACHE_L2X0
1266 The PL310 L2 cache controller implements three types of Clean &
1267 Invalidate maintenance operations: by Physical Address
1268 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1269 They are architecturally defined to behave as the execution of a
1270 clean operation followed immediately by an invalidate operation,
1271 both performing to the same memory location. This functionality
1272 is not correctly implemented in PL310 as clean lines are not
1273 invalidated as a result of these operations.
1275 config ARM_ERRATA_720789
1276 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1279 This option enables the workaround for the 720789 Cortex-A9 (prior to
1280 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1281 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1282 As a consequence of this erratum, some TLB entries which should be
1283 invalidated are not, resulting in an incoherency in the system page
1284 tables. The workaround changes the TLB flushing routines to invalidate
1285 entries regardless of the ASID.
1287 config PL310_ERRATA_727915
1288 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1289 depends on CACHE_L2X0
1291 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1292 operation (offset 0x7FC). This operation runs in background so that
1293 PL310 can handle normal accesses while it is in progress. Under very
1294 rare circumstances, due to this erratum, write data can be lost when
1295 PL310 treats a cacheable write transaction during a Clean &
1296 Invalidate by Way operation.
1298 config ARM_ERRATA_743622
1299 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1302 This option enables the workaround for the 743622 Cortex-A9
1303 (r2p*) erratum. Under very rare conditions, a faulty
1304 optimisation in the Cortex-A9 Store Buffer may lead to data
1305 corruption. This workaround sets a specific bit in the diagnostic
1306 register of the Cortex-A9 which disables the Store Buffer
1307 optimisation, preventing the defect from occurring. This has no
1308 visible impact on the overall performance or power consumption of the
1311 config ARM_ERRATA_751472
1312 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1315 This option enables the workaround for the 751472 Cortex-A9 (prior
1316 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1317 completion of a following broadcasted operation if the second
1318 operation is received by a CPU before the ICIALLUIS has completed,
1319 potentially leading to corrupted entries in the cache or TLB.
1321 config PL310_ERRATA_753970
1322 bool "PL310 errata: cache sync operation may be faulty"
1323 depends on CACHE_PL310
1325 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1327 Under some condition the effect of cache sync operation on
1328 the store buffer still remains when the operation completes.
1329 This means that the store buffer is always asked to drain and
1330 this prevents it from merging any further writes. The workaround
1331 is to replace the normal offset of cache sync operation (0x730)
1332 by another offset targeting an unmapped PL310 register 0x740.
1333 This has the same effect as the cache sync operation: store buffer
1334 drain and waiting for all buffers empty.
1336 config ARM_ERRATA_754322
1337 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1340 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1341 r3p*) erratum. A speculative memory access may cause a page table walk
1342 which starts prior to an ASID switch but completes afterwards. This
1343 can populate the micro-TLB with a stale entry which may be hit with
1344 the new ASID. This workaround places two dsb instructions in the mm
1345 switching code so that no page table walks can cross the ASID switch.
1347 config ARM_ERRATA_754327
1348 bool "ARM errata: no automatic Store Buffer drain"
1349 depends on CPU_V7 && SMP
1351 This option enables the workaround for the 754327 Cortex-A9 (prior to
1352 r2p0) erratum. The Store Buffer does not have any automatic draining
1353 mechanism and therefore a livelock may occur if an external agent
1354 continuously polls a memory location waiting to observe an update.
1355 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1356 written polling loops from denying visibility of updates to memory.
1358 config ARM_ERRATA_364296
1359 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1360 depends on CPU_V6 && !SMP
1362 This options enables the workaround for the 364296 ARM1136
1363 r0p2 erratum (possible cache data corruption with
1364 hit-under-miss enabled). It sets the undocumented bit 31 in
1365 the auxiliary control register and the FI bit in the control
1366 register, thus disabling hit-under-miss without putting the
1367 processor into full low interrupt latency mode. ARM11MPCore
1370 config ARM_ERRATA_764369
1371 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1372 depends on CPU_V7 && SMP
1374 This option enables the workaround for erratum 764369
1375 affecting Cortex-A9 MPCore with two or more processors (all
1376 current revisions). Under certain timing circumstances, a data
1377 cache line maintenance operation by MVA targeting an Inner
1378 Shareable memory region may fail to proceed up to either the
1379 Point of Coherency or to the Point of Unification of the
1380 system. This workaround adds a DSB instruction before the
1381 relevant cache maintenance functions and sets a specific bit
1382 in the diagnostic control register of the SCU.
1384 config PL310_ERRATA_769419
1385 bool "PL310 errata: no automatic Store Buffer drain"
1386 depends on CACHE_L2X0
1388 On revisions of the PL310 prior to r3p2, the Store Buffer does
1389 not automatically drain. This can cause normal, non-cacheable
1390 writes to be retained when the memory system is idle, leading
1391 to suboptimal I/O performance for drivers using coherent DMA.
1392 This option adds a write barrier to the cpu_idle loop so that,
1393 on systems with an outer cache, the store buffer is drained
1398 source "arch/arm/common/Kconfig"
1408 Find out whether you have ISA slots on your motherboard. ISA is the
1409 name of a bus system, i.e. the way the CPU talks to the other stuff
1410 inside your box. Other bus systems are PCI, EISA, MicroChannel
1411 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1412 newer boards don't support it. If you have ISA, say Y, otherwise N.
1414 # Select ISA DMA controller support
1419 # Select ISA DMA interface
1424 bool "PCI support" if MIGHT_HAVE_PCI
1426 Find out whether you have a PCI motherboard. PCI is the name of a
1427 bus system, i.e. the way the CPU talks to the other stuff inside
1428 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1429 VESA. If you have PCI, say Y, otherwise N.
1435 config PCI_NANOENGINE
1436 bool "BSE nanoEngine PCI support"
1437 depends on SA1100_NANOENGINE
1439 Enable PCI on the BSE nanoEngine board.
1444 # Select the host bridge type
1445 config PCI_HOST_VIA82C505
1447 depends on PCI && ARCH_SHARK
1450 config PCI_HOST_ITE8152
1452 depends on PCI && MACH_ARMCORE
1456 source "drivers/pci/Kconfig"
1458 source "drivers/pcmcia/Kconfig"
1462 menu "Kernel Features"
1467 This option should be selected by machines which have an SMP-
1470 The only effect of this option is to make the SMP-related
1471 options available to the user for configuration.
1474 bool "Symmetric Multi-Processing"
1475 depends on CPU_V6K || CPU_V7
1476 depends on GENERIC_CLOCKEVENTS
1479 select USE_GENERIC_SMP_HELPERS
1480 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1482 This enables support for systems with more than one CPU. If you have
1483 a system with only one CPU, like most personal computers, say N. If
1484 you have a system with more than one CPU, say Y.
1486 If you say N here, the kernel will run on single and multiprocessor
1487 machines, but will use only one CPU of a multiprocessor machine. If
1488 you say Y here, the kernel will run on many, but not all, single
1489 processor machines. On a single processor machine, the kernel will
1490 run faster if you say N here.
1492 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1493 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1494 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1496 If you don't know what to do here, say N.
1499 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1500 depends on EXPERIMENTAL
1501 depends on SMP && !XIP_KERNEL
1504 SMP kernels contain instructions which fail on non-SMP processors.
1505 Enabling this option allows the kernel to modify itself to make
1506 these instructions safe. Disabling it allows about 1K of space
1509 If you don't know what to do here, say Y.
1511 config ARM_CPU_TOPOLOGY
1512 bool "Support cpu topology definition"
1513 depends on SMP && CPU_V7
1516 Support ARM cpu topology definition. The MPIDR register defines
1517 affinity between processors which is then used to describe the cpu
1518 topology of an ARM System.
1521 bool "Multi-core scheduler support"
1522 depends on ARM_CPU_TOPOLOGY
1524 Multi-core scheduler support improves the CPU scheduler's decision
1525 making when dealing with multi-core CPU chips at a cost of slightly
1526 increased overhead in some places. If unsure say N here.
1529 bool "SMT scheduler support"
1530 depends on ARM_CPU_TOPOLOGY
1532 Improves the CPU scheduler's decision making when dealing with
1533 MultiThreading at a cost of slightly increased overhead in some
1534 places. If unsure say N here.
1539 This option enables support for the ARM system coherency unit
1541 config ARM_ARCH_TIMER
1542 bool "Architected timer support"
1545 This option enables support for the ARM architected timer
1551 This options enables support for the ARM timer and watchdog unit
1554 prompt "Memory split"
1557 Select the desired split between kernel and user memory.
1559 If you are not absolutely sure what you are doing, leave this
1563 bool "3G/1G user/kernel split"
1565 bool "2G/2G user/kernel split"
1567 bool "1G/3G user/kernel split"
1572 default 0x40000000 if VMSPLIT_1G
1573 default 0x80000000 if VMSPLIT_2G
1577 int "Maximum number of CPUs (2-32)"
1583 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1584 depends on SMP && HOTPLUG && EXPERIMENTAL
1586 Say Y here to experiment with turning CPUs off and on. CPUs
1587 can be controlled through /sys/devices/system/cpu.
1590 bool "Use local timer interrupts"
1593 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1595 Enable support for local timers on SMP platforms, rather then the
1596 legacy IPI broadcast method. Local timers allows the system
1597 accounting to be spread across the timer interval, preventing a
1598 "thundering herd" at every timer tick.
1602 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1603 default 355 if ARCH_U8500
1604 default 264 if MACH_H4700
1605 default 512 if SOC_OMAP5
1608 Maximum number of GPIOs in the system.
1610 If unsure, leave the default value.
1612 source kernel/Kconfig.preempt
1616 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1617 ARCH_S5PV210 || ARCH_EXYNOS4
1618 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1619 default AT91_TIMER_HZ if ARCH_AT91
1620 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1623 config THUMB2_KERNEL
1624 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1625 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1627 select ARM_ASM_UNIFIED
1630 By enabling this option, the kernel will be compiled in
1631 Thumb-2 mode. A compiler/assembler that understand the unified
1632 ARM-Thumb syntax is needed.
1636 config THUMB2_AVOID_R_ARM_THM_JUMP11
1637 bool "Work around buggy Thumb-2 short branch relocations in gas"
1638 depends on THUMB2_KERNEL && MODULES
1641 Various binutils versions can resolve Thumb-2 branches to
1642 locally-defined, preemptible global symbols as short-range "b.n"
1643 branch instructions.
1645 This is a problem, because there's no guarantee the final
1646 destination of the symbol, or any candidate locations for a
1647 trampoline, are within range of the branch. For this reason, the
1648 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1649 relocation in modules at all, and it makes little sense to add
1652 The symptom is that the kernel fails with an "unsupported
1653 relocation" error when loading some modules.
1655 Until fixed tools are available, passing
1656 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1657 code which hits this problem, at the cost of a bit of extra runtime
1658 stack usage in some cases.
1660 The problem is described in more detail at:
1661 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1663 Only Thumb-2 kernels are affected.
1665 Unless you are sure your tools don't have this problem, say Y.
1667 config ARM_ASM_UNIFIED
1671 bool "Use the ARM EABI to compile the kernel"
1673 This option allows for the kernel to be compiled using the latest
1674 ARM ABI (aka EABI). This is only useful if you are using a user
1675 space environment that is also compiled with EABI.
1677 Since there are major incompatibilities between the legacy ABI and
1678 EABI, especially with regard to structure member alignment, this
1679 option also changes the kernel syscall calling convention to
1680 disambiguate both ABIs and allow for backward compatibility support
1681 (selected with CONFIG_OABI_COMPAT).
1683 To use this you need GCC version 4.0.0 or later.
1686 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1687 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1690 This option preserves the old syscall interface along with the
1691 new (ARM EABI) one. It also provides a compatibility layer to
1692 intercept syscalls that have structure arguments which layout
1693 in memory differs between the legacy ABI and the new ARM EABI
1694 (only for non "thumb" binaries). This option adds a tiny
1695 overhead to all syscalls and produces a slightly larger kernel.
1696 If you know you'll be using only pure EABI user space then you
1697 can say N here. If this option is not selected and you attempt
1698 to execute a legacy ABI binary then the result will be
1699 UNPREDICTABLE (in fact it can be predicted that it won't work
1700 at all). If in doubt say Y.
1702 config ARCH_HAS_HOLES_MEMORYMODEL
1705 config ARCH_SPARSEMEM_ENABLE
1708 config ARCH_SPARSEMEM_DEFAULT
1709 def_bool ARCH_SPARSEMEM_ENABLE
1711 config ARCH_SELECT_MEMORY_MODEL
1712 def_bool ARCH_SPARSEMEM_ENABLE
1714 config HAVE_ARCH_PFN_VALID
1715 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1718 bool "High Memory Support"
1721 The address space of ARM processors is only 4 Gigabytes large
1722 and it has to accommodate user address space, kernel address
1723 space as well as some memory mapped IO. That means that, if you
1724 have a large amount of physical memory and/or IO, not all of the
1725 memory can be "permanently mapped" by the kernel. The physical
1726 memory that is not permanently mapped is called "high memory".
1728 Depending on the selected kernel/user memory split, minimum
1729 vmalloc space and actual amount of RAM, you may not need this
1730 option which should result in a slightly faster kernel.
1735 bool "Allocate 2nd-level pagetables from highmem"
1738 config HW_PERF_EVENTS
1739 bool "Enable hardware performance counter support for perf events"
1740 depends on PERF_EVENTS
1743 Enable hardware performance counter support for perf events. If
1744 disabled, perf events will use software events only.
1748 config FORCE_MAX_ZONEORDER
1749 int "Maximum zone order" if ARCH_SHMOBILE
1750 range 11 64 if ARCH_SHMOBILE
1751 default "9" if SA1111
1754 The kernel memory allocator divides physically contiguous memory
1755 blocks into "zones", where each zone is a power of two number of
1756 pages. This option selects the largest power of two that the kernel
1757 keeps in the memory allocator. If you need to allocate very large
1758 blocks of physically contiguous memory, then you may need to
1759 increase this value.
1761 This config option is actually maximum order plus one. For example,
1762 a value of 11 means that the largest free memory block is 2^10 pages.
1764 config ALIGNMENT_TRAP
1766 depends on CPU_CP15_MMU
1767 default y if !ARCH_EBSA110
1768 select HAVE_PROC_CPU if PROC_FS
1770 ARM processors cannot fetch/store information which is not
1771 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1772 address divisible by 4. On 32-bit ARM processors, these non-aligned
1773 fetch/store instructions will be emulated in software if you say
1774 here, which has a severe performance impact. This is necessary for
1775 correct operation of some network protocols. With an IP-only
1776 configuration it is safe to say N, otherwise say Y.
1778 config UACCESS_WITH_MEMCPY
1779 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1780 depends on MMU && EXPERIMENTAL
1781 default y if CPU_FEROCEON
1783 Implement faster copy_to_user and clear_user methods for CPU
1784 cores where a 8-word STM instruction give significantly higher
1785 memory write throughput than a sequence of individual 32bit stores.
1787 A possible side effect is a slight increase in scheduling latency
1788 between threads sharing the same address space if they invoke
1789 such copy operations with large buffers.
1791 However, if the CPU data cache is using a write-allocate mode,
1792 this option is unlikely to provide any performance gain.
1796 prompt "Enable seccomp to safely compute untrusted bytecode"
1798 This kernel feature is useful for number crunching applications
1799 that may need to compute untrusted bytecode during their
1800 execution. By using pipes or other transports made available to
1801 the process as file descriptors supporting the read/write
1802 syscalls, it's possible to isolate those applications in
1803 their own address space using seccomp. Once seccomp is
1804 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1805 and the task is only allowed to execute a few safe syscalls
1806 defined by each seccomp mode.
1808 config CC_STACKPROTECTOR
1809 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1810 depends on EXPERIMENTAL
1812 This option turns on the -fstack-protector GCC feature. This
1813 feature puts, at the beginning of functions, a canary value on
1814 the stack just before the return address, and validates
1815 the value just before actually returning. Stack based buffer
1816 overflows (that need to overwrite this return address) now also
1817 overwrite the canary, which gets detected and the attack is then
1818 neutralized via a kernel panic.
1819 This feature requires gcc version 4.2 or above.
1821 config DEPRECATED_PARAM_STRUCT
1822 bool "Provide old way to pass kernel parameters"
1824 This was deprecated in 2001 and announced to live on for 5 years.
1825 Some old boot loaders still use this way.
1832 bool "Flattened Device Tree support"
1834 select OF_EARLY_FLATTREE
1837 Include support for flattened device tree machine descriptions.
1839 # Compressed boot loader in ROM. Yes, we really want to ask about
1840 # TEXT and BSS so we preserve their values in the config files.
1841 config ZBOOT_ROM_TEXT
1842 hex "Compressed ROM boot loader base address"
1845 The physical address at which the ROM-able zImage is to be
1846 placed in the target. Platforms which normally make use of
1847 ROM-able zImage formats normally set this to a suitable
1848 value in their defconfig file.
1850 If ZBOOT_ROM is not enabled, this has no effect.
1852 config ZBOOT_ROM_BSS
1853 hex "Compressed ROM boot loader BSS address"
1856 The base address of an area of read/write memory in the target
1857 for the ROM-able zImage which must be available while the
1858 decompressor is running. It must be large enough to hold the
1859 entire decompressed kernel plus an additional 128 KiB.
1860 Platforms which normally make use of ROM-able zImage formats
1861 normally set this to a suitable value in their defconfig file.
1863 If ZBOOT_ROM is not enabled, this has no effect.
1866 bool "Compressed boot loader in ROM/flash"
1867 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1869 Say Y here if you intend to execute your compressed kernel image
1870 (zImage) directly from ROM or flash. If unsure, say N.
1873 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1874 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1875 default ZBOOT_ROM_NONE
1877 Include experimental SD/MMC loading code in the ROM-able zImage.
1878 With this enabled it is possible to write the ROM-able zImage
1879 kernel image to an MMC or SD card and boot the kernel straight
1880 from the reset vector. At reset the processor Mask ROM will load
1881 the first part of the ROM-able zImage which in turn loads the
1882 rest the kernel image to RAM.
1884 config ZBOOT_ROM_NONE
1885 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1887 Do not load image from SD or MMC
1889 config ZBOOT_ROM_MMCIF
1890 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1892 Load image from MMCIF hardware block.
1894 config ZBOOT_ROM_SH_MOBILE_SDHI
1895 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1897 Load image from SDHI hardware block
1901 config ARM_APPENDED_DTB
1902 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1903 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1905 With this option, the boot code will look for a device tree binary
1906 (DTB) appended to zImage
1907 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1909 This is meant as a backward compatibility convenience for those
1910 systems with a bootloader that can't be upgraded to accommodate
1911 the documented boot protocol using a device tree.
1913 Beware that there is very little in terms of protection against
1914 this option being confused by leftover garbage in memory that might
1915 look like a DTB header after a reboot if no actual DTB is appended
1916 to zImage. Do not leave this option active in a production kernel
1917 if you don't intend to always append a DTB. Proper passing of the
1918 location into r2 of a bootloader provided DTB is always preferable
1921 config ARM_ATAG_DTB_COMPAT
1922 bool "Supplement the appended DTB with traditional ATAG information"
1923 depends on ARM_APPENDED_DTB
1925 Some old bootloaders can't be updated to a DTB capable one, yet
1926 they provide ATAGs with memory configuration, the ramdisk address,
1927 the kernel cmdline string, etc. Such information is dynamically
1928 provided by the bootloader and can't always be stored in a static
1929 DTB. To allow a device tree enabled kernel to be used with such
1930 bootloaders, this option allows zImage to extract the information
1931 from the ATAG list and store it at run time into the appended DTB.
1934 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1935 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1937 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1938 bool "Use bootloader kernel arguments if available"
1940 Uses the command-line options passed by the boot loader instead of
1941 the device tree bootargs property. If the boot loader doesn't provide
1942 any, the device tree bootargs property will be used.
1944 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1945 bool "Extend with bootloader kernel arguments"
1947 The command-line arguments provided by the boot loader will be
1948 appended to the the device tree bootargs property.
1953 string "Default kernel command string"
1956 On some architectures (EBSA110 and CATS), there is currently no way
1957 for the boot loader to pass arguments to the kernel. For these
1958 architectures, you should supply some command-line options at build
1959 time by entering them here. As a minimum, you should specify the
1960 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1963 prompt "Kernel command line type" if CMDLINE != ""
1964 default CMDLINE_FROM_BOOTLOADER
1966 config CMDLINE_FROM_BOOTLOADER
1967 bool "Use bootloader kernel arguments if available"
1969 Uses the command-line options passed by the boot loader. If
1970 the boot loader doesn't provide any, the default kernel command
1971 string provided in CMDLINE will be used.
1973 config CMDLINE_EXTEND
1974 bool "Extend bootloader kernel arguments"
1976 The command-line arguments provided by the boot loader will be
1977 appended to the default kernel command string.
1979 config CMDLINE_FORCE
1980 bool "Always use the default kernel command string"
1982 Always use the default kernel command string, even if the boot
1983 loader passes other arguments to the kernel.
1984 This is useful if you cannot or don't want to change the
1985 command-line options your boot loader passes to the kernel.
1989 bool "Kernel Execute-In-Place from ROM"
1990 depends on !ZBOOT_ROM && !ARM_LPAE
1992 Execute-In-Place allows the kernel to run from non-volatile storage
1993 directly addressable by the CPU, such as NOR flash. This saves RAM
1994 space since the text section of the kernel is not loaded from flash
1995 to RAM. Read-write sections, such as the data section and stack,
1996 are still copied to RAM. The XIP kernel is not compressed since
1997 it has to run directly from flash, so it will take more space to
1998 store it. The flash address used to link the kernel object files,
1999 and for storing it, is configuration dependent. Therefore, if you
2000 say Y here, you must know the proper physical address where to
2001 store the kernel image depending on your own flash memory usage.
2003 Also note that the make target becomes "make xipImage" rather than
2004 "make zImage" or "make Image". The final kernel binary to put in
2005 ROM memory will be arch/arm/boot/xipImage.
2009 config XIP_PHYS_ADDR
2010 hex "XIP Kernel Physical Location"
2011 depends on XIP_KERNEL
2012 default "0x00080000"
2014 This is the physical address in your flash memory the kernel will
2015 be linked for and stored to. This address is dependent on your
2019 bool "Kexec system call (EXPERIMENTAL)"
2020 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2022 kexec is a system call that implements the ability to shutdown your
2023 current kernel, and to start another kernel. It is like a reboot
2024 but it is independent of the system firmware. And like a reboot
2025 you can start any kernel with it, not just Linux.
2027 It is an ongoing process to be certain the hardware in a machine
2028 is properly shutdown, so do not be surprised if this code does not
2029 initially work for you. It may help to enable device hotplugging
2033 bool "Export atags in procfs"
2037 Should the atags used to boot the kernel be exported in an "atags"
2038 file in procfs. Useful with kexec.
2041 bool "Build kdump crash kernel (EXPERIMENTAL)"
2042 depends on EXPERIMENTAL
2044 Generate crash dump after being started by kexec. This should
2045 be normally only set in special crash dump kernels which are
2046 loaded in the main kernel with kexec-tools into a specially
2047 reserved region and then later executed after a crash by
2048 kdump/kexec. The crash dump kernel must be compiled to a
2049 memory address not used by the main kernel
2051 For more details see Documentation/kdump/kdump.txt
2053 config AUTO_ZRELADDR
2054 bool "Auto calculation of the decompressed kernel image address"
2055 depends on !ZBOOT_ROM && !ARCH_U300
2057 ZRELADDR is the physical address where the decompressed kernel
2058 image will be placed. If AUTO_ZRELADDR is selected, the address
2059 will be determined at run-time by masking the current IP with
2060 0xf8000000. This assumes the zImage being placed in the first 128MB
2061 from start of memory.
2065 menu "CPU Power Management"
2069 source "drivers/cpufreq/Kconfig"
2072 tristate "CPUfreq driver for i.MX CPUs"
2073 depends on ARCH_MXC && CPU_FREQ
2074 select CPU_FREQ_TABLE
2076 This enables the CPUfreq driver for i.MX CPUs.
2078 config CPU_FREQ_SA1100
2081 config CPU_FREQ_SA1110
2084 config CPU_FREQ_INTEGRATOR
2085 tristate "CPUfreq driver for ARM Integrator CPUs"
2086 depends on ARCH_INTEGRATOR && CPU_FREQ
2089 This enables the CPUfreq driver for ARM Integrator CPUs.
2091 For details, take a look at <file:Documentation/cpu-freq>.
2097 depends on CPU_FREQ && ARCH_PXA && PXA25x
2099 select CPU_FREQ_TABLE
2100 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2105 Internal configuration node for common cpufreq on Samsung SoC
2107 config CPU_FREQ_S3C24XX
2108 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2109 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2112 This enables the CPUfreq driver for the Samsung S3C24XX family
2115 For details, take a look at <file:Documentation/cpu-freq>.
2119 config CPU_FREQ_S3C24XX_PLL
2120 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2121 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2123 Compile in support for changing the PLL frequency from the
2124 S3C24XX series CPUfreq driver. The PLL takes time to settle
2125 after a frequency change, so by default it is not enabled.
2127 This also means that the PLL tables for the selected CPU(s) will
2128 be built which may increase the size of the kernel image.
2130 config CPU_FREQ_S3C24XX_DEBUG
2131 bool "Debug CPUfreq Samsung driver core"
2132 depends on CPU_FREQ_S3C24XX
2134 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2136 config CPU_FREQ_S3C24XX_IODEBUG
2137 bool "Debug CPUfreq Samsung driver IO timing"
2138 depends on CPU_FREQ_S3C24XX
2140 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2142 config CPU_FREQ_S3C24XX_DEBUGFS
2143 bool "Export debugfs for CPUFreq"
2144 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2146 Export status information via debugfs.
2150 source "drivers/cpuidle/Kconfig"
2154 menu "Floating point emulation"
2156 comment "At least one emulation must be selected"
2159 bool "NWFPE math emulation"
2160 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2162 Say Y to include the NWFPE floating point emulator in the kernel.
2163 This is necessary to run most binaries. Linux does not currently
2164 support floating point hardware so you need to say Y here even if
2165 your machine has an FPA or floating point co-processor podule.
2167 You may say N here if you are going to load the Acorn FPEmulator
2168 early in the bootup.
2171 bool "Support extended precision"
2172 depends on FPE_NWFPE
2174 Say Y to include 80-bit support in the kernel floating-point
2175 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2176 Note that gcc does not generate 80-bit operations by default,
2177 so in most cases this option only enlarges the size of the
2178 floating point emulator without any good reason.
2180 You almost surely want to say N here.
2183 bool "FastFPE math emulation (EXPERIMENTAL)"
2184 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2186 Say Y here to include the FAST floating point emulator in the kernel.
2187 This is an experimental much faster emulator which now also has full
2188 precision for the mantissa. It does not support any exceptions.
2189 It is very simple, and approximately 3-6 times faster than NWFPE.
2191 It should be sufficient for most programs. It may be not suitable
2192 for scientific calculations, but you have to check this for yourself.
2193 If you do not feel you need a faster FP emulation you should better
2197 bool "VFP-format floating point maths"
2198 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2200 Say Y to include VFP support code in the kernel. This is needed
2201 if your hardware includes a VFP unit.
2203 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2204 release notes and additional status information.
2206 Say N if your target does not have VFP hardware.
2214 bool "Advanced SIMD (NEON) Extension support"
2215 depends on VFPv3 && CPU_V7
2217 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2222 menu "Userspace binary formats"
2224 source "fs/Kconfig.binfmt"
2227 tristate "RISC OS personality"
2230 Say Y here to include the kernel code necessary if you want to run
2231 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2232 experimental; if this sounds frightening, say N and sleep in peace.
2233 You can also say M here to compile this support as a module (which
2234 will be called arthur).
2238 menu "Power management options"
2240 source "kernel/power/Kconfig"
2242 config ARCH_SUSPEND_POSSIBLE
2243 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2244 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2245 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2248 config ARM_CPU_SUSPEND
2253 source "net/Kconfig"
2255 source "drivers/Kconfig"
2259 source "arch/arm/Kconfig.debug"
2261 source "security/Kconfig"
2263 source "crypto/Kconfig"
2265 source "lib/Kconfig"