5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
68 select GENERIC_ALLOCATOR
79 The Extended Industry Standard Architecture (EISA) bus was
80 developed as an open alternative to the IBM MicroChannel bus.
82 The EISA bus provided some of the features of the IBM MicroChannel
83 bus while maintaining backward compatibility with cards made for
84 the older ISA bus. The EISA bus saw limited use between 1988 and
85 1995 when it was made obsolete by the PCI bus.
87 Say Y here if you are building a kernel for an EISA-based machine.
97 MicroChannel Architecture is found in some IBM PS/2 machines and
98 laptops. It is a bus system similar to PCI or ISA. See
99 <file:Documentation/mca.txt> (and especially the web page given
100 there) before attempting to build an MCA bus kernel.
102 config STACKTRACE_SUPPORT
106 config HAVE_LATENCYTOP_SUPPORT
111 config LOCKDEP_SUPPORT
115 config TRACE_IRQFLAGS_SUPPORT
119 config HARDIRQS_SW_RESEND
123 config GENERIC_IRQ_PROBE
127 config GENERIC_LOCKBREAK
130 depends on SMP && PREEMPT
132 config RWSEM_GENERIC_SPINLOCK
136 config RWSEM_XCHGADD_ALGORITHM
139 config ARCH_HAS_ILOG2_U32
142 config ARCH_HAS_ILOG2_U64
145 config ARCH_HAS_CPUFREQ
148 Internal node to signify that the ARCH has CPUFREQ support
149 and that the relevant menu configurations are displayed for
152 config ARCH_HAS_CPU_IDLE_WAIT
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config GENERIC_ISA_DMA
181 config ARM_L1_CACHE_SHIFT_6
184 Setting ARM L1 cache line size to 64 Bytes.
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 source "init/Kconfig"
196 source "kernel/Kconfig.freezer"
201 bool "MMU-based Paged Memory Management Support"
204 Select if you want MMU-based virtualised addressing space
205 support by paged memory management. If unsure, say 'Y'.
208 # The "ARM system type" choice list is ordered alphabetically by option
209 # text. Please add new entries in the option alphabetic order.
212 prompt "ARM system type"
213 default ARCH_VERSATILE
216 bool "Agilent AAEC-2000 based"
220 select ARCH_USES_GETTIMEOFFSET
222 This enables support for systems based on the Agilent AAEC-2000
224 config ARCH_INTEGRATOR
225 bool "ARM Ltd. Integrator family"
227 select ARCH_HAS_CPUFREQ
230 select GENERIC_CLOCKEVENTS
231 select PLAT_VERSATILE
233 Support for ARM's Integrator platform.
236 bool "ARM Ltd. RealView family"
239 select HAVE_SCHED_CLOCK
241 select GENERIC_CLOCKEVENTS
242 select ARCH_WANT_OPTIONAL_GPIOLIB
243 select PLAT_VERSATILE
244 select ARM_TIMER_SP804
245 select GPIO_PL061 if GPIOLIB
247 This enables support for ARM Ltd RealView boards.
249 config ARCH_VERSATILE
250 bool "ARM Ltd. Versatile family"
254 select HAVE_SCHED_CLOCK
256 select GENERIC_CLOCKEVENTS
257 select ARCH_WANT_OPTIONAL_GPIOLIB
258 select PLAT_VERSATILE
259 select ARM_TIMER_SP804
261 This enables support for ARM Ltd Versatile board.
264 bool "ARM Ltd. Versatile Express family"
265 select ARCH_WANT_OPTIONAL_GPIOLIB
267 select ARM_TIMER_SP804
269 select GENERIC_CLOCKEVENTS
271 select HAVE_SCHED_CLOCK
273 select PLAT_VERSATILE
275 This enables support for the ARM Ltd Versatile Express boards.
279 select ARCH_REQUIRE_GPIOLIB
282 This enables support for systems based on the Atmel AT91RM9200,
283 AT91SAM9 and AT91CAP9 processors.
286 bool "Broadcom BCMRING"
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
294 Support for Broadcom's BCMRing platform.
297 bool "Cirrus Logic CLPS711x/EP721x-based"
299 select ARCH_USES_GETTIMEOFFSET
301 Support for Cirrus Logic 711x/721x based boards.
304 bool "Cavium Networks CNS3XXX family"
306 select GENERIC_CLOCKEVENTS
308 select MIGHT_HAVE_PCI
309 select PCI_DOMAINS if PCI
311 Support for Cavium Networks CNS3XXX platform.
314 bool "Cortina Systems Gemini"
316 select ARCH_REQUIRE_GPIOLIB
317 select ARCH_USES_GETTIMEOFFSET
319 Support for the Cortina Systems Gemini family SoCs
326 select ARCH_USES_GETTIMEOFFSET
328 This is an evaluation board for the StrongARM processor available
329 from Digital. It has limited hardware on-board, including an
330 Ethernet interface, two PCMCIA sockets, two serial ports and a
339 select ARCH_REQUIRE_GPIOLIB
340 select ARCH_HAS_HOLES_MEMORYMODEL
341 select ARCH_USES_GETTIMEOFFSET
343 This enables support for the Cirrus EP93xx series of CPUs.
345 config ARCH_FOOTBRIDGE
349 select GENERIC_CLOCKEVENTS
351 Support for systems based on the DC21285 companion chip
352 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
355 bool "Freescale MXC/iMX-based"
356 select GENERIC_CLOCKEVENTS
357 select ARCH_REQUIRE_GPIOLIB
360 Support for Freescale MXC/iMX-based family of processors
363 bool "Freescale MXS-based"
364 select GENERIC_CLOCKEVENTS
365 select ARCH_REQUIRE_GPIOLIB
368 Support for Freescale MXS-based family of processors
371 bool "Freescale STMP3xxx"
374 select ARCH_REQUIRE_GPIOLIB
375 select GENERIC_CLOCKEVENTS
376 select USB_ARCH_HAS_EHCI
378 Support for systems based on the Freescale 3xxx CPUs.
381 bool "Hilscher NetX based"
384 select GENERIC_CLOCKEVENTS
386 This enables support for systems based on the Hilscher NetX Soc
389 bool "Hynix HMS720x-based"
392 select ARCH_USES_GETTIMEOFFSET
394 This enables support for systems based on the Hynix HMS720x
402 select ARCH_SUPPORTS_MSI
405 Support for Intel's IOP13XX (XScale) family of processors.
413 select ARCH_REQUIRE_GPIOLIB
415 Support for Intel's 80219 and IOP32X (XScale) family of
424 select ARCH_REQUIRE_GPIOLIB
426 Support for Intel's IOP33X (XScale) family of processors.
433 select ARCH_USES_GETTIMEOFFSET
435 Support for Intel's IXP23xx (XScale) family of processors.
438 bool "IXP2400/2800-based"
442 select ARCH_USES_GETTIMEOFFSET
444 Support for Intel's IXP2400/2800 (XScale) family of processors.
451 select GENERIC_CLOCKEVENTS
452 select HAVE_SCHED_CLOCK
453 select MIGHT_HAVE_PCI
454 select DMABOUNCE if PCI
456 Support for Intel's IXP4XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
462 select GENERIC_CLOCKEVENTS
465 Support for the Marvell Dove SoC 88AP510
468 bool "Marvell Kirkwood"
471 select ARCH_REQUIRE_GPIOLIB
472 select GENERIC_CLOCKEVENTS
475 Support for the following Marvell Kirkwood series SoCs:
476 88F6180, 88F6192 and 88F6281.
479 bool "Marvell Loki (88RC8480)"
481 select GENERIC_CLOCKEVENTS
484 Support for the Marvell Loki (88RC8480) SoC.
489 select ARCH_REQUIRE_GPIOLIB
492 select USB_ARCH_HAS_OHCI
495 select GENERIC_CLOCKEVENTS
497 Support for the NXP LPC32XX family of processors
500 bool "Marvell MV78xx0"
503 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
507 Support for the following Marvell MV78xx0 series SoCs:
515 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
519 Support for the following Marvell Orion 5x series SoCs:
520 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
521 Orion-2 (5281), Orion-1-90 (6183).
524 bool "Marvell PXA168/910/MMP2"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
529 select HAVE_SCHED_CLOCK
534 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
537 bool "Micrel/Kendin KS8695"
539 select ARCH_REQUIRE_GPIOLIB
540 select ARCH_USES_GETTIMEOFFSET
542 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
543 System-on-Chip devices.
546 bool "NetSilicon NS9xxx"
549 select GENERIC_CLOCKEVENTS
552 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
555 <http://www.digi.com/products/microprocessors/index.jsp>
558 bool "Nuvoton W90X900 CPU"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
565 At present, the w90x900 has been renamed nuc900, regarding
566 the ARM series product line, you can login the following
567 link address to know more.
569 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
570 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
573 bool "Nuvoton NUC93X CPU"
577 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
578 low-power and high performance MPEG-4/JPEG multimedia controller chip.
584 select GENERIC_CLOCKEVENTS
587 select HAVE_SCHED_CLOCK
588 select ARCH_HAS_BARRIERS if CACHE_L2X0
589 select ARCH_HAS_CPUFREQ
591 This enables support for NVIDIA Tegra based systems (Tegra APX,
592 Tegra 6xx and Tegra 2 series).
595 bool "Philips Nexperia PNX4008 Mobile"
598 select ARCH_USES_GETTIMEOFFSET
600 This enables support for Philips PNX4008 mobile platform.
603 bool "PXA2xx/PXA3xx-based"
606 select ARCH_HAS_CPUFREQ
608 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
610 select HAVE_SCHED_CLOCK
615 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
620 select GENERIC_CLOCKEVENTS
621 select ARCH_REQUIRE_GPIOLIB
623 Support for Qualcomm MSM/QSD based systems. This runs on the
624 apps processor of the MSM/QSD and depends on a shared memory
625 interface to the modem processor which runs the baseband
626 stack and controls some vital subsystems
627 (clock and power control, etc).
630 bool "Renesas SH-Mobile / R-Mobile"
633 select GENERIC_CLOCKEVENTS
636 select MULTI_IRQ_HANDLER
638 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
645 select ARCH_MAY_HAVE_PC_FDC
646 select HAVE_PATA_PLATFORM
649 select ARCH_SPARSEMEM_ENABLE
650 select ARCH_USES_GETTIMEOFFSET
652 On the Acorn Risc-PC, Linux can support the internal IDE disk and
653 CD-ROM interface, serial and parallel port, and the floppy drive.
659 select ARCH_SPARSEMEM_ENABLE
661 select ARCH_HAS_CPUFREQ
663 select GENERIC_CLOCKEVENTS
665 select HAVE_SCHED_CLOCK
667 select ARCH_REQUIRE_GPIOLIB
669 Support for StrongARM 11x0 based boards.
672 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
674 select ARCH_HAS_CPUFREQ
676 select ARCH_USES_GETTIMEOFFSET
677 select HAVE_S3C2410_I2C if I2C
679 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
680 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
681 the Samsung SMDK2410 development board (and derivatives).
683 Note, the S3C2416 and the S3C2450 are so close that they even share
684 the same SoC ID code. This means that there is no seperate machine
685 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
688 bool "Samsung S3C64XX"
694 select ARCH_USES_GETTIMEOFFSET
695 select ARCH_HAS_CPUFREQ
696 select ARCH_REQUIRE_GPIOLIB
697 select SAMSUNG_CLKSRC
698 select SAMSUNG_IRQ_VIC_TIMER
699 select SAMSUNG_IRQ_UART
700 select S3C_GPIO_TRACK
701 select S3C_GPIO_PULL_UPDOWN
702 select S3C_GPIO_CFG_S3C24XX
703 select S3C_GPIO_CFG_S3C64XX
705 select USB_ARCH_HAS_OHCI
706 select SAMSUNG_GPIOLIB_4BIT
707 select HAVE_S3C2410_I2C if I2C
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
710 Samsung S3C64XX series based systems
713 bool "Samsung S5P6440 S5P6450"
717 select HAVE_S3C2410_WATCHDOG if WATCHDOG
718 select ARCH_USES_GETTIMEOFFSET
719 select HAVE_S3C2410_I2C if I2C
720 select HAVE_S3C_RTC if RTC_CLASS
722 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
726 bool "Samsung S5P6442"
730 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_S3C2410_WATCHDOG if WATCHDOG
733 Samsung S5P6442 CPU based systems
736 bool "Samsung S5PC100"
740 select ARM_L1_CACHE_SHIFT_6
741 select ARCH_USES_GETTIMEOFFSET
742 select HAVE_S3C2410_I2C if I2C
743 select HAVE_S3C_RTC if RTC_CLASS
744 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 Samsung S5PC100 series based systems
749 bool "Samsung S5PV210/S5PC110"
751 select ARCH_SPARSEMEM_ENABLE
754 select ARM_L1_CACHE_SHIFT_6
755 select ARCH_HAS_CPUFREQ
756 select ARCH_USES_GETTIMEOFFSET
757 select HAVE_S3C2410_I2C if I2C
758 select HAVE_S3C_RTC if RTC_CLASS
759 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 Samsung S5PV210/S5PC110 series based systems
764 bool "Samsung S5PV310/S5PC210"
766 select ARCH_SPARSEMEM_ENABLE
769 select ARCH_HAS_CPUFREQ
770 select GENERIC_CLOCKEVENTS
771 select HAVE_S3C_RTC if RTC_CLASS
772 select HAVE_S3C2410_I2C if I2C
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 Samsung S5PV310 series based systems
784 select ARCH_USES_GETTIMEOFFSET
786 Support for the StrongARM based Digital DNARD machine, also known
787 as "Shark" (<http://www.shark-linux.de/shark.html>).
790 bool "Telechips TCC ARM926-based systems"
794 select GENERIC_CLOCKEVENTS
796 Support for Telechips TCC ARM926-based systems.
801 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
802 select ARCH_USES_GETTIMEOFFSET
804 Say Y here for systems based on one of the Sharp LH7A40X
805 System on a Chip processors. These CPUs include an ARM922T
806 core with a wide array of integrated devices for
807 hand-held and low-power applications.
810 bool "ST-Ericsson U300 Series"
813 select HAVE_SCHED_CLOCK
817 select GENERIC_CLOCKEVENTS
821 Support for ST-Ericsson U300 series mobile platforms.
824 bool "ST-Ericsson U8500 Series"
827 select GENERIC_CLOCKEVENTS
829 select ARCH_REQUIRE_GPIOLIB
830 select ARCH_HAS_CPUFREQ
832 Support for ST-Ericsson's Ux500 architecture
835 bool "STMicroelectronics Nomadik"
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
843 Support for the Nomadik platform by ST-Ericsson
847 select GENERIC_CLOCKEVENTS
848 select ARCH_REQUIRE_GPIOLIB
852 select GENERIC_ALLOCATOR
853 select ARCH_HAS_HOLES_MEMORYMODEL
855 Support for TI's DaVinci platform.
860 select ARCH_REQUIRE_GPIOLIB
861 select ARCH_HAS_CPUFREQ
862 select GENERIC_CLOCKEVENTS
863 select HAVE_SCHED_CLOCK
864 select ARCH_HAS_HOLES_MEMORYMODEL
866 Support for TI's OMAP platform (OMAP1/2/3/4).
871 select ARCH_REQUIRE_GPIOLIB
873 select GENERIC_CLOCKEVENTS
876 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
879 bool "VIA/WonderMedia 85xx"
882 select ARCH_HAS_CPUFREQ
883 select GENERIC_CLOCKEVENTS
884 select ARCH_REQUIRE_GPIOLIB
887 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
891 # This is sorted alphabetically by mach-* pathname. However, plat-*
892 # Kconfigs may be included either alphabetically (according to the
893 # plat- suffix) or along side the corresponding mach-* source.
895 source "arch/arm/mach-aaec2000/Kconfig"
897 source "arch/arm/mach-at91/Kconfig"
899 source "arch/arm/mach-bcmring/Kconfig"
901 source "arch/arm/mach-clps711x/Kconfig"
903 source "arch/arm/mach-cns3xxx/Kconfig"
905 source "arch/arm/mach-davinci/Kconfig"
907 source "arch/arm/mach-dove/Kconfig"
909 source "arch/arm/mach-ep93xx/Kconfig"
911 source "arch/arm/mach-footbridge/Kconfig"
913 source "arch/arm/mach-gemini/Kconfig"
915 source "arch/arm/mach-h720x/Kconfig"
917 source "arch/arm/mach-integrator/Kconfig"
919 source "arch/arm/mach-iop32x/Kconfig"
921 source "arch/arm/mach-iop33x/Kconfig"
923 source "arch/arm/mach-iop13xx/Kconfig"
925 source "arch/arm/mach-ixp4xx/Kconfig"
927 source "arch/arm/mach-ixp2000/Kconfig"
929 source "arch/arm/mach-ixp23xx/Kconfig"
931 source "arch/arm/mach-kirkwood/Kconfig"
933 source "arch/arm/mach-ks8695/Kconfig"
935 source "arch/arm/mach-lh7a40x/Kconfig"
937 source "arch/arm/mach-loki/Kconfig"
939 source "arch/arm/mach-lpc32xx/Kconfig"
941 source "arch/arm/mach-msm/Kconfig"
943 source "arch/arm/mach-mv78xx0/Kconfig"
945 source "arch/arm/plat-mxc/Kconfig"
947 source "arch/arm/mach-mxs/Kconfig"
949 source "arch/arm/mach-netx/Kconfig"
951 source "arch/arm/mach-nomadik/Kconfig"
952 source "arch/arm/plat-nomadik/Kconfig"
954 source "arch/arm/mach-ns9xxx/Kconfig"
956 source "arch/arm/mach-nuc93x/Kconfig"
958 source "arch/arm/plat-omap/Kconfig"
960 source "arch/arm/mach-omap1/Kconfig"
962 source "arch/arm/mach-omap2/Kconfig"
964 source "arch/arm/mach-orion5x/Kconfig"
966 source "arch/arm/mach-pxa/Kconfig"
967 source "arch/arm/plat-pxa/Kconfig"
969 source "arch/arm/mach-mmp/Kconfig"
971 source "arch/arm/mach-realview/Kconfig"
973 source "arch/arm/mach-sa1100/Kconfig"
975 source "arch/arm/plat-samsung/Kconfig"
976 source "arch/arm/plat-s3c24xx/Kconfig"
977 source "arch/arm/plat-s5p/Kconfig"
979 source "arch/arm/plat-spear/Kconfig"
981 source "arch/arm/plat-tcc/Kconfig"
984 source "arch/arm/mach-s3c2400/Kconfig"
985 source "arch/arm/mach-s3c2410/Kconfig"
986 source "arch/arm/mach-s3c2412/Kconfig"
987 source "arch/arm/mach-s3c2416/Kconfig"
988 source "arch/arm/mach-s3c2440/Kconfig"
989 source "arch/arm/mach-s3c2443/Kconfig"
993 source "arch/arm/mach-s3c64xx/Kconfig"
996 source "arch/arm/mach-s5p64x0/Kconfig"
998 source "arch/arm/mach-s5p6442/Kconfig"
1000 source "arch/arm/mach-s5pc100/Kconfig"
1002 source "arch/arm/mach-s5pv210/Kconfig"
1004 source "arch/arm/mach-s5pv310/Kconfig"
1006 source "arch/arm/mach-shmobile/Kconfig"
1008 source "arch/arm/plat-stmp3xxx/Kconfig"
1010 source "arch/arm/mach-tegra/Kconfig"
1012 source "arch/arm/mach-u300/Kconfig"
1014 source "arch/arm/mach-ux500/Kconfig"
1016 source "arch/arm/mach-versatile/Kconfig"
1018 source "arch/arm/mach-vexpress/Kconfig"
1020 source "arch/arm/mach-vt8500/Kconfig"
1022 source "arch/arm/mach-w90x900/Kconfig"
1024 # Definitions to make life easier
1030 select GENERIC_CLOCKEVENTS
1031 select HAVE_SCHED_CLOCK
1035 select HAVE_SCHED_CLOCK
1040 config PLAT_VERSATILE
1043 config ARM_TIMER_SP804
1046 source arch/arm/mm/Kconfig
1049 bool "Enable iWMMXt support"
1050 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1051 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1053 Enable support for iWMMXt context switching at run time if
1054 running on a CPU that supports it.
1056 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1059 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1063 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1064 (!ARCH_OMAP3 || OMAP3_EMU)
1068 config MULTI_IRQ_HANDLER
1071 Allow each machine to specify it's own IRQ handler at run time.
1074 source "arch/arm/Kconfig-nommu"
1077 config ARM_ERRATA_411920
1078 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1081 Invalidation of the Instruction Cache operation can
1082 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1083 It does not affect the MPCore. This option enables the ARM Ltd.
1084 recommended workaround.
1086 config ARM_ERRATA_430973
1087 bool "ARM errata: Stale prediction on replaced interworking branch"
1090 This option enables the workaround for the 430973 Cortex-A8
1091 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1092 interworking branch is replaced with another code sequence at the
1093 same virtual address, whether due to self-modifying code or virtual
1094 to physical address re-mapping, Cortex-A8 does not recover from the
1095 stale interworking branch prediction. This results in Cortex-A8
1096 executing the new code sequence in the incorrect ARM or Thumb state.
1097 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1098 and also flushes the branch target cache at every context switch.
1099 Note that setting specific bits in the ACTLR register may not be
1100 available in non-secure mode.
1102 config ARM_ERRATA_458693
1103 bool "ARM errata: Processor deadlock when a false hazard is created"
1106 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1107 erratum. For very specific sequences of memory operations, it is
1108 possible for a hazard condition intended for a cache line to instead
1109 be incorrectly associated with a different cache line. This false
1110 hazard might then cause a processor deadlock. The workaround enables
1111 the L1 caching of the NEON accesses and disables the PLD instruction
1112 in the ACTLR register. Note that setting specific bits in the ACTLR
1113 register may not be available in non-secure mode.
1115 config ARM_ERRATA_460075
1116 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1119 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1120 erratum. Any asynchronous access to the L2 cache may encounter a
1121 situation in which recent store transactions to the L2 cache are lost
1122 and overwritten with stale memory contents from external memory. The
1123 workaround disables the write-allocate mode for the L2 cache via the
1124 ACTLR register. Note that setting specific bits in the ACTLR register
1125 may not be available in non-secure mode.
1127 config ARM_ERRATA_742230
1128 bool "ARM errata: DMB operation may be faulty"
1129 depends on CPU_V7 && SMP
1131 This option enables the workaround for the 742230 Cortex-A9
1132 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1133 between two write operations may not ensure the correct visibility
1134 ordering of the two writes. This workaround sets a specific bit in
1135 the diagnostic register of the Cortex-A9 which causes the DMB
1136 instruction to behave as a DSB, ensuring the correct behaviour of
1139 config ARM_ERRATA_742231
1140 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1141 depends on CPU_V7 && SMP
1143 This option enables the workaround for the 742231 Cortex-A9
1144 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1145 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1146 accessing some data located in the same cache line, may get corrupted
1147 data due to bad handling of the address hazard when the line gets
1148 replaced from one of the CPUs at the same time as another CPU is
1149 accessing it. This workaround sets specific bits in the diagnostic
1150 register of the Cortex-A9 which reduces the linefill issuing
1151 capabilities of the processor.
1153 config PL310_ERRATA_588369
1154 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1155 depends on CACHE_L2X0 && ARCH_OMAP4
1157 The PL310 L2 cache controller implements three types of Clean &
1158 Invalidate maintenance operations: by Physical Address
1159 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1160 They are architecturally defined to behave as the execution of a
1161 clean operation followed immediately by an invalidate operation,
1162 both performing to the same memory location. This functionality
1163 is not correctly implemented in PL310 as clean lines are not
1164 invalidated as a result of these operations. Note that this errata
1165 uses Texas Instrument's secure monitor api.
1167 config ARM_ERRATA_720789
1168 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1169 depends on CPU_V7 && SMP
1171 This option enables the workaround for the 720789 Cortex-A9 (prior to
1172 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1173 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1174 As a consequence of this erratum, some TLB entries which should be
1175 invalidated are not, resulting in an incoherency in the system page
1176 tables. The workaround changes the TLB flushing routines to invalidate
1177 entries regardless of the ASID.
1179 config ARM_ERRATA_743622
1180 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1183 This option enables the workaround for the 743622 Cortex-A9
1184 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1185 optimisation in the Cortex-A9 Store Buffer may lead to data
1186 corruption. This workaround sets a specific bit in the diagnostic
1187 register of the Cortex-A9 which disables the Store Buffer
1188 optimisation, preventing the defect from occurring. This has no
1189 visible impact on the overall performance or power consumption of the
1192 config ARM_ERRATA_751472
1193 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for the 751472 Cortex-A9 (prior
1197 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1198 completion of a following broadcasted operation if the second
1199 operation is received by a CPU before the ICIALLUIS has completed,
1200 potentially leading to corrupted entries in the cache or TLB.
1202 config ARM_ERRATA_753970
1203 bool "ARM errata: cache sync operation may be faulty"
1204 depends on CACHE_PL310
1206 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1208 Under some condition the effect of cache sync operation on
1209 the store buffer still remains when the operation completes.
1210 This means that the store buffer is always asked to drain and
1211 this prevents it from merging any further writes. The workaround
1212 is to replace the normal offset of cache sync operation (0x730)
1213 by another offset targeting an unmapped PL310 register 0x740.
1214 This has the same effect as the cache sync operation: store buffer
1215 drain and waiting for all buffers empty.
1217 config ARM_ERRATA_754322
1218 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1221 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1222 r3p*) erratum. A speculative memory access may cause a page table walk
1223 which starts prior to an ASID switch but completes afterwards. This
1224 can populate the micro-TLB with a stale entry which may be hit with
1225 the new ASID. This workaround places two dsb instructions in the mm
1226 switching code so that no page table walks can cross the ASID switch.
1228 config ARM_ERRATA_754327
1229 bool "ARM errata: no automatic Store Buffer drain"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 754327 Cortex-A9 (prior to
1233 r2p0) erratum. The Store Buffer does not have any automatic draining
1234 mechanism and therefore a livelock may occur if an external agent
1235 continuously polls a memory location waiting to observe an update.
1236 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1237 written polling loops from denying visibility of updates to memory.
1241 source "arch/arm/common/Kconfig"
1251 Find out whether you have ISA slots on your motherboard. ISA is the
1252 name of a bus system, i.e. the way the CPU talks to the other stuff
1253 inside your box. Other bus systems are PCI, EISA, MicroChannel
1254 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1255 newer boards don't support it. If you have ISA, say Y, otherwise N.
1257 # Select ISA DMA controller support
1262 # Select ISA DMA interface
1267 bool "PCI support" if MIGHT_HAVE_PCI
1269 Find out whether you have a PCI motherboard. PCI is the name of a
1270 bus system, i.e. the way the CPU talks to the other stuff inside
1271 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1272 VESA. If you have PCI, say Y, otherwise N.
1278 config PCI_NANOENGINE
1279 bool "BSE nanoEngine PCI support"
1280 depends on SA1100_NANOENGINE
1282 Enable PCI on the BSE nanoEngine board.
1287 # Select the host bridge type
1288 config PCI_HOST_VIA82C505
1290 depends on PCI && ARCH_SHARK
1293 config PCI_HOST_ITE8152
1295 depends on PCI && MACH_ARMCORE
1299 source "drivers/pci/Kconfig"
1301 source "drivers/pcmcia/Kconfig"
1305 menu "Kernel Features"
1307 source "kernel/time/Kconfig"
1310 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1311 depends on EXPERIMENTAL
1312 depends on GENERIC_CLOCKEVENTS
1313 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1314 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1315 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1316 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1317 select USE_GENERIC_SMP_HELPERS
1318 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1320 This enables support for systems with more than one CPU. If you have
1321 a system with only one CPU, like most personal computers, say N. If
1322 you have a system with more than one CPU, say Y.
1324 If you say N here, the kernel will run on single and multiprocessor
1325 machines, but will use only one CPU of a multiprocessor machine. If
1326 you say Y here, the kernel will run on many, but not all, single
1327 processor machines. On a single processor machine, the kernel will
1328 run faster if you say N here.
1330 See also <file:Documentation/i386/IO-APIC.txt>,
1331 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1332 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1334 If you don't know what to do here, say N.
1337 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1338 depends on EXPERIMENTAL
1339 depends on SMP && !XIP_KERNEL
1342 SMP kernels contain instructions which fail on non-SMP processors.
1343 Enabling this option allows the kernel to modify itself to make
1344 these instructions safe. Disabling it allows about 1K of space
1347 If you don't know what to do here, say Y.
1353 This option enables support for the ARM system coherency unit
1360 This options enables support for the ARM timer and watchdog unit
1363 prompt "Memory split"
1366 Select the desired split between kernel and user memory.
1368 If you are not absolutely sure what you are doing, leave this
1372 bool "3G/1G user/kernel split"
1374 bool "2G/2G user/kernel split"
1376 bool "1G/3G user/kernel split"
1381 default 0x40000000 if VMSPLIT_1G
1382 default 0x80000000 if VMSPLIT_2G
1386 int "Maximum number of CPUs (2-32)"
1392 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1393 depends on SMP && HOTPLUG && EXPERIMENTAL
1394 depends on !ARCH_MSM
1396 Say Y here to experiment with turning CPUs off and on. CPUs
1397 can be controlled through /sys/devices/system/cpu.
1400 bool "Use local timer interrupts"
1403 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1405 Enable support for local timers on SMP platforms, rather then the
1406 legacy IPI broadcast method. Local timers allows the system
1407 accounting to be spread across the timer interval, preventing a
1408 "thundering herd" at every timer tick.
1410 source kernel/Kconfig.preempt
1414 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1415 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1416 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1417 default AT91_TIMER_HZ if ARCH_AT91
1418 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1421 config THUMB2_KERNEL
1422 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1423 depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
1425 select ARM_ASM_UNIFIED
1427 By enabling this option, the kernel will be compiled in
1428 Thumb-2 mode. A compiler/assembler that understand the unified
1429 ARM-Thumb syntax is needed.
1433 config ARM_ASM_UNIFIED
1437 bool "Use the ARM EABI to compile the kernel"
1439 This option allows for the kernel to be compiled using the latest
1440 ARM ABI (aka EABI). This is only useful if you are using a user
1441 space environment that is also compiled with EABI.
1443 Since there are major incompatibilities between the legacy ABI and
1444 EABI, especially with regard to structure member alignment, this
1445 option also changes the kernel syscall calling convention to
1446 disambiguate both ABIs and allow for backward compatibility support
1447 (selected with CONFIG_OABI_COMPAT).
1449 To use this you need GCC version 4.0.0 or later.
1452 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1453 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1456 This option preserves the old syscall interface along with the
1457 new (ARM EABI) one. It also provides a compatibility layer to
1458 intercept syscalls that have structure arguments which layout
1459 in memory differs between the legacy ABI and the new ARM EABI
1460 (only for non "thumb" binaries). This option adds a tiny
1461 overhead to all syscalls and produces a slightly larger kernel.
1462 If you know you'll be using only pure EABI user space then you
1463 can say N here. If this option is not selected and you attempt
1464 to execute a legacy ABI binary then the result will be
1465 UNPREDICTABLE (in fact it can be predicted that it won't work
1466 at all). If in doubt say Y.
1468 config ARCH_HAS_HOLES_MEMORYMODEL
1471 config ARCH_SPARSEMEM_ENABLE
1474 config ARCH_SPARSEMEM_DEFAULT
1475 def_bool ARCH_SPARSEMEM_ENABLE
1477 config ARCH_SELECT_MEMORY_MODEL
1478 def_bool ARCH_SPARSEMEM_ENABLE
1481 bool "High Memory Support (EXPERIMENTAL)"
1482 depends on MMU && EXPERIMENTAL
1484 The address space of ARM processors is only 4 Gigabytes large
1485 and it has to accommodate user address space, kernel address
1486 space as well as some memory mapped IO. That means that, if you
1487 have a large amount of physical memory and/or IO, not all of the
1488 memory can be "permanently mapped" by the kernel. The physical
1489 memory that is not permanently mapped is called "high memory".
1491 Depending on the selected kernel/user memory split, minimum
1492 vmalloc space and actual amount of RAM, you may not need this
1493 option which should result in a slightly faster kernel.
1498 bool "Allocate 2nd-level pagetables from highmem"
1500 depends on !OUTER_CACHE
1502 config HW_PERF_EVENTS
1503 bool "Enable hardware performance counter support for perf events"
1504 depends on PERF_EVENTS && CPU_HAS_PMU
1507 Enable hardware performance counter support for perf events. If
1508 disabled, perf events will use software events only.
1512 config FORCE_MAX_ZONEORDER
1513 int "Maximum zone order" if ARCH_SHMOBILE
1514 range 11 64 if ARCH_SHMOBILE
1515 default "9" if SA1111
1518 The kernel memory allocator divides physically contiguous memory
1519 blocks into "zones", where each zone is a power of two number of
1520 pages. This option selects the largest power of two that the kernel
1521 keeps in the memory allocator. If you need to allocate very large
1522 blocks of physically contiguous memory, then you may need to
1523 increase this value.
1525 This config option is actually maximum order plus one. For example,
1526 a value of 11 means that the largest free memory block is 2^10 pages.
1529 bool "Timer and CPU usage LEDs"
1530 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1531 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1532 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1533 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1534 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1535 ARCH_AT91 || ARCH_DAVINCI || \
1536 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1538 If you say Y here, the LEDs on your machine will be used
1539 to provide useful information about your current system status.
1541 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1542 be able to select which LEDs are active using the options below. If
1543 you are compiling a kernel for the EBSA-110 or the LART however, the
1544 red LED will simply flash regularly to indicate that the system is
1545 still functional. It is safe to say Y here if you have a CATS
1546 system, but the driver will do nothing.
1549 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1550 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1551 || MACH_OMAP_PERSEUS2
1553 depends on !GENERIC_CLOCKEVENTS
1554 default y if ARCH_EBSA110
1556 If you say Y here, one of the system LEDs (the green one on the
1557 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1558 will flash regularly to indicate that the system is still
1559 operational. This is mainly useful to kernel hackers who are
1560 debugging unstable kernels.
1562 The LART uses the same LED for both Timer LED and CPU usage LED
1563 functions. You may choose to use both, but the Timer LED function
1564 will overrule the CPU usage LED.
1567 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1569 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1570 || MACH_OMAP_PERSEUS2
1573 If you say Y here, the red LED will be used to give a good real
1574 time indication of CPU usage, by lighting whenever the idle task
1575 is not currently executing.
1577 The LART uses the same LED for both Timer LED and CPU usage LED
1578 functions. You may choose to use both, but the Timer LED function
1579 will overrule the CPU usage LED.
1581 config ALIGNMENT_TRAP
1583 depends on CPU_CP15_MMU
1584 default y if !ARCH_EBSA110
1585 select HAVE_PROC_CPU if PROC_FS
1587 ARM processors cannot fetch/store information which is not
1588 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1589 address divisible by 4. On 32-bit ARM processors, these non-aligned
1590 fetch/store instructions will be emulated in software if you say
1591 here, which has a severe performance impact. This is necessary for
1592 correct operation of some network protocols. With an IP-only
1593 configuration it is safe to say N, otherwise say Y.
1595 config UACCESS_WITH_MEMCPY
1596 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1597 depends on MMU && EXPERIMENTAL
1598 default y if CPU_FEROCEON
1600 Implement faster copy_to_user and clear_user methods for CPU
1601 cores where a 8-word STM instruction give significantly higher
1602 memory write throughput than a sequence of individual 32bit stores.
1604 A possible side effect is a slight increase in scheduling latency
1605 between threads sharing the same address space if they invoke
1606 such copy operations with large buffers.
1608 However, if the CPU data cache is using a write-allocate mode,
1609 this option is unlikely to provide any performance gain.
1613 prompt "Enable seccomp to safely compute untrusted bytecode"
1615 This kernel feature is useful for number crunching applications
1616 that may need to compute untrusted bytecode during their
1617 execution. By using pipes or other transports made available to
1618 the process as file descriptors supporting the read/write
1619 syscalls, it's possible to isolate those applications in
1620 their own address space using seccomp. Once seccomp is
1621 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1622 and the task is only allowed to execute a few safe syscalls
1623 defined by each seccomp mode.
1625 config CC_STACKPROTECTOR
1626 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1627 depends on EXPERIMENTAL
1629 This option turns on the -fstack-protector GCC feature. This
1630 feature puts, at the beginning of functions, a canary value on
1631 the stack just before the return address, and validates
1632 the value just before actually returning. Stack based buffer
1633 overflows (that need to overwrite this return address) now also
1634 overwrite the canary, which gets detected and the attack is then
1635 neutralized via a kernel panic.
1636 This feature requires gcc version 4.2 or above.
1638 config DEPRECATED_PARAM_STRUCT
1639 bool "Provide old way to pass kernel parameters"
1641 This was deprecated in 2001 and announced to live on for 5 years.
1642 Some old boot loaders still use this way.
1648 # Compressed boot loader in ROM. Yes, we really want to ask about
1649 # TEXT and BSS so we preserve their values in the config files.
1650 config ZBOOT_ROM_TEXT
1651 hex "Compressed ROM boot loader base address"
1654 The physical address at which the ROM-able zImage is to be
1655 placed in the target. Platforms which normally make use of
1656 ROM-able zImage formats normally set this to a suitable
1657 value in their defconfig file.
1659 If ZBOOT_ROM is not enabled, this has no effect.
1661 config ZBOOT_ROM_BSS
1662 hex "Compressed ROM boot loader BSS address"
1665 The base address of an area of read/write memory in the target
1666 for the ROM-able zImage which must be available while the
1667 decompressor is running. It must be large enough to hold the
1668 entire decompressed kernel plus an additional 128 KiB.
1669 Platforms which normally make use of ROM-able zImage formats
1670 normally set this to a suitable value in their defconfig file.
1672 If ZBOOT_ROM is not enabled, this has no effect.
1675 bool "Compressed boot loader in ROM/flash"
1676 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1678 Say Y here if you intend to execute your compressed kernel image
1679 (zImage) directly from ROM or flash. If unsure, say N.
1681 config ZBOOT_ROM_MMCIF
1682 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1683 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1685 Say Y here to include experimental MMCIF loading code in the
1686 ROM-able zImage. With this enabled it is possible to write the
1687 the ROM-able zImage kernel image to an MMC card and boot the
1688 kernel straight from the reset vector. At reset the processor
1689 Mask ROM will load the first part of the the ROM-able zImage
1690 which in turn loads the rest the kernel image to RAM using the
1691 MMCIF hardware block.
1694 string "Default kernel command string"
1697 On some architectures (EBSA110 and CATS), there is currently no way
1698 for the boot loader to pass arguments to the kernel. For these
1699 architectures, you should supply some command-line options at build
1700 time by entering them here. As a minimum, you should specify the
1701 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1703 config CMDLINE_FORCE
1704 bool "Always use the default kernel command string"
1705 depends on CMDLINE != ""
1707 Always use the default kernel command string, even if the boot
1708 loader passes other arguments to the kernel.
1709 This is useful if you cannot or don't want to change the
1710 command-line options your boot loader passes to the kernel.
1715 bool "Kernel Execute-In-Place from ROM"
1716 depends on !ZBOOT_ROM
1718 Execute-In-Place allows the kernel to run from non-volatile storage
1719 directly addressable by the CPU, such as NOR flash. This saves RAM
1720 space since the text section of the kernel is not loaded from flash
1721 to RAM. Read-write sections, such as the data section and stack,
1722 are still copied to RAM. The XIP kernel is not compressed since
1723 it has to run directly from flash, so it will take more space to
1724 store it. The flash address used to link the kernel object files,
1725 and for storing it, is configuration dependent. Therefore, if you
1726 say Y here, you must know the proper physical address where to
1727 store the kernel image depending on your own flash memory usage.
1729 Also note that the make target becomes "make xipImage" rather than
1730 "make zImage" or "make Image". The final kernel binary to put in
1731 ROM memory will be arch/arm/boot/xipImage.
1735 config XIP_PHYS_ADDR
1736 hex "XIP Kernel Physical Location"
1737 depends on XIP_KERNEL
1738 default "0x00080000"
1740 This is the physical address in your flash memory the kernel will
1741 be linked for and stored to. This address is dependent on your
1745 bool "Kexec system call (EXPERIMENTAL)"
1746 depends on EXPERIMENTAL
1748 kexec is a system call that implements the ability to shutdown your
1749 current kernel, and to start another kernel. It is like a reboot
1750 but it is independent of the system firmware. And like a reboot
1751 you can start any kernel with it, not just Linux.
1753 It is an ongoing process to be certain the hardware in a machine
1754 is properly shutdown, so do not be surprised if this code does not
1755 initially work for you. It may help to enable device hotplugging
1759 bool "Export atags in procfs"
1763 Should the atags used to boot the kernel be exported in an "atags"
1764 file in procfs. Useful with kexec.
1767 bool "Build kdump crash kernel (EXPERIMENTAL)"
1768 depends on EXPERIMENTAL
1770 Generate crash dump after being started by kexec. This should
1771 be normally only set in special crash dump kernels which are
1772 loaded in the main kernel with kexec-tools into a specially
1773 reserved region and then later executed after a crash by
1774 kdump/kexec. The crash dump kernel must be compiled to a
1775 memory address not used by the main kernel
1777 For more details see Documentation/kdump/kdump.txt
1779 config AUTO_ZRELADDR
1780 bool "Auto calculation of the decompressed kernel image address"
1781 depends on !ZBOOT_ROM && !ARCH_U300
1783 ZRELADDR is the physical address where the decompressed kernel
1784 image will be placed. If AUTO_ZRELADDR is selected, the address
1785 will be determined at run-time by masking the current IP with
1786 0xf8000000. This assumes the zImage being placed in the first 128MB
1787 from start of memory.
1791 menu "CPU Power Management"
1795 source "drivers/cpufreq/Kconfig"
1798 tristate "CPUfreq driver for i.MX CPUs"
1799 depends on ARCH_MXC && CPU_FREQ
1801 This enables the CPUfreq driver for i.MX CPUs.
1803 config CPU_FREQ_SA1100
1806 config CPU_FREQ_SA1110
1809 config CPU_FREQ_INTEGRATOR
1810 tristate "CPUfreq driver for ARM Integrator CPUs"
1811 depends on ARCH_INTEGRATOR && CPU_FREQ
1814 This enables the CPUfreq driver for ARM Integrator CPUs.
1816 For details, take a look at <file:Documentation/cpu-freq>.
1822 depends on CPU_FREQ && ARCH_PXA && PXA25x
1824 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1826 config CPU_FREQ_S3C64XX
1827 bool "CPUfreq support for Samsung S3C64XX CPUs"
1828 depends on CPU_FREQ && CPU_S3C6410
1833 Internal configuration node for common cpufreq on Samsung SoC
1835 config CPU_FREQ_S3C24XX
1836 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1837 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1840 This enables the CPUfreq driver for the Samsung S3C24XX family
1843 For details, take a look at <file:Documentation/cpu-freq>.
1847 config CPU_FREQ_S3C24XX_PLL
1848 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1849 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1851 Compile in support for changing the PLL frequency from the
1852 S3C24XX series CPUfreq driver. The PLL takes time to settle
1853 after a frequency change, so by default it is not enabled.
1855 This also means that the PLL tables for the selected CPU(s) will
1856 be built which may increase the size of the kernel image.
1858 config CPU_FREQ_S3C24XX_DEBUG
1859 bool "Debug CPUfreq Samsung driver core"
1860 depends on CPU_FREQ_S3C24XX
1862 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1864 config CPU_FREQ_S3C24XX_IODEBUG
1865 bool "Debug CPUfreq Samsung driver IO timing"
1866 depends on CPU_FREQ_S3C24XX
1868 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1870 config CPU_FREQ_S3C24XX_DEBUGFS
1871 bool "Export debugfs for CPUFreq"
1872 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1874 Export status information via debugfs.
1878 source "drivers/cpuidle/Kconfig"
1882 menu "Floating point emulation"
1884 comment "At least one emulation must be selected"
1887 bool "NWFPE math emulation"
1888 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1890 Say Y to include the NWFPE floating point emulator in the kernel.
1891 This is necessary to run most binaries. Linux does not currently
1892 support floating point hardware so you need to say Y here even if
1893 your machine has an FPA or floating point co-processor podule.
1895 You may say N here if you are going to load the Acorn FPEmulator
1896 early in the bootup.
1899 bool "Support extended precision"
1900 depends on FPE_NWFPE
1902 Say Y to include 80-bit support in the kernel floating-point
1903 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1904 Note that gcc does not generate 80-bit operations by default,
1905 so in most cases this option only enlarges the size of the
1906 floating point emulator without any good reason.
1908 You almost surely want to say N here.
1911 bool "FastFPE math emulation (EXPERIMENTAL)"
1912 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1914 Say Y here to include the FAST floating point emulator in the kernel.
1915 This is an experimental much faster emulator which now also has full
1916 precision for the mantissa. It does not support any exceptions.
1917 It is very simple, and approximately 3-6 times faster than NWFPE.
1919 It should be sufficient for most programs. It may be not suitable
1920 for scientific calculations, but you have to check this for yourself.
1921 If you do not feel you need a faster FP emulation you should better
1925 bool "VFP-format floating point maths"
1926 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1928 Say Y to include VFP support code in the kernel. This is needed
1929 if your hardware includes a VFP unit.
1931 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1932 release notes and additional status information.
1934 Say N if your target does not have VFP hardware.
1942 bool "Advanced SIMD (NEON) Extension support"
1943 depends on VFPv3 && CPU_V7
1945 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1950 menu "Userspace binary formats"
1952 source "fs/Kconfig.binfmt"
1955 tristate "RISC OS personality"
1958 Say Y here to include the kernel code necessary if you want to run
1959 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1960 experimental; if this sounds frightening, say N and sleep in peace.
1961 You can also say M here to compile this support as a module (which
1962 will be called arthur).
1966 menu "Power management options"
1968 source "kernel/power/Kconfig"
1970 config ARCH_SUSPEND_POSSIBLE
1975 source "net/Kconfig"
1977 source "drivers/Kconfig"
1981 source "arch/arm/Kconfig.debug"
1983 source "security/Kconfig"
1985 source "crypto/Kconfig"
1987 source "lib/Kconfig"