4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_MMAP_RND_BITS if MMU
41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42 select HAVE_ARCH_TRACEHOOK
43 select HAVE_ARM_SMCCC if CPU_V7
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CONTEXT_TRACKING
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
51 select HAVE_DMA_CONTIGUOUS if MMU
52 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
53 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
57 select HAVE_GENERIC_DMA_COHERENT
58 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
59 select HAVE_IDE if PCI || ISA || PCMCIA
60 select HAVE_IRQ_TIME_ACCOUNTING
61 select HAVE_KERNEL_GZIP
62 select HAVE_KERNEL_LZ4
63 select HAVE_KERNEL_LZMA
64 select HAVE_KERNEL_LZO
66 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
67 select HAVE_KRETPROBES if (HAVE_KPROBES)
69 select HAVE_MOD_ARCH_SPECIFIC
70 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
71 select HAVE_OPTPROBES if !THUMB2_KERNEL
72 select HAVE_PERF_EVENTS
74 select HAVE_PERF_USER_STACK_DUMP
75 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
76 select HAVE_REGS_AND_STACK_ACCESS_API
77 select HAVE_SYSCALL_TRACEPOINTS
79 select HAVE_VIRT_CPU_ACCOUNTING_GEN
80 select IRQ_FORCED_THREADING
81 select MODULES_USE_ELF_REL
83 select OF_EARLY_FLATTREE if OF
84 select OF_RESERVED_MEM if OF
86 select OLD_SIGSUSPEND3
87 select PERF_USE_VMALLOC
89 select SYS_SUPPORTS_APM_EMULATION
90 # Above selects are sorted alphabetically; please add new ones
91 # according to that. Thanks.
93 The ARM series is a line of low-power-consumption RISC chip designs
94 licensed by ARM Ltd and targeted at embedded applications and
95 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
96 manufactured, but legacy ARM-based PC hardware remains popular in
97 Europe. There is an ARM Linux project with a web page at
98 <http://www.arm.linux.org.uk/>.
100 config ARM_HAS_SG_CHAIN
101 select ARCH_HAS_SG_CHAIN
104 config NEED_SG_DMA_LENGTH
107 config ARM_DMA_USE_IOMMU
109 select ARM_HAS_SG_CHAIN
110 select NEED_SG_DMA_LENGTH
114 config ARM_DMA_IOMMU_ALIGNMENT
115 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
119 DMA mapping framework by default aligns all buffers to the smallest
120 PAGE_SIZE order which is greater than or equal to the requested buffer
121 size. This works well for buffers up to a few hundreds kilobytes, but
122 for larger buffers it just a waste of address space. Drivers which has
123 relatively small addressing window (like 64Mib) might run out of
124 virtual space with just a few allocations.
126 With this parameter you can specify the maximum PAGE_SIZE order for
127 DMA IOMMU buffers. Larger buffers will be aligned only to this
128 specified order. The order is expressed as a power of two multiplied
133 config MIGHT_HAVE_PCI
136 config SYS_SUPPORTS_APM_EMULATION
141 select GENERIC_ALLOCATOR
152 The Extended Industry Standard Architecture (EISA) bus was
153 developed as an open alternative to the IBM MicroChannel bus.
155 The EISA bus provided some of the features of the IBM MicroChannel
156 bus while maintaining backward compatibility with cards made for
157 the older ISA bus. The EISA bus saw limited use between 1988 and
158 1995 when it was made obsolete by the PCI bus.
160 Say Y here if you are building a kernel for an EISA-based machine.
167 config STACKTRACE_SUPPORT
171 config HAVE_LATENCYTOP_SUPPORT
176 config LOCKDEP_SUPPORT
180 config TRACE_IRQFLAGS_SUPPORT
184 config RWSEM_XCHGADD_ALGORITHM
188 config ARCH_HAS_ILOG2_U32
191 config ARCH_HAS_ILOG2_U64
194 config ARCH_HAS_BANDGAP
197 config FIX_EARLYCON_MEM
200 config GENERIC_HWEIGHT
204 config GENERIC_CALIBRATE_DELAY
208 config ARCH_MAY_HAVE_PC_FDC
214 config NEED_DMA_MAP_STATE
217 config ARCH_SUPPORTS_UPROBES
220 config ARCH_HAS_DMA_SET_COHERENT_MASK
223 config GENERIC_ISA_DMA
229 config NEED_RET_TO_USER
237 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
238 default DRAM_BASE if REMAP_VECTORS_TO_RAM
241 The base address of exception vectors. This must be two pages
244 config ARM_PATCH_PHYS_VIRT
245 bool "Patch physical to virtual translations at runtime" if EMBEDDED
247 depends on !XIP_KERNEL && MMU
248 depends on !ARCH_REALVIEW || !SPARSEMEM
250 Patch phys-to-virt and virt-to-phys translation functions at
251 boot and module load time according to the position of the
252 kernel in system memory.
254 This can only be used with non-XIP MMU kernels where the base
255 of physical memory is at a 16MB boundary.
257 Only disable this option if you know that you do not require
258 this feature (eg, building a kernel for a single machine) and
259 you need to shrink the kernel to the minimal size.
261 config NEED_MACH_IO_H
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT
278 default DRAM_BASE if !MMU
279 default 0x00000000 if ARCH_EBSA110 || \
284 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
285 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
286 default 0x20000000 if ARCH_S5PV210
287 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
288 default 0xc0000000 if ARCH_SA1100
290 Please provide the physical address corresponding to the
291 location of main memory in your system.
297 config PGTABLE_LEVELS
299 default 3 if ARM_LPAE
302 source "init/Kconfig"
304 source "kernel/Kconfig.freezer"
309 bool "MMU-based Paged Memory Management Support"
312 Select if you want MMU-based virtualised addressing space
313 support by paged memory management. If unsure, say 'Y'.
315 config ARCH_MMAP_RND_BITS_MIN
318 config ARCH_MMAP_RND_BITS_MAX
319 default 14 if PAGE_OFFSET=0x40000000
320 default 15 if PAGE_OFFSET=0x80000000
324 # The "ARM system type" choice list is ordered alphabetically by option
325 # text. Please add new entries in the option alphabetic order.
328 prompt "ARM system type"
329 default ARCH_VERSATILE if !MMU
330 default ARCH_MULTIPLATFORM if MMU
332 config ARCH_MULTIPLATFORM
333 bool "Allow multiple platforms to be selected"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_HAS_SG_CHAIN
337 select ARM_PATCH_PHYS_VIRT
341 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select MULTI_IRQ_HANDLER
347 config ARM_SINGLE_ARMV7M
348 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
356 select GENERIC_CLOCKEVENTS
362 bool "ARM Ltd. RealView family"
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 select ARM_TIMER_SP804
367 select COMMON_CLK_VERSATILE
368 select GENERIC_CLOCKEVENTS
369 select GPIO_PL061 if GPIOLIB
371 select NEED_MACH_MEMORY_H
372 select PLAT_VERSATILE
373 select PLAT_VERSATILE_SCHED_CLOCK
375 This enables support for ARM Ltd RealView boards.
377 config ARCH_VERSATILE
378 bool "ARM Ltd. Versatile family"
379 select ARCH_WANT_OPTIONAL_GPIOLIB
381 select ARM_TIMER_SP804
384 select GENERIC_CLOCKEVENTS
385 select HAVE_MACH_CLKDEV
387 select PLAT_VERSATILE
388 select PLAT_VERSATILE_CLOCK
389 select PLAT_VERSATILE_SCHED_CLOCK
390 select VERSATILE_FPGA_IRQ
392 This enables support for ARM Ltd Versatile board.
395 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
396 select ARCH_REQUIRE_GPIOLIB
401 select GENERIC_CLOCKEVENTS
405 Support for Cirrus Logic 711x/721x/731x based boards.
408 bool "Cortina Systems Gemini"
409 select ARCH_REQUIRE_GPIOLIB
412 select GENERIC_CLOCKEVENTS
414 Support for the Cortina Systems Gemini family SoCs
418 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_IO_H
422 select NEED_MACH_MEMORY_H
425 This is an evaluation board for the StrongARM processor available
426 from Digital. It has limited hardware on-board, including an
427 Ethernet interface, two PCMCIA sockets, two serial ports and a
432 select ARCH_HAS_HOLES_MEMORYMODEL
433 select ARCH_REQUIRE_GPIOLIB
435 select ARM_PATCH_PHYS_VIRT
441 select GENERIC_CLOCKEVENTS
443 This enables support for the Cirrus EP93xx series of CPUs.
445 config ARCH_FOOTBRIDGE
449 select GENERIC_CLOCKEVENTS
451 select NEED_MACH_IO_H if !MMU
452 select NEED_MACH_MEMORY_H
454 Support for systems based on the DC21285 companion chip
455 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
458 bool "Hilscher NetX based"
462 select GENERIC_CLOCKEVENTS
464 This enables support for systems based on the Hilscher NetX Soc
470 select NEED_MACH_MEMORY_H
471 select NEED_RET_TO_USER
477 Support for Intel's IOP13XX (XScale) family of processors.
482 select ARCH_REQUIRE_GPIOLIB
485 select NEED_RET_TO_USER
489 Support for Intel's 80219 and IOP32X (XScale) family of
495 select ARCH_REQUIRE_GPIOLIB
498 select NEED_RET_TO_USER
502 Support for Intel's IOP33X (XScale) family of processors.
507 select ARCH_HAS_DMA_SET_COHERENT_MASK
508 select ARCH_REQUIRE_GPIOLIB
509 select ARCH_SUPPORTS_BIG_ENDIAN
512 select DMABOUNCE if PCI
513 select GENERIC_CLOCKEVENTS
514 select MIGHT_HAVE_PCI
515 select NEED_MACH_IO_H
516 select USB_EHCI_BIG_ENDIAN_DESC
517 select USB_EHCI_BIG_ENDIAN_MMIO
519 Support for Intel's IXP4XX (XScale) family of processors.
523 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
526 select MIGHT_HAVE_PCI
530 select PLAT_ORION_LEGACY
532 Support for the Marvell Dove SoC 88AP510
535 bool "Marvell MV78xx0"
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
541 select PLAT_ORION_LEGACY
543 Support for the following Marvell MV78xx0 series SoCs:
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 select PLAT_ORION_LEGACY
555 select MULTI_IRQ_HANDLER
557 Support for the following Marvell Orion 5x series SoCs:
558 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
559 Orion-2 (5281), Orion-1-90 (6183).
562 bool "Marvell PXA168/910/MMP2"
564 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_ALLOCATOR
567 select GENERIC_CLOCKEVENTS
570 select MULTI_IRQ_HANDLER
575 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
578 bool "Micrel/Kendin KS8695"
579 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select NEED_MACH_MEMORY_H
585 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
586 System-on-Chip devices.
589 bool "Nuvoton W90X900 CPU"
590 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
596 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
597 At present, the w90x900 has been renamed nuc900, regarding
598 the ARM series product line, you can login the following
599 link address to know more.
601 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
602 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
606 select ARCH_REQUIRE_GPIOLIB
611 select GENERIC_CLOCKEVENTS
615 Support for the NXP LPC32XX family of processors
618 bool "PXA2xx/PXA3xx-based"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM
629 select GENERIC_CLOCKEVENTS
633 select MULTI_IRQ_HANDLER
637 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
643 select ARCH_MAY_HAVE_PC_FDC
644 select ARCH_SPARSEMEM_ENABLE
645 select ARCH_USES_GETTIMEOFFSET
649 select HAVE_PATA_PLATFORM
651 select NEED_MACH_IO_H
652 select NEED_MACH_MEMORY_H
656 On the Acorn Risc-PC, Linux can support the internal IDE disk and
657 CD-ROM interface, serial and parallel port, and the floppy drive.
662 select ARCH_REQUIRE_GPIOLIB
663 select ARCH_SPARSEMEM_ENABLE
667 select CLKSRC_OF if OF
670 select GENERIC_CLOCKEVENTS
674 select MULTI_IRQ_HANDLER
675 select NEED_MACH_MEMORY_H
678 Support for StrongARM 11x0 based boards.
681 bool "Samsung S3C24XX SoCs"
682 select ARCH_REQUIRE_GPIOLIB
685 select CLKSRC_SAMSUNG_PWM
686 select GENERIC_CLOCKEVENTS
688 select HAVE_S3C2410_I2C if I2C
689 select HAVE_S3C2410_WATCHDOG if WATCHDOG
690 select HAVE_S3C_RTC if RTC_CLASS
691 select MULTI_IRQ_HANDLER
692 select NEED_MACH_IO_H
695 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
696 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
697 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
698 Samsung SMDK2410 development board (and derivatives).
701 bool "Samsung S3C64XX"
702 select ARCH_REQUIRE_GPIOLIB
707 select CLKSRC_SAMSUNG_PWM
708 select COMMON_CLK_SAMSUNG
710 select GENERIC_CLOCKEVENTS
712 select HAVE_S3C2410_I2C if I2C
713 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 select PM_GENERIC_DOMAINS if PM
719 select S3C_GPIO_TRACK
721 select SAMSUNG_WAKEMASK
722 select SAMSUNG_WDT_RESET
724 Samsung S3C64XX series based systems
728 select ARCH_HAS_HOLES_MEMORYMODEL
729 select ARCH_REQUIRE_GPIOLIB
731 select GENERIC_ALLOCATOR
732 select GENERIC_CLOCKEVENTS
733 select GENERIC_IRQ_CHIP
738 Support for TI's DaVinci platform.
743 select ARCH_HAS_HOLES_MEMORYMODEL
745 select ARCH_REQUIRE_GPIOLIB
748 select GENERIC_CLOCKEVENTS
749 select GENERIC_IRQ_CHIP
752 select MULTI_IRQ_HANDLER
753 select NEED_MACH_IO_H if PCCARD
754 select NEED_MACH_MEMORY_H
757 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
761 menu "Multiple platform selection"
762 depends on ARCH_MULTIPLATFORM
764 comment "CPU Core family selection"
767 bool "ARMv4 based platforms (FA526)"
768 depends on !ARCH_MULTI_V6_V7
769 select ARCH_MULTI_V4_V5
772 config ARCH_MULTI_V4T
773 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
774 depends on !ARCH_MULTI_V6_V7
775 select ARCH_MULTI_V4_V5
776 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
777 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
778 CPU_ARM925T || CPU_ARM940T)
781 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
782 depends on !ARCH_MULTI_V6_V7
783 select ARCH_MULTI_V4_V5
784 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
785 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
786 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
788 config ARCH_MULTI_V4_V5
792 bool "ARMv6 based platforms (ARM11)"
793 select ARCH_MULTI_V6_V7
797 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
799 select ARCH_MULTI_V6_V7
803 config ARCH_MULTI_V6_V7
805 select MIGHT_HAVE_CACHE_L2X0
807 config ARCH_MULTI_CPU_AUTO
808 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
814 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
817 select ARM_GIC_V2M if PCI_MSI
820 select HAVE_ARM_ARCH_TIMER
823 # This is sorted alphabetically by mach-* pathname. However, plat-*
824 # Kconfigs may be included either alphabetically (according to the
825 # plat- suffix) or along side the corresponding mach-* source.
827 source "arch/arm/mach-mvebu/Kconfig"
829 source "arch/arm/mach-alpine/Kconfig"
831 source "arch/arm/mach-asm9260/Kconfig"
833 source "arch/arm/mach-at91/Kconfig"
835 source "arch/arm/mach-axxia/Kconfig"
837 source "arch/arm/mach-bcm/Kconfig"
839 source "arch/arm/mach-berlin/Kconfig"
841 source "arch/arm/mach-clps711x/Kconfig"
843 source "arch/arm/mach-cns3xxx/Kconfig"
845 source "arch/arm/mach-davinci/Kconfig"
847 source "arch/arm/mach-digicolor/Kconfig"
849 source "arch/arm/mach-dove/Kconfig"
851 source "arch/arm/mach-ep93xx/Kconfig"
853 source "arch/arm/mach-footbridge/Kconfig"
855 source "arch/arm/mach-gemini/Kconfig"
857 source "arch/arm/mach-highbank/Kconfig"
859 source "arch/arm/mach-hisi/Kconfig"
861 source "arch/arm/mach-integrator/Kconfig"
863 source "arch/arm/mach-iop32x/Kconfig"
865 source "arch/arm/mach-iop33x/Kconfig"
867 source "arch/arm/mach-iop13xx/Kconfig"
869 source "arch/arm/mach-ixp4xx/Kconfig"
871 source "arch/arm/mach-keystone/Kconfig"
873 source "arch/arm/mach-ks8695/Kconfig"
875 source "arch/arm/mach-meson/Kconfig"
877 source "arch/arm/mach-moxart/Kconfig"
879 source "arch/arm/mach-mv78xx0/Kconfig"
881 source "arch/arm/mach-imx/Kconfig"
883 source "arch/arm/mach-mediatek/Kconfig"
885 source "arch/arm/mach-mxs/Kconfig"
887 source "arch/arm/mach-netx/Kconfig"
889 source "arch/arm/mach-nomadik/Kconfig"
891 source "arch/arm/mach-nspire/Kconfig"
893 source "arch/arm/plat-omap/Kconfig"
895 source "arch/arm/mach-omap1/Kconfig"
897 source "arch/arm/mach-omap2/Kconfig"
899 source "arch/arm/mach-orion5x/Kconfig"
901 source "arch/arm/mach-picoxcell/Kconfig"
903 source "arch/arm/mach-pxa/Kconfig"
904 source "arch/arm/plat-pxa/Kconfig"
906 source "arch/arm/mach-mmp/Kconfig"
908 source "arch/arm/mach-qcom/Kconfig"
910 source "arch/arm/mach-realview/Kconfig"
912 source "arch/arm/mach-rockchip/Kconfig"
914 source "arch/arm/mach-sa1100/Kconfig"
916 source "arch/arm/mach-socfpga/Kconfig"
918 source "arch/arm/mach-spear/Kconfig"
920 source "arch/arm/mach-sti/Kconfig"
922 source "arch/arm/mach-s3c24xx/Kconfig"
924 source "arch/arm/mach-s3c64xx/Kconfig"
926 source "arch/arm/mach-s5pv210/Kconfig"
928 source "arch/arm/mach-exynos/Kconfig"
929 source "arch/arm/plat-samsung/Kconfig"
931 source "arch/arm/mach-shmobile/Kconfig"
933 source "arch/arm/mach-sunxi/Kconfig"
935 source "arch/arm/mach-prima2/Kconfig"
937 source "arch/arm/mach-tegra/Kconfig"
939 source "arch/arm/mach-u300/Kconfig"
941 source "arch/arm/mach-uniphier/Kconfig"
943 source "arch/arm/mach-ux500/Kconfig"
945 source "arch/arm/mach-versatile/Kconfig"
947 source "arch/arm/mach-vexpress/Kconfig"
948 source "arch/arm/plat-versatile/Kconfig"
950 source "arch/arm/mach-vt8500/Kconfig"
952 source "arch/arm/mach-w90x900/Kconfig"
954 source "arch/arm/mach-zx/Kconfig"
956 source "arch/arm/mach-zynq/Kconfig"
958 # ARMv7-M architecture
960 bool "Energy Micro efm32"
961 depends on ARM_SINGLE_ARMV7M
962 select ARCH_REQUIRE_GPIOLIB
964 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
968 bool "NXP LPC18xx/LPC43xx"
969 depends on ARM_SINGLE_ARMV7M
970 select ARCH_HAS_RESET_CONTROLLER
972 select CLKSRC_LPC32XX
975 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
976 high performance microcontrollers.
979 bool "STMicrolectronics STM32"
980 depends on ARM_SINGLE_ARMV7M
981 select ARCH_HAS_RESET_CONTROLLER
982 select ARMV7M_SYSTICK
984 select RESET_CONTROLLER
986 Support for STMicroelectronics STM32 processors.
988 # Definitions to make life easier
994 select GENERIC_CLOCKEVENTS
1000 select GENERIC_IRQ_CHIP
1003 config PLAT_ORION_LEGACY
1010 config PLAT_VERSATILE
1013 source "arch/arm/firmware/Kconfig"
1015 source arch/arm/mm/Kconfig
1018 bool "Enable iWMMXt support"
1019 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1020 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1022 Enable support for iWMMXt context switching at run time if
1023 running on a CPU that supports it.
1025 config MULTI_IRQ_HANDLER
1028 Allow each machine to specify it's own IRQ handler at run time.
1031 source "arch/arm/Kconfig-nommu"
1034 config PJ4B_ERRATA_4742
1035 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1036 depends on CPU_PJ4B && MACH_ARMADA_370
1039 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1040 Event (WFE) IDLE states, a specific timing sensitivity exists between
1041 the retiring WFI/WFE instructions and the newly issued subsequent
1042 instructions. This sensitivity can result in a CPU hang scenario.
1044 The software must insert either a Data Synchronization Barrier (DSB)
1045 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1048 config ARM_ERRATA_326103
1049 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1052 Executing a SWP instruction to read-only memory does not set bit 11
1053 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1054 treat the access as a read, preventing a COW from occurring and
1055 causing the faulting task to livelock.
1057 config ARM_ERRATA_411920
1058 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1059 depends on CPU_V6 || CPU_V6K
1061 Invalidation of the Instruction Cache operation can
1062 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1063 It does not affect the MPCore. This option enables the ARM Ltd.
1064 recommended workaround.
1066 config ARM_ERRATA_430973
1067 bool "ARM errata: Stale prediction on replaced interworking branch"
1070 This option enables the workaround for the 430973 Cortex-A8
1071 r1p* erratum. If a code sequence containing an ARM/Thumb
1072 interworking branch is replaced with another code sequence at the
1073 same virtual address, whether due to self-modifying code or virtual
1074 to physical address re-mapping, Cortex-A8 does not recover from the
1075 stale interworking branch prediction. This results in Cortex-A8
1076 executing the new code sequence in the incorrect ARM or Thumb state.
1077 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1078 and also flushes the branch target cache at every context switch.
1079 Note that setting specific bits in the ACTLR register may not be
1080 available in non-secure mode.
1082 config ARM_ERRATA_458693
1083 bool "ARM errata: Processor deadlock when a false hazard is created"
1085 depends on !ARCH_MULTIPLATFORM
1087 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1088 erratum. For very specific sequences of memory operations, it is
1089 possible for a hazard condition intended for a cache line to instead
1090 be incorrectly associated with a different cache line. This false
1091 hazard might then cause a processor deadlock. The workaround enables
1092 the L1 caching of the NEON accesses and disables the PLD instruction
1093 in the ACTLR register. Note that setting specific bits in the ACTLR
1094 register may not be available in non-secure mode.
1096 config ARM_ERRATA_460075
1097 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1099 depends on !ARCH_MULTIPLATFORM
1101 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1102 erratum. Any asynchronous access to the L2 cache may encounter a
1103 situation in which recent store transactions to the L2 cache are lost
1104 and overwritten with stale memory contents from external memory. The
1105 workaround disables the write-allocate mode for the L2 cache via the
1106 ACTLR register. Note that setting specific bits in the ACTLR register
1107 may not be available in non-secure mode.
1109 config ARM_ERRATA_742230
1110 bool "ARM errata: DMB operation may be faulty"
1111 depends on CPU_V7 && SMP
1112 depends on !ARCH_MULTIPLATFORM
1114 This option enables the workaround for the 742230 Cortex-A9
1115 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1116 between two write operations may not ensure the correct visibility
1117 ordering of the two writes. This workaround sets a specific bit in
1118 the diagnostic register of the Cortex-A9 which causes the DMB
1119 instruction to behave as a DSB, ensuring the correct behaviour of
1122 config ARM_ERRATA_742231
1123 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1124 depends on CPU_V7 && SMP
1125 depends on !ARCH_MULTIPLATFORM
1127 This option enables the workaround for the 742231 Cortex-A9
1128 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1129 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1130 accessing some data located in the same cache line, may get corrupted
1131 data due to bad handling of the address hazard when the line gets
1132 replaced from one of the CPUs at the same time as another CPU is
1133 accessing it. This workaround sets specific bits in the diagnostic
1134 register of the Cortex-A9 which reduces the linefill issuing
1135 capabilities of the processor.
1137 config ARM_ERRATA_643719
1138 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1139 depends on CPU_V7 && SMP
1142 This option enables the workaround for the 643719 Cortex-A9 (prior to
1143 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1144 register returns zero when it should return one. The workaround
1145 corrects this value, ensuring cache maintenance operations which use
1146 it behave as intended and avoiding data corruption.
1148 config ARM_ERRATA_720789
1149 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1152 This option enables the workaround for the 720789 Cortex-A9 (prior to
1153 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1154 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1155 As a consequence of this erratum, some TLB entries which should be
1156 invalidated are not, resulting in an incoherency in the system page
1157 tables. The workaround changes the TLB flushing routines to invalidate
1158 entries regardless of the ASID.
1160 config ARM_ERRATA_743622
1161 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1163 depends on !ARCH_MULTIPLATFORM
1165 This option enables the workaround for the 743622 Cortex-A9
1166 (r2p*) erratum. Under very rare conditions, a faulty
1167 optimisation in the Cortex-A9 Store Buffer may lead to data
1168 corruption. This workaround sets a specific bit in the diagnostic
1169 register of the Cortex-A9 which disables the Store Buffer
1170 optimisation, preventing the defect from occurring. This has no
1171 visible impact on the overall performance or power consumption of the
1174 config ARM_ERRATA_751472
1175 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1177 depends on !ARCH_MULTIPLATFORM
1179 This option enables the workaround for the 751472 Cortex-A9 (prior
1180 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1181 completion of a following broadcasted operation if the second
1182 operation is received by a CPU before the ICIALLUIS has completed,
1183 potentially leading to corrupted entries in the cache or TLB.
1185 config ARM_ERRATA_754322
1186 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1189 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1190 r3p*) erratum. A speculative memory access may cause a page table walk
1191 which starts prior to an ASID switch but completes afterwards. This
1192 can populate the micro-TLB with a stale entry which may be hit with
1193 the new ASID. This workaround places two dsb instructions in the mm
1194 switching code so that no page table walks can cross the ASID switch.
1196 config ARM_ERRATA_754327
1197 bool "ARM errata: no automatic Store Buffer drain"
1198 depends on CPU_V7 && SMP
1200 This option enables the workaround for the 754327 Cortex-A9 (prior to
1201 r2p0) erratum. The Store Buffer does not have any automatic draining
1202 mechanism and therefore a livelock may occur if an external agent
1203 continuously polls a memory location waiting to observe an update.
1204 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1205 written polling loops from denying visibility of updates to memory.
1207 config ARM_ERRATA_364296
1208 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1211 This options enables the workaround for the 364296 ARM1136
1212 r0p2 erratum (possible cache data corruption with
1213 hit-under-miss enabled). It sets the undocumented bit 31 in
1214 the auxiliary control register and the FI bit in the control
1215 register, thus disabling hit-under-miss without putting the
1216 processor into full low interrupt latency mode. ARM11MPCore
1219 config ARM_ERRATA_764369
1220 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1221 depends on CPU_V7 && SMP
1223 This option enables the workaround for erratum 764369
1224 affecting Cortex-A9 MPCore with two or more processors (all
1225 current revisions). Under certain timing circumstances, a data
1226 cache line maintenance operation by MVA targeting an Inner
1227 Shareable memory region may fail to proceed up to either the
1228 Point of Coherency or to the Point of Unification of the
1229 system. This workaround adds a DSB instruction before the
1230 relevant cache maintenance functions and sets a specific bit
1231 in the diagnostic control register of the SCU.
1233 config ARM_ERRATA_775420
1234 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1237 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1238 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1239 operation aborts with MMU exception, it might cause the processor
1240 to deadlock. This workaround puts DSB before executing ISB if
1241 an abort may occur on cache maintenance.
1243 config ARM_ERRATA_798181
1244 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1245 depends on CPU_V7 && SMP
1247 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1248 adequately shooting down all use of the old entries. This
1249 option enables the Linux kernel workaround for this erratum
1250 which sends an IPI to the CPUs that are running the same ASID
1251 as the one being invalidated.
1253 config ARM_ERRATA_773022
1254 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1257 This option enables the workaround for the 773022 Cortex-A15
1258 (up to r0p4) erratum. In certain rare sequences of code, the
1259 loop buffer may deliver incorrect instructions. This
1260 workaround disables the loop buffer to avoid the erratum.
1264 source "arch/arm/common/Kconfig"
1271 Find out whether you have ISA slots on your motherboard. ISA is the
1272 name of a bus system, i.e. the way the CPU talks to the other stuff
1273 inside your box. Other bus systems are PCI, EISA, MicroChannel
1274 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1275 newer boards don't support it. If you have ISA, say Y, otherwise N.
1277 # Select ISA DMA controller support
1282 # Select ISA DMA interface
1287 bool "PCI support" if MIGHT_HAVE_PCI
1289 Find out whether you have a PCI motherboard. PCI is the name of a
1290 bus system, i.e. the way the CPU talks to the other stuff inside
1291 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1292 VESA. If you have PCI, say Y, otherwise N.
1298 config PCI_DOMAINS_GENERIC
1299 def_bool PCI_DOMAINS
1301 config PCI_NANOENGINE
1302 bool "BSE nanoEngine PCI support"
1303 depends on SA1100_NANOENGINE
1305 Enable PCI on the BSE nanoEngine board.
1310 config PCI_HOST_ITE8152
1312 depends on PCI && MACH_ARMCORE
1316 source "drivers/pci/Kconfig"
1317 source "drivers/pci/pcie/Kconfig"
1319 source "drivers/pcmcia/Kconfig"
1323 menu "Kernel Features"
1328 This option should be selected by machines which have an SMP-
1331 The only effect of this option is to make the SMP-related
1332 options available to the user for configuration.
1335 bool "Symmetric Multi-Processing"
1336 depends on CPU_V6K || CPU_V7
1337 depends on GENERIC_CLOCKEVENTS
1339 depends on MMU || ARM_MPU
1342 This enables support for systems with more than one CPU. If you have
1343 a system with only one CPU, say N. If you have a system with more
1344 than one CPU, say Y.
1346 If you say N here, the kernel will run on uni- and multiprocessor
1347 machines, but will use only one CPU of a multiprocessor machine. If
1348 you say Y here, the kernel will run on many, but not all,
1349 uniprocessor machines. On a uniprocessor machine, the kernel
1350 will run faster if you say N here.
1352 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1353 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1354 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1356 If you don't know what to do here, say N.
1359 bool "Allow booting SMP kernel on uniprocessor systems"
1360 depends on SMP && !XIP_KERNEL && MMU
1363 SMP kernels contain instructions which fail on non-SMP processors.
1364 Enabling this option allows the kernel to modify itself to make
1365 these instructions safe. Disabling it allows about 1K of space
1368 If you don't know what to do here, say Y.
1370 config ARM_CPU_TOPOLOGY
1371 bool "Support cpu topology definition"
1372 depends on SMP && CPU_V7
1375 Support ARM cpu topology definition. The MPIDR register defines
1376 affinity between processors which is then used to describe the cpu
1377 topology of an ARM System.
1380 bool "Multi-core scheduler support"
1381 depends on ARM_CPU_TOPOLOGY
1383 Multi-core scheduler support improves the CPU scheduler's decision
1384 making when dealing with multi-core CPU chips at a cost of slightly
1385 increased overhead in some places. If unsure say N here.
1388 bool "SMT scheduler support"
1389 depends on ARM_CPU_TOPOLOGY
1391 Improves the CPU scheduler's decision making when dealing with
1392 MultiThreading at a cost of slightly increased overhead in some
1393 places. If unsure say N here.
1398 This option enables support for the ARM system coherency unit
1400 config HAVE_ARM_ARCH_TIMER
1401 bool "Architected timer support"
1403 select ARM_ARCH_TIMER
1404 select GENERIC_CLOCKEVENTS
1406 This option enables support for the ARM architected timer
1410 select CLKSRC_OF if OF
1412 This options enables support for the ARM timer and watchdog unit
1415 bool "Multi-Cluster Power Management"
1416 depends on CPU_V7 && SMP
1418 This option provides the common power management infrastructure
1419 for (multi-)cluster based systems, such as big.LITTLE based
1422 config MCPM_QUAD_CLUSTER
1426 To avoid wasting resources unnecessarily, MCPM only supports up
1427 to 2 clusters by default.
1428 Platforms with 3 or 4 clusters that use MCPM must select this
1429 option to allow the additional clusters to be managed.
1432 bool "big.LITTLE support (Experimental)"
1433 depends on CPU_V7 && SMP
1436 This option enables support selections for the big.LITTLE
1437 system architecture.
1440 bool "big.LITTLE switcher support"
1441 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1442 select ARM_CPU_SUSPEND
1445 The big.LITTLE "switcher" provides the core functionality to
1446 transparently handle transition between a cluster of A15's
1447 and a cluster of A7's in a big.LITTLE system.
1449 config BL_SWITCHER_DUMMY_IF
1450 tristate "Simple big.LITTLE switcher user interface"
1451 depends on BL_SWITCHER && DEBUG_KERNEL
1453 This is a simple and dummy char dev interface to control
1454 the big.LITTLE switcher core code. It is meant for
1455 debugging purposes only.
1458 prompt "Memory split"
1462 Select the desired split between kernel and user memory.
1464 If you are not absolutely sure what you are doing, leave this
1468 bool "3G/1G user/kernel split"
1469 config VMSPLIT_3G_OPT
1470 bool "3G/1G user/kernel split (for full 1G low memory)"
1472 bool "2G/2G user/kernel split"
1474 bool "1G/3G user/kernel split"
1479 default PHYS_OFFSET if !MMU
1480 default 0x40000000 if VMSPLIT_1G
1481 default 0x80000000 if VMSPLIT_2G
1482 default 0xB0000000 if VMSPLIT_3G_OPT
1486 int "Maximum number of CPUs (2-32)"
1492 bool "Support for hot-pluggable CPUs"
1495 Say Y here to experiment with turning CPUs off and on. CPUs
1496 can be controlled through /sys/devices/system/cpu.
1499 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1500 depends on HAVE_ARM_SMCCC
1503 Say Y here if you want Linux to communicate with system firmware
1504 implementing the PSCI specification for CPU-centric power
1505 management operations described in ARM document number ARM DEN
1506 0022A ("Power State Coordination Interface System Software on
1509 # The GPIO number here must be sorted by descending number. In case of
1510 # a multiplatform kernel, we just want the highest value required by the
1511 # selected platforms.
1514 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1516 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1517 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1518 default 416 if ARCH_SUNXI
1519 default 392 if ARCH_U8500
1520 default 352 if ARCH_VT8500
1521 default 288 if ARCH_ROCKCHIP
1522 default 264 if MACH_H4700
1525 Maximum number of GPIOs in the system.
1527 If unsure, leave the default value.
1529 source kernel/Kconfig.preempt
1533 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1534 ARCH_S5PV210 || ARCH_EXYNOS4
1535 default 128 if SOC_AT91RM9200
1539 depends on HZ_FIXED = 0
1540 prompt "Timer frequency"
1564 default HZ_FIXED if HZ_FIXED != 0
1565 default 100 if HZ_100
1566 default 200 if HZ_200
1567 default 250 if HZ_250
1568 default 300 if HZ_300
1569 default 500 if HZ_500
1573 def_bool HIGH_RES_TIMERS
1575 config THUMB2_KERNEL
1576 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1577 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1578 default y if CPU_THUMBONLY
1580 select ARM_ASM_UNIFIED
1583 By enabling this option, the kernel will be compiled in
1584 Thumb-2 mode. A compiler/assembler that understand the unified
1585 ARM-Thumb syntax is needed.
1589 config THUMB2_AVOID_R_ARM_THM_JUMP11
1590 bool "Work around buggy Thumb-2 short branch relocations in gas"
1591 depends on THUMB2_KERNEL && MODULES
1594 Various binutils versions can resolve Thumb-2 branches to
1595 locally-defined, preemptible global symbols as short-range "b.n"
1596 branch instructions.
1598 This is a problem, because there's no guarantee the final
1599 destination of the symbol, or any candidate locations for a
1600 trampoline, are within range of the branch. For this reason, the
1601 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1602 relocation in modules at all, and it makes little sense to add
1605 The symptom is that the kernel fails with an "unsupported
1606 relocation" error when loading some modules.
1608 Until fixed tools are available, passing
1609 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1610 code which hits this problem, at the cost of a bit of extra runtime
1611 stack usage in some cases.
1613 The problem is described in more detail at:
1614 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1616 Only Thumb-2 kernels are affected.
1618 Unless you are sure your tools don't have this problem, say Y.
1620 config ARM_ASM_UNIFIED
1623 config ARM_PATCH_IDIV
1624 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1625 depends on CPU_32v7 && !XIP_KERNEL
1628 The ARM compiler inserts calls to __aeabi_idiv() and
1629 __aeabi_uidiv() when it needs to perform division on signed
1630 and unsigned integers. Some v7 CPUs have support for the sdiv
1631 and udiv instructions that can be used to implement those
1634 Enabling this option allows the kernel to modify itself to
1635 replace the first two instructions of these library functions
1636 with the sdiv or udiv plus "bx lr" instructions when the CPU
1637 it is running on supports them. Typically this will be faster
1638 and less power intensive than running the original library
1639 code to do integer division.
1642 bool "Use the ARM EABI to compile the kernel"
1644 This option allows for the kernel to be compiled using the latest
1645 ARM ABI (aka EABI). This is only useful if you are using a user
1646 space environment that is also compiled with EABI.
1648 Since there are major incompatibilities between the legacy ABI and
1649 EABI, especially with regard to structure member alignment, this
1650 option also changes the kernel syscall calling convention to
1651 disambiguate both ABIs and allow for backward compatibility support
1652 (selected with CONFIG_OABI_COMPAT).
1654 To use this you need GCC version 4.0.0 or later.
1657 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1658 depends on AEABI && !THUMB2_KERNEL
1660 This option preserves the old syscall interface along with the
1661 new (ARM EABI) one. It also provides a compatibility layer to
1662 intercept syscalls that have structure arguments which layout
1663 in memory differs between the legacy ABI and the new ARM EABI
1664 (only for non "thumb" binaries). This option adds a tiny
1665 overhead to all syscalls and produces a slightly larger kernel.
1667 The seccomp filter system will not be available when this is
1668 selected, since there is no way yet to sensibly distinguish
1669 between calling conventions during filtering.
1671 If you know you'll be using only pure EABI user space then you
1672 can say N here. If this option is not selected and you attempt
1673 to execute a legacy ABI binary then the result will be
1674 UNPREDICTABLE (in fact it can be predicted that it won't work
1675 at all). If in doubt say N.
1677 config ARCH_HAS_HOLES_MEMORYMODEL
1680 config ARCH_SPARSEMEM_ENABLE
1683 config ARCH_SPARSEMEM_DEFAULT
1684 def_bool ARCH_SPARSEMEM_ENABLE
1686 config ARCH_SELECT_MEMORY_MODEL
1687 def_bool ARCH_SPARSEMEM_ENABLE
1689 config HAVE_ARCH_PFN_VALID
1690 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1692 config HAVE_GENERIC_RCU_GUP
1697 bool "High Memory Support"
1700 The address space of ARM processors is only 4 Gigabytes large
1701 and it has to accommodate user address space, kernel address
1702 space as well as some memory mapped IO. That means that, if you
1703 have a large amount of physical memory and/or IO, not all of the
1704 memory can be "permanently mapped" by the kernel. The physical
1705 memory that is not permanently mapped is called "high memory".
1707 Depending on the selected kernel/user memory split, minimum
1708 vmalloc space and actual amount of RAM, you may not need this
1709 option which should result in a slightly faster kernel.
1714 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1718 The VM uses one page of physical memory for each page table.
1719 For systems with a lot of processes, this can use a lot of
1720 precious low memory, eventually leading to low memory being
1721 consumed by page tables. Setting this option will allow
1722 user-space 2nd level page tables to reside in high memory.
1724 config CPU_SW_DOMAIN_PAN
1725 bool "Enable use of CPU domains to implement privileged no-access"
1726 depends on MMU && !ARM_LPAE
1729 Increase kernel security by ensuring that normal kernel accesses
1730 are unable to access userspace addresses. This can help prevent
1731 use-after-free bugs becoming an exploitable privilege escalation
1732 by ensuring that magic values (such as LIST_POISON) will always
1733 fault when dereferenced.
1735 CPUs with low-vector mappings use a best-efforts implementation.
1736 Their lower 1MB needs to remain accessible for the vectors, but
1737 the remainder of userspace will become appropriately inaccessible.
1739 config HW_PERF_EVENTS
1743 config SYS_SUPPORTS_HUGETLBFS
1747 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1751 config ARCH_WANT_GENERAL_HUGETLB
1754 config ARM_MODULE_PLTS
1755 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1758 Allocate PLTs when loading modules so that jumps and calls whose
1759 targets are too far away for their relative offsets to be encoded
1760 in the instructions themselves can be bounced via veneers in the
1761 module's PLT. This allows modules to be allocated in the generic
1762 vmalloc area after the dedicated module memory area has been
1763 exhausted. The modules will use slightly more memory, but after
1764 rounding up to page size, the actual memory footprint is usually
1767 Say y if you are getting out of memory errors while loading modules
1771 config FORCE_MAX_ZONEORDER
1772 int "Maximum zone order"
1773 default "12" if SOC_AM33XX
1774 default "9" if SA1111 || ARCH_EFM32
1777 The kernel memory allocator divides physically contiguous memory
1778 blocks into "zones", where each zone is a power of two number of
1779 pages. This option selects the largest power of two that the kernel
1780 keeps in the memory allocator. If you need to allocate very large
1781 blocks of physically contiguous memory, then you may need to
1782 increase this value.
1784 This config option is actually maximum order plus one. For example,
1785 a value of 11 means that the largest free memory block is 2^10 pages.
1787 config ALIGNMENT_TRAP
1789 depends on CPU_CP15_MMU
1790 default y if !ARCH_EBSA110
1791 select HAVE_PROC_CPU if PROC_FS
1793 ARM processors cannot fetch/store information which is not
1794 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1795 address divisible by 4. On 32-bit ARM processors, these non-aligned
1796 fetch/store instructions will be emulated in software if you say
1797 here, which has a severe performance impact. This is necessary for
1798 correct operation of some network protocols. With an IP-only
1799 configuration it is safe to say N, otherwise say Y.
1801 config UACCESS_WITH_MEMCPY
1802 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1804 default y if CPU_FEROCEON
1806 Implement faster copy_to_user and clear_user methods for CPU
1807 cores where a 8-word STM instruction give significantly higher
1808 memory write throughput than a sequence of individual 32bit stores.
1810 A possible side effect is a slight increase in scheduling latency
1811 between threads sharing the same address space if they invoke
1812 such copy operations with large buffers.
1814 However, if the CPU data cache is using a write-allocate mode,
1815 this option is unlikely to provide any performance gain.
1819 prompt "Enable seccomp to safely compute untrusted bytecode"
1821 This kernel feature is useful for number crunching applications
1822 that may need to compute untrusted bytecode during their
1823 execution. By using pipes or other transports made available to
1824 the process as file descriptors supporting the read/write
1825 syscalls, it's possible to isolate those applications in
1826 their own address space using seccomp. Once seccomp is
1827 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1828 and the task is only allowed to execute a few safe syscalls
1829 defined by each seccomp mode.
1838 bool "Enable paravirtualization code"
1840 This changes the kernel so it can modify itself when it is run
1841 under a hypervisor, potentially improving performance significantly
1842 over full virtualization.
1844 config PARAVIRT_TIME_ACCOUNTING
1845 bool "Paravirtual steal time accounting"
1849 Select this option to enable fine granularity task steal time
1850 accounting. Time spent executing other tasks in parallel with
1851 the current vCPU is discounted from the vCPU power. To account for
1852 that, there can be a small performance impact.
1854 If in doubt, say N here.
1861 bool "Xen guest support on ARM"
1862 depends on ARM && AEABI && OF
1863 depends on CPU_V7 && !CPU_V6
1864 depends on !GENERIC_ATOMIC64
1866 select ARCH_DMA_ADDR_T_64BIT
1871 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1878 bool "Flattened Device Tree support"
1882 Include support for flattened device tree machine descriptions.
1885 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1888 This is the traditional way of passing data to the kernel at boot
1889 time. If you are solely relying on the flattened device tree (or
1890 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1891 to remove ATAGS support from your kernel binary. If unsure,
1894 config DEPRECATED_PARAM_STRUCT
1895 bool "Provide old way to pass kernel parameters"
1898 This was deprecated in 2001 and announced to live on for 5 years.
1899 Some old boot loaders still use this way.
1901 # Compressed boot loader in ROM. Yes, we really want to ask about
1902 # TEXT and BSS so we preserve their values in the config files.
1903 config ZBOOT_ROM_TEXT
1904 hex "Compressed ROM boot loader base address"
1907 The physical address at which the ROM-able zImage is to be
1908 placed in the target. Platforms which normally make use of
1909 ROM-able zImage formats normally set this to a suitable
1910 value in their defconfig file.
1912 If ZBOOT_ROM is not enabled, this has no effect.
1914 config ZBOOT_ROM_BSS
1915 hex "Compressed ROM boot loader BSS address"
1918 The base address of an area of read/write memory in the target
1919 for the ROM-able zImage which must be available while the
1920 decompressor is running. It must be large enough to hold the
1921 entire decompressed kernel plus an additional 128 KiB.
1922 Platforms which normally make use of ROM-able zImage formats
1923 normally set this to a suitable value in their defconfig file.
1925 If ZBOOT_ROM is not enabled, this has no effect.
1928 bool "Compressed boot loader in ROM/flash"
1929 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1930 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1932 Say Y here if you intend to execute your compressed kernel image
1933 (zImage) directly from ROM or flash. If unsure, say N.
1935 config ARM_APPENDED_DTB
1936 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1939 With this option, the boot code will look for a device tree binary
1940 (DTB) appended to zImage
1941 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1943 This is meant as a backward compatibility convenience for those
1944 systems with a bootloader that can't be upgraded to accommodate
1945 the documented boot protocol using a device tree.
1947 Beware that there is very little in terms of protection against
1948 this option being confused by leftover garbage in memory that might
1949 look like a DTB header after a reboot if no actual DTB is appended
1950 to zImage. Do not leave this option active in a production kernel
1951 if you don't intend to always append a DTB. Proper passing of the
1952 location into r2 of a bootloader provided DTB is always preferable
1955 config ARM_ATAG_DTB_COMPAT
1956 bool "Supplement the appended DTB with traditional ATAG information"
1957 depends on ARM_APPENDED_DTB
1959 Some old bootloaders can't be updated to a DTB capable one, yet
1960 they provide ATAGs with memory configuration, the ramdisk address,
1961 the kernel cmdline string, etc. Such information is dynamically
1962 provided by the bootloader and can't always be stored in a static
1963 DTB. To allow a device tree enabled kernel to be used with such
1964 bootloaders, this option allows zImage to extract the information
1965 from the ATAG list and store it at run time into the appended DTB.
1968 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1969 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1971 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1972 bool "Use bootloader kernel arguments if available"
1974 Uses the command-line options passed by the boot loader instead of
1975 the device tree bootargs property. If the boot loader doesn't provide
1976 any, the device tree bootargs property will be used.
1978 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1979 bool "Extend with bootloader kernel arguments"
1981 The command-line arguments provided by the boot loader will be
1982 appended to the the device tree bootargs property.
1987 string "Default kernel command string"
1990 On some architectures (EBSA110 and CATS), there is currently no way
1991 for the boot loader to pass arguments to the kernel. For these
1992 architectures, you should supply some command-line options at build
1993 time by entering them here. As a minimum, you should specify the
1994 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1997 prompt "Kernel command line type" if CMDLINE != ""
1998 default CMDLINE_FROM_BOOTLOADER
2001 config CMDLINE_FROM_BOOTLOADER
2002 bool "Use bootloader kernel arguments if available"
2004 Uses the command-line options passed by the boot loader. If
2005 the boot loader doesn't provide any, the default kernel command
2006 string provided in CMDLINE will be used.
2008 config CMDLINE_EXTEND
2009 bool "Extend bootloader kernel arguments"
2011 The command-line arguments provided by the boot loader will be
2012 appended to the default kernel command string.
2014 config CMDLINE_FORCE
2015 bool "Always use the default kernel command string"
2017 Always use the default kernel command string, even if the boot
2018 loader passes other arguments to the kernel.
2019 This is useful if you cannot or don't want to change the
2020 command-line options your boot loader passes to the kernel.
2024 bool "Kernel Execute-In-Place from ROM"
2025 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2027 Execute-In-Place allows the kernel to run from non-volatile storage
2028 directly addressable by the CPU, such as NOR flash. This saves RAM
2029 space since the text section of the kernel is not loaded from flash
2030 to RAM. Read-write sections, such as the data section and stack,
2031 are still copied to RAM. The XIP kernel is not compressed since
2032 it has to run directly from flash, so it will take more space to
2033 store it. The flash address used to link the kernel object files,
2034 and for storing it, is configuration dependent. Therefore, if you
2035 say Y here, you must know the proper physical address where to
2036 store the kernel image depending on your own flash memory usage.
2038 Also note that the make target becomes "make xipImage" rather than
2039 "make zImage" or "make Image". The final kernel binary to put in
2040 ROM memory will be arch/arm/boot/xipImage.
2044 config XIP_PHYS_ADDR
2045 hex "XIP Kernel Physical Location"
2046 depends on XIP_KERNEL
2047 default "0x00080000"
2049 This is the physical address in your flash memory the kernel will
2050 be linked for and stored to. This address is dependent on your
2054 bool "Kexec system call (EXPERIMENTAL)"
2055 depends on (!SMP || PM_SLEEP_SMP)
2059 kexec is a system call that implements the ability to shutdown your
2060 current kernel, and to start another kernel. It is like a reboot
2061 but it is independent of the system firmware. And like a reboot
2062 you can start any kernel with it, not just Linux.
2064 It is an ongoing process to be certain the hardware in a machine
2065 is properly shutdown, so do not be surprised if this code does not
2066 initially work for you.
2069 bool "Export atags in procfs"
2070 depends on ATAGS && KEXEC
2073 Should the atags used to boot the kernel be exported in an "atags"
2074 file in procfs. Useful with kexec.
2077 bool "Build kdump crash kernel (EXPERIMENTAL)"
2079 Generate crash dump after being started by kexec. This should
2080 be normally only set in special crash dump kernels which are
2081 loaded in the main kernel with kexec-tools into a specially
2082 reserved region and then later executed after a crash by
2083 kdump/kexec. The crash dump kernel must be compiled to a
2084 memory address not used by the main kernel
2086 For more details see Documentation/kdump/kdump.txt
2088 config AUTO_ZRELADDR
2089 bool "Auto calculation of the decompressed kernel image address"
2091 ZRELADDR is the physical address where the decompressed kernel
2092 image will be placed. If AUTO_ZRELADDR is selected, the address
2093 will be determined at run-time by masking the current IP with
2094 0xf8000000. This assumes the zImage being placed in the first 128MB
2095 from start of memory.
2101 bool "UEFI runtime support"
2102 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2104 select EFI_PARAMS_FROM_FDT
2107 select EFI_RUNTIME_WRAPPERS
2109 This option provides support for runtime services provided
2110 by UEFI firmware (such as non-volatile variables, realtime
2111 clock, and platform reset). A UEFI stub is also provided to
2112 allow the kernel to be booted as an EFI application. This
2113 is only useful for kernels that may run on systems that have
2118 menu "CPU Power Management"
2120 source "drivers/cpufreq/Kconfig"
2122 source "drivers/cpuidle/Kconfig"
2126 menu "Floating point emulation"
2128 comment "At least one emulation must be selected"
2131 bool "NWFPE math emulation"
2132 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2134 Say Y to include the NWFPE floating point emulator in the kernel.
2135 This is necessary to run most binaries. Linux does not currently
2136 support floating point hardware so you need to say Y here even if
2137 your machine has an FPA or floating point co-processor podule.
2139 You may say N here if you are going to load the Acorn FPEmulator
2140 early in the bootup.
2143 bool "Support extended precision"
2144 depends on FPE_NWFPE
2146 Say Y to include 80-bit support in the kernel floating-point
2147 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2148 Note that gcc does not generate 80-bit operations by default,
2149 so in most cases this option only enlarges the size of the
2150 floating point emulator without any good reason.
2152 You almost surely want to say N here.
2155 bool "FastFPE math emulation (EXPERIMENTAL)"
2156 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2158 Say Y here to include the FAST floating point emulator in the kernel.
2159 This is an experimental much faster emulator which now also has full
2160 precision for the mantissa. It does not support any exceptions.
2161 It is very simple, and approximately 3-6 times faster than NWFPE.
2163 It should be sufficient for most programs. It may be not suitable
2164 for scientific calculations, but you have to check this for yourself.
2165 If you do not feel you need a faster FP emulation you should better
2169 bool "VFP-format floating point maths"
2170 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2172 Say Y to include VFP support code in the kernel. This is needed
2173 if your hardware includes a VFP unit.
2175 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2176 release notes and additional status information.
2178 Say N if your target does not have VFP hardware.
2186 bool "Advanced SIMD (NEON) Extension support"
2187 depends on VFPv3 && CPU_V7
2189 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2192 config KERNEL_MODE_NEON
2193 bool "Support for NEON in kernel mode"
2194 depends on NEON && AEABI
2196 Say Y to include support for NEON in kernel mode.
2200 menu "Userspace binary formats"
2202 source "fs/Kconfig.binfmt"
2206 menu "Power management options"
2208 source "kernel/power/Kconfig"
2210 config ARCH_SUSPEND_POSSIBLE
2211 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2212 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2215 config ARM_CPU_SUSPEND
2218 config ARCH_HIBERNATION_POSSIBLE
2221 default y if ARCH_SUSPEND_POSSIBLE
2225 source "net/Kconfig"
2227 source "drivers/Kconfig"
2229 source "drivers/firmware/Kconfig"
2233 source "arch/arm/Kconfig.debug"
2235 source "security/Kconfig"
2237 source "crypto/Kconfig"
2239 source "arch/arm/crypto/Kconfig"
2242 source "lib/Kconfig"
2244 source "arch/arm/kvm/Kconfig"