4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
256 select ARCH_HAS_CPUFREQ
258 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_CLOCK
264 select PLAT_VERSATILE_FPGA_IRQ
265 select NEED_MACH_IO_H
266 select NEED_MACH_MEMORY_H
268 select MULTI_IRQ_HANDLER
270 Support for ARM's Integrator platform.
273 bool "ARM Ltd. RealView family"
276 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLOCK
282 select PLAT_VERSATILE_CLCD
283 select ARM_TIMER_SP804
284 select GPIO_PL061 if GPIOLIB
285 select NEED_MACH_MEMORY_H
287 This enables support for ARM Ltd RealView boards.
289 config ARCH_VERSATILE
290 bool "ARM Ltd. Versatile family"
294 select HAVE_MACH_CLKDEV
296 select GENERIC_CLOCKEVENTS
297 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select NEED_MACH_IO_H if PCI
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
301 select PLAT_VERSATILE_CLCD
302 select PLAT_VERSATILE_FPGA_IRQ
303 select ARM_TIMER_SP804
305 This enables support for ARM Ltd Versatile board.
308 bool "ARM Ltd. Versatile Express family"
309 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_TIMER_SP804
314 select GENERIC_CLOCKEVENTS
316 select HAVE_PATA_PLATFORM
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select REGULATOR_FIXED_VOLTAGE if REGULATOR
323 This enables support for the ARM Ltd Versatile Express boards.
327 select ARCH_REQUIRE_GPIOLIB
331 select NEED_MACH_IO_H if PCCARD
333 This enables support for systems based on Atmel
334 AT91RM9200 and AT91SAM9* processors.
337 bool "Broadcom BCMRING"
341 select ARM_TIMER_SP804
343 select GENERIC_CLOCKEVENTS
344 select ARCH_WANT_OPTIONAL_GPIOLIB
346 Support for Broadcom's BCMRing platform.
349 bool "Calxeda Highbank-based"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
353 select ARM_TIMER_SP804
357 select GENERIC_CLOCKEVENTS
363 Support for the Calxeda Highbank SoC based boards.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
368 select ARCH_USES_GETTIMEOFFSET
369 select NEED_MACH_MEMORY_H
371 Support for Cirrus Logic 711x/721x/731x based boards.
374 bool "Cavium Networks CNS3XXX family"
376 select GENERIC_CLOCKEVENTS
378 select MIGHT_HAVE_CACHE_L2X0
379 select MIGHT_HAVE_PCI
380 select PCI_DOMAINS if PCI
382 Support for Cavium Networks CNS3XXX platform.
385 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
390 Support for the Cortina Systems Gemini family SoCs
393 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
396 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
405 Support for CSR SiRFSoC ARM Cortex A9 Platform
412 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
427 select ARCH_REQUIRE_GPIOLIB
428 select ARCH_HAS_HOLES_MEMORYMODEL
429 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Freescale MXC/iMX-based"
448 select GENERIC_CLOCKEVENTS
449 select ARCH_REQUIRE_GPIOLIB
452 select GENERIC_IRQ_CHIP
453 select MULTI_IRQ_HANDLER
455 Support for Freescale MXC/iMX-based family of processors
458 bool "Freescale MXS-based"
459 select GENERIC_CLOCKEVENTS
460 select ARCH_REQUIRE_GPIOLIB
464 select HAVE_CLK_PREPARE
468 Support for Freescale MXS-based family of processors
471 bool "Hilscher NetX based"
475 select GENERIC_CLOCKEVENTS
477 This enables support for systems based on the Hilscher NetX Soc
480 bool "Hynix HMS720x-based"
483 select ARCH_USES_GETTIMEOFFSET
485 This enables support for systems based on the Hynix HMS720x
493 select ARCH_SUPPORTS_MSI
495 select NEED_MACH_IO_H
496 select NEED_MACH_MEMORY_H
497 select NEED_RET_TO_USER
499 Support for Intel's IOP13XX (XScale) family of processors.
505 select NEED_MACH_IO_H
506 select NEED_RET_TO_USER
509 select ARCH_REQUIRE_GPIOLIB
511 Support for Intel's 80219 and IOP32X (XScale) family of
518 select NEED_MACH_IO_H
519 select NEED_RET_TO_USER
522 select ARCH_REQUIRE_GPIOLIB
524 Support for Intel's IOP33X (XScale) family of processors.
529 select ARCH_HAS_DMA_SET_COHERENT_MASK
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
535 select NEED_MACH_IO_H
536 select DMABOUNCE if PCI
538 Support for Intel's IXP4XX (XScale) family of processors.
544 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select NEED_MACH_IO_H
549 Support for the Marvell Dove SoC 88AP510
552 bool "Marvell Kirkwood"
555 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
557 select NEED_MACH_IO_H
560 Support for the following Marvell Kirkwood series SoCs:
561 88F6180, 88F6192 and 88F6281.
567 select ARCH_REQUIRE_GPIOLIB
570 select USB_ARCH_HAS_OHCI
572 select GENERIC_CLOCKEVENTS
576 Support for the NXP LPC32XX family of processors
579 bool "Marvell MV78xx0"
582 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
584 select NEED_MACH_IO_H
587 Support for the following Marvell MV78xx0 series SoCs:
595 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
597 select NEED_MACH_IO_H
600 Support for the following Marvell Orion 5x series SoCs:
601 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
602 Orion-2 (5281), Orion-1-90 (6183).
605 bool "Marvell PXA168/910/MMP2"
607 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
614 select GENERIC_ALLOCATOR
616 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
619 bool "Micrel/Kendin KS8695"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARCH_USES_GETTIMEOFFSET
623 select NEED_MACH_MEMORY_H
625 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
626 System-on-Chip devices.
629 bool "Nuvoton W90X900 CPU"
631 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
636 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
637 At present, the w90x900 has been renamed nuc900, regarding
638 the ARM series product line, you can login the following
639 link address to know more.
641 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
642 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
648 select GENERIC_CLOCKEVENTS
652 select MIGHT_HAVE_CACHE_L2X0
653 select NEED_MACH_IO_H if PCI
654 select ARCH_HAS_CPUFREQ
656 This enables support for NVIDIA Tegra based systems (Tegra APX,
657 Tegra 6xx and Tegra 2 series).
659 config ARCH_PICOXCELL
660 bool "Picochip picoXcell"
661 select ARCH_REQUIRE_GPIOLIB
662 select ARM_PATCH_PHYS_VIRT
666 select GENERIC_CLOCKEVENTS
673 This enables support for systems based on the Picochip picoXcell
674 family of Femtocell devices. The picoxcell support requires device tree
678 bool "Philips Nexperia PNX4008 Mobile"
681 select ARCH_USES_GETTIMEOFFSET
683 This enables support for Philips PNX4008 mobile platform.
686 bool "PXA2xx/PXA3xx-based"
689 select ARCH_HAS_CPUFREQ
692 select ARCH_REQUIRE_GPIOLIB
693 select GENERIC_CLOCKEVENTS
698 select MULTI_IRQ_HANDLER
699 select ARM_CPU_SUSPEND if PM
702 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
707 select GENERIC_CLOCKEVENTS
708 select ARCH_REQUIRE_GPIOLIB
711 Support for Qualcomm MSM/QSD based systems. This runs on the
712 apps processor of the MSM/QSD and depends on a shared memory
713 interface to the modem processor which runs the baseband
714 stack and controls some vital subsystems
715 (clock and power control, etc).
718 bool "Renesas SH-Mobile / R-Mobile"
721 select HAVE_MACH_CLKDEV
723 select GENERIC_CLOCKEVENTS
724 select MIGHT_HAVE_CACHE_L2X0
727 select MULTI_IRQ_HANDLER
728 select PM_GENERIC_DOMAINS if PM
729 select NEED_MACH_MEMORY_H
731 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
737 select ARCH_MAY_HAVE_PC_FDC
738 select HAVE_PATA_PLATFORM
741 select ARCH_SPARSEMEM_ENABLE
742 select ARCH_USES_GETTIMEOFFSET
744 select NEED_MACH_IO_H
745 select NEED_MACH_MEMORY_H
747 On the Acorn Risc-PC, Linux can support the internal IDE disk and
748 CD-ROM interface, serial and parallel port, and the floppy drive.
755 select ARCH_SPARSEMEM_ENABLE
757 select ARCH_HAS_CPUFREQ
759 select GENERIC_CLOCKEVENTS
761 select ARCH_REQUIRE_GPIOLIB
763 select NEED_MACH_MEMORY_H
766 Support for StrongARM 11x0 based boards.
769 bool "Samsung S3C24XX SoCs"
771 select ARCH_HAS_CPUFREQ
774 select ARCH_USES_GETTIMEOFFSET
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C_RTC if RTC_CLASS
777 select HAVE_S3C2410_WATCHDOG if WATCHDOG
778 select NEED_MACH_IO_H
780 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
781 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
782 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
783 Samsung SMDK2410 development board (and derivatives).
786 bool "Samsung S3C64XX"
794 select ARCH_USES_GETTIMEOFFSET
795 select ARCH_HAS_CPUFREQ
796 select ARCH_REQUIRE_GPIOLIB
797 select SAMSUNG_CLKSRC
798 select SAMSUNG_IRQ_VIC_TIMER
799 select S3C_GPIO_TRACK
801 select USB_ARCH_HAS_OHCI
802 select SAMSUNG_GPIOLIB_4BIT
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 Samsung S3C64XX series based systems
809 bool "Samsung S5P6440 S5P6450"
815 select HAVE_S3C2410_WATCHDOG if WATCHDOG
816 select GENERIC_CLOCKEVENTS
817 select HAVE_S3C2410_I2C if I2C
818 select HAVE_S3C_RTC if RTC_CLASS
820 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
824 bool "Samsung S5PC100"
829 select ARCH_USES_GETTIMEOFFSET
830 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C_RTC if RTC_CLASS
832 select HAVE_S3C2410_WATCHDOG if WATCHDOG
834 Samsung S5PC100 series based systems
837 bool "Samsung S5PV210/S5PC110"
839 select ARCH_SPARSEMEM_ENABLE
840 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARCH_HAS_CPUFREQ
846 select GENERIC_CLOCKEVENTS
847 select HAVE_S3C2410_I2C if I2C
848 select HAVE_S3C_RTC if RTC_CLASS
849 select HAVE_S3C2410_WATCHDOG if WATCHDOG
850 select NEED_MACH_MEMORY_H
852 Samsung S5PV210/S5PC110 series based systems
855 bool "SAMSUNG EXYNOS"
857 select ARCH_SPARSEMEM_ENABLE
858 select ARCH_HAS_HOLES_MEMORYMODEL
862 select ARCH_HAS_CPUFREQ
863 select GENERIC_CLOCKEVENTS
864 select HAVE_S3C_RTC if RTC_CLASS
865 select HAVE_S3C2410_I2C if I2C
866 select HAVE_S3C2410_WATCHDOG if WATCHDOG
867 select NEED_MACH_MEMORY_H
869 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
878 select ARCH_USES_GETTIMEOFFSET
879 select NEED_MACH_MEMORY_H
880 select NEED_MACH_IO_H
882 Support for the StrongARM based Digital DNARD machine, also known
883 as "Shark" (<http://www.shark-linux.de/shark.html>).
886 bool "ST-Ericsson U300 Series"
892 select ARM_PATCH_PHYS_VIRT
894 select GENERIC_CLOCKEVENTS
896 select HAVE_MACH_CLKDEV
898 select ARCH_REQUIRE_GPIOLIB
900 Support for ST-Ericsson U300 series mobile platforms.
903 bool "ST-Ericsson U8500 Series"
907 select GENERIC_CLOCKEVENTS
909 select ARCH_REQUIRE_GPIOLIB
910 select ARCH_HAS_CPUFREQ
912 select MIGHT_HAVE_CACHE_L2X0
914 Support for ST-Ericsson's Ux500 architecture
917 bool "STMicroelectronics Nomadik"
922 select GENERIC_CLOCKEVENTS
924 select MIGHT_HAVE_CACHE_L2X0
925 select ARCH_REQUIRE_GPIOLIB
927 Support for the Nomadik platform by ST-Ericsson
931 select GENERIC_CLOCKEVENTS
932 select ARCH_REQUIRE_GPIOLIB
936 select GENERIC_ALLOCATOR
937 select GENERIC_IRQ_CHIP
938 select ARCH_HAS_HOLES_MEMORYMODEL
940 Support for TI's DaVinci platform.
946 select ARCH_REQUIRE_GPIOLIB
947 select ARCH_HAS_CPUFREQ
949 select GENERIC_CLOCKEVENTS
950 select ARCH_HAS_HOLES_MEMORYMODEL
952 Support for TI's OMAP platform (OMAP1/2/3/4).
957 select ARCH_REQUIRE_GPIOLIB
961 select GENERIC_CLOCKEVENTS
964 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
967 bool "VIA/WonderMedia 85xx"
970 select ARCH_HAS_CPUFREQ
971 select GENERIC_CLOCKEVENTS
972 select ARCH_REQUIRE_GPIOLIB
975 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
978 bool "Xilinx Zynq ARM Cortex A9 Platform"
980 select GENERIC_CLOCKEVENTS
985 select MIGHT_HAVE_CACHE_L2X0
988 Support for Xilinx Zynq ARM Cortex A9 Platform
992 # This is sorted alphabetically by mach-* pathname. However, plat-*
993 # Kconfigs may be included either alphabetically (according to the
994 # plat- suffix) or along side the corresponding mach-* source.
996 source "arch/arm/mach-at91/Kconfig"
998 source "arch/arm/mach-bcmring/Kconfig"
1000 source "arch/arm/mach-clps711x/Kconfig"
1002 source "arch/arm/mach-cns3xxx/Kconfig"
1004 source "arch/arm/mach-davinci/Kconfig"
1006 source "arch/arm/mach-dove/Kconfig"
1008 source "arch/arm/mach-ep93xx/Kconfig"
1010 source "arch/arm/mach-footbridge/Kconfig"
1012 source "arch/arm/mach-gemini/Kconfig"
1014 source "arch/arm/mach-h720x/Kconfig"
1016 source "arch/arm/mach-integrator/Kconfig"
1018 source "arch/arm/mach-iop32x/Kconfig"
1020 source "arch/arm/mach-iop33x/Kconfig"
1022 source "arch/arm/mach-iop13xx/Kconfig"
1024 source "arch/arm/mach-ixp4xx/Kconfig"
1026 source "arch/arm/mach-kirkwood/Kconfig"
1028 source "arch/arm/mach-ks8695/Kconfig"
1030 source "arch/arm/mach-msm/Kconfig"
1032 source "arch/arm/mach-mv78xx0/Kconfig"
1034 source "arch/arm/plat-mxc/Kconfig"
1036 source "arch/arm/mach-mxs/Kconfig"
1038 source "arch/arm/mach-netx/Kconfig"
1040 source "arch/arm/mach-nomadik/Kconfig"
1041 source "arch/arm/plat-nomadik/Kconfig"
1043 source "arch/arm/plat-omap/Kconfig"
1045 source "arch/arm/mach-omap1/Kconfig"
1047 source "arch/arm/mach-omap2/Kconfig"
1049 source "arch/arm/mach-orion5x/Kconfig"
1051 source "arch/arm/mach-pxa/Kconfig"
1052 source "arch/arm/plat-pxa/Kconfig"
1054 source "arch/arm/mach-mmp/Kconfig"
1056 source "arch/arm/mach-realview/Kconfig"
1058 source "arch/arm/mach-sa1100/Kconfig"
1060 source "arch/arm/plat-samsung/Kconfig"
1061 source "arch/arm/plat-s3c24xx/Kconfig"
1063 source "arch/arm/plat-spear/Kconfig"
1065 source "arch/arm/mach-s3c24xx/Kconfig"
1067 source "arch/arm/mach-s3c2412/Kconfig"
1068 source "arch/arm/mach-s3c2440/Kconfig"
1072 source "arch/arm/mach-s3c64xx/Kconfig"
1075 source "arch/arm/mach-s5p64x0/Kconfig"
1077 source "arch/arm/mach-s5pc100/Kconfig"
1079 source "arch/arm/mach-s5pv210/Kconfig"
1081 source "arch/arm/mach-exynos/Kconfig"
1083 source "arch/arm/mach-shmobile/Kconfig"
1085 source "arch/arm/mach-tegra/Kconfig"
1087 source "arch/arm/mach-u300/Kconfig"
1089 source "arch/arm/mach-ux500/Kconfig"
1091 source "arch/arm/mach-versatile/Kconfig"
1093 source "arch/arm/mach-vexpress/Kconfig"
1094 source "arch/arm/plat-versatile/Kconfig"
1096 source "arch/arm/mach-vt8500/Kconfig"
1098 source "arch/arm/mach-w90x900/Kconfig"
1100 # Definitions to make life easier
1106 select GENERIC_CLOCKEVENTS
1111 select GENERIC_IRQ_CHIP
1117 config PLAT_VERSATILE
1120 config ARM_TIMER_SP804
1123 select HAVE_SCHED_CLOCK
1125 source arch/arm/mm/Kconfig
1129 default 16 if ARCH_EP93XX
1133 bool "Enable iWMMXt support"
1134 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1135 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1137 Enable support for iWMMXt context switching at run time if
1138 running on a CPU that supports it.
1142 depends on CPU_XSCALE
1146 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1147 (!ARCH_OMAP3 || OMAP3_EMU)
1151 config MULTI_IRQ_HANDLER
1154 Allow each machine to specify it's own IRQ handler at run time.
1157 source "arch/arm/Kconfig-nommu"
1160 config ARM_ERRATA_326103
1161 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1164 Executing a SWP instruction to read-only memory does not set bit 11
1165 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1166 treat the access as a read, preventing a COW from occurring and
1167 causing the faulting task to livelock.
1169 config ARM_ERRATA_411920
1170 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1171 depends on CPU_V6 || CPU_V6K
1173 Invalidation of the Instruction Cache operation can
1174 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1175 It does not affect the MPCore. This option enables the ARM Ltd.
1176 recommended workaround.
1178 config ARM_ERRATA_430973
1179 bool "ARM errata: Stale prediction on replaced interworking branch"
1182 This option enables the workaround for the 430973 Cortex-A8
1183 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1184 interworking branch is replaced with another code sequence at the
1185 same virtual address, whether due to self-modifying code or virtual
1186 to physical address re-mapping, Cortex-A8 does not recover from the
1187 stale interworking branch prediction. This results in Cortex-A8
1188 executing the new code sequence in the incorrect ARM or Thumb state.
1189 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1190 and also flushes the branch target cache at every context switch.
1191 Note that setting specific bits in the ACTLR register may not be
1192 available in non-secure mode.
1194 config ARM_ERRATA_458693
1195 bool "ARM errata: Processor deadlock when a false hazard is created"
1198 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1199 erratum. For very specific sequences of memory operations, it is
1200 possible for a hazard condition intended for a cache line to instead
1201 be incorrectly associated with a different cache line. This false
1202 hazard might then cause a processor deadlock. The workaround enables
1203 the L1 caching of the NEON accesses and disables the PLD instruction
1204 in the ACTLR register. Note that setting specific bits in the ACTLR
1205 register may not be available in non-secure mode.
1207 config ARM_ERRATA_460075
1208 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1211 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1212 erratum. Any asynchronous access to the L2 cache may encounter a
1213 situation in which recent store transactions to the L2 cache are lost
1214 and overwritten with stale memory contents from external memory. The
1215 workaround disables the write-allocate mode for the L2 cache via the
1216 ACTLR register. Note that setting specific bits in the ACTLR register
1217 may not be available in non-secure mode.
1219 config ARM_ERRATA_742230
1220 bool "ARM errata: DMB operation may be faulty"
1221 depends on CPU_V7 && SMP
1223 This option enables the workaround for the 742230 Cortex-A9
1224 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1225 between two write operations may not ensure the correct visibility
1226 ordering of the two writes. This workaround sets a specific bit in
1227 the diagnostic register of the Cortex-A9 which causes the DMB
1228 instruction to behave as a DSB, ensuring the correct behaviour of
1231 config ARM_ERRATA_742231
1232 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1233 depends on CPU_V7 && SMP
1235 This option enables the workaround for the 742231 Cortex-A9
1236 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1237 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1238 accessing some data located in the same cache line, may get corrupted
1239 data due to bad handling of the address hazard when the line gets
1240 replaced from one of the CPUs at the same time as another CPU is
1241 accessing it. This workaround sets specific bits in the diagnostic
1242 register of the Cortex-A9 which reduces the linefill issuing
1243 capabilities of the processor.
1245 config PL310_ERRATA_588369
1246 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1247 depends on CACHE_L2X0
1249 The PL310 L2 cache controller implements three types of Clean &
1250 Invalidate maintenance operations: by Physical Address
1251 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1252 They are architecturally defined to behave as the execution of a
1253 clean operation followed immediately by an invalidate operation,
1254 both performing to the same memory location. This functionality
1255 is not correctly implemented in PL310 as clean lines are not
1256 invalidated as a result of these operations.
1258 config ARM_ERRATA_720789
1259 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1262 This option enables the workaround for the 720789 Cortex-A9 (prior to
1263 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1264 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1265 As a consequence of this erratum, some TLB entries which should be
1266 invalidated are not, resulting in an incoherency in the system page
1267 tables. The workaround changes the TLB flushing routines to invalidate
1268 entries regardless of the ASID.
1270 config PL310_ERRATA_727915
1271 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1272 depends on CACHE_L2X0
1274 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1275 operation (offset 0x7FC). This operation runs in background so that
1276 PL310 can handle normal accesses while it is in progress. Under very
1277 rare circumstances, due to this erratum, write data can be lost when
1278 PL310 treats a cacheable write transaction during a Clean &
1279 Invalidate by Way operation.
1281 config ARM_ERRATA_743622
1282 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1285 This option enables the workaround for the 743622 Cortex-A9
1286 (r2p*) erratum. Under very rare conditions, a faulty
1287 optimisation in the Cortex-A9 Store Buffer may lead to data
1288 corruption. This workaround sets a specific bit in the diagnostic
1289 register of the Cortex-A9 which disables the Store Buffer
1290 optimisation, preventing the defect from occurring. This has no
1291 visible impact on the overall performance or power consumption of the
1294 config ARM_ERRATA_751472
1295 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1298 This option enables the workaround for the 751472 Cortex-A9 (prior
1299 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1300 completion of a following broadcasted operation if the second
1301 operation is received by a CPU before the ICIALLUIS has completed,
1302 potentially leading to corrupted entries in the cache or TLB.
1304 config PL310_ERRATA_753970
1305 bool "PL310 errata: cache sync operation may be faulty"
1306 depends on CACHE_PL310
1308 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1310 Under some condition the effect of cache sync operation on
1311 the store buffer still remains when the operation completes.
1312 This means that the store buffer is always asked to drain and
1313 this prevents it from merging any further writes. The workaround
1314 is to replace the normal offset of cache sync operation (0x730)
1315 by another offset targeting an unmapped PL310 register 0x740.
1316 This has the same effect as the cache sync operation: store buffer
1317 drain and waiting for all buffers empty.
1319 config ARM_ERRATA_754322
1320 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1323 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1324 r3p*) erratum. A speculative memory access may cause a page table walk
1325 which starts prior to an ASID switch but completes afterwards. This
1326 can populate the micro-TLB with a stale entry which may be hit with
1327 the new ASID. This workaround places two dsb instructions in the mm
1328 switching code so that no page table walks can cross the ASID switch.
1330 config ARM_ERRATA_754327
1331 bool "ARM errata: no automatic Store Buffer drain"
1332 depends on CPU_V7 && SMP
1334 This option enables the workaround for the 754327 Cortex-A9 (prior to
1335 r2p0) erratum. The Store Buffer does not have any automatic draining
1336 mechanism and therefore a livelock may occur if an external agent
1337 continuously polls a memory location waiting to observe an update.
1338 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1339 written polling loops from denying visibility of updates to memory.
1341 config ARM_ERRATA_364296
1342 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1343 depends on CPU_V6 && !SMP
1345 This options enables the workaround for the 364296 ARM1136
1346 r0p2 erratum (possible cache data corruption with
1347 hit-under-miss enabled). It sets the undocumented bit 31 in
1348 the auxiliary control register and the FI bit in the control
1349 register, thus disabling hit-under-miss without putting the
1350 processor into full low interrupt latency mode. ARM11MPCore
1353 config ARM_ERRATA_764369
1354 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1355 depends on CPU_V7 && SMP
1357 This option enables the workaround for erratum 764369
1358 affecting Cortex-A9 MPCore with two or more processors (all
1359 current revisions). Under certain timing circumstances, a data
1360 cache line maintenance operation by MVA targeting an Inner
1361 Shareable memory region may fail to proceed up to either the
1362 Point of Coherency or to the Point of Unification of the
1363 system. This workaround adds a DSB instruction before the
1364 relevant cache maintenance functions and sets a specific bit
1365 in the diagnostic control register of the SCU.
1367 config PL310_ERRATA_769419
1368 bool "PL310 errata: no automatic Store Buffer drain"
1369 depends on CACHE_L2X0
1371 On revisions of the PL310 prior to r3p2, the Store Buffer does
1372 not automatically drain. This can cause normal, non-cacheable
1373 writes to be retained when the memory system is idle, leading
1374 to suboptimal I/O performance for drivers using coherent DMA.
1375 This option adds a write barrier to the cpu_idle loop so that,
1376 on systems with an outer cache, the store buffer is drained
1381 source "arch/arm/common/Kconfig"
1391 Find out whether you have ISA slots on your motherboard. ISA is the
1392 name of a bus system, i.e. the way the CPU talks to the other stuff
1393 inside your box. Other bus systems are PCI, EISA, MicroChannel
1394 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1395 newer boards don't support it. If you have ISA, say Y, otherwise N.
1397 # Select ISA DMA controller support
1402 # Select ISA DMA interface
1407 bool "PCI support" if MIGHT_HAVE_PCI
1409 Find out whether you have a PCI motherboard. PCI is the name of a
1410 bus system, i.e. the way the CPU talks to the other stuff inside
1411 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1412 VESA. If you have PCI, say Y, otherwise N.
1418 config PCI_NANOENGINE
1419 bool "BSE nanoEngine PCI support"
1420 depends on SA1100_NANOENGINE
1422 Enable PCI on the BSE nanoEngine board.
1427 # Select the host bridge type
1428 config PCI_HOST_VIA82C505
1430 depends on PCI && ARCH_SHARK
1433 config PCI_HOST_ITE8152
1435 depends on PCI && MACH_ARMCORE
1439 source "drivers/pci/Kconfig"
1441 source "drivers/pcmcia/Kconfig"
1445 menu "Kernel Features"
1450 This option should be selected by machines which have an SMP-
1453 The only effect of this option is to make the SMP-related
1454 options available to the user for configuration.
1457 bool "Symmetric Multi-Processing"
1458 depends on CPU_V6K || CPU_V7
1459 depends on GENERIC_CLOCKEVENTS
1462 select USE_GENERIC_SMP_HELPERS
1463 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1465 This enables support for systems with more than one CPU. If you have
1466 a system with only one CPU, like most personal computers, say N. If
1467 you have a system with more than one CPU, say Y.
1469 If you say N here, the kernel will run on single and multiprocessor
1470 machines, but will use only one CPU of a multiprocessor machine. If
1471 you say Y here, the kernel will run on many, but not all, single
1472 processor machines. On a single processor machine, the kernel will
1473 run faster if you say N here.
1475 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1476 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1477 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1479 If you don't know what to do here, say N.
1482 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1483 depends on EXPERIMENTAL
1484 depends on SMP && !XIP_KERNEL
1487 SMP kernels contain instructions which fail on non-SMP processors.
1488 Enabling this option allows the kernel to modify itself to make
1489 these instructions safe. Disabling it allows about 1K of space
1492 If you don't know what to do here, say Y.
1494 config ARM_CPU_TOPOLOGY
1495 bool "Support cpu topology definition"
1496 depends on SMP && CPU_V7
1499 Support ARM cpu topology definition. The MPIDR register defines
1500 affinity between processors which is then used to describe the cpu
1501 topology of an ARM System.
1504 bool "Multi-core scheduler support"
1505 depends on ARM_CPU_TOPOLOGY
1507 Multi-core scheduler support improves the CPU scheduler's decision
1508 making when dealing with multi-core CPU chips at a cost of slightly
1509 increased overhead in some places. If unsure say N here.
1512 bool "SMT scheduler support"
1513 depends on ARM_CPU_TOPOLOGY
1515 Improves the CPU scheduler's decision making when dealing with
1516 MultiThreading at a cost of slightly increased overhead in some
1517 places. If unsure say N here.
1522 This option enables support for the ARM system coherency unit
1524 config ARM_ARCH_TIMER
1525 bool "Architected timer support"
1528 This option enables support for the ARM architected timer
1534 This options enables support for the ARM timer and watchdog unit
1537 prompt "Memory split"
1540 Select the desired split between kernel and user memory.
1542 If you are not absolutely sure what you are doing, leave this
1546 bool "3G/1G user/kernel split"
1548 bool "2G/2G user/kernel split"
1550 bool "1G/3G user/kernel split"
1555 default 0x40000000 if VMSPLIT_1G
1556 default 0x80000000 if VMSPLIT_2G
1560 int "Maximum number of CPUs (2-32)"
1566 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1567 depends on SMP && HOTPLUG && EXPERIMENTAL
1569 Say Y here to experiment with turning CPUs off and on. CPUs
1570 can be controlled through /sys/devices/system/cpu.
1573 bool "Use local timer interrupts"
1576 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1578 Enable support for local timers on SMP platforms, rather then the
1579 legacy IPI broadcast method. Local timers allows the system
1580 accounting to be spread across the timer interval, preventing a
1581 "thundering herd" at every timer tick.
1585 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1586 default 355 if ARCH_U8500
1587 default 264 if MACH_H4700
1590 Maximum number of GPIOs in the system.
1592 If unsure, leave the default value.
1594 source kernel/Kconfig.preempt
1598 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1599 ARCH_S5PV210 || ARCH_EXYNOS4
1600 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1601 default AT91_TIMER_HZ if ARCH_AT91
1602 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1605 config THUMB2_KERNEL
1606 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1607 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1609 select ARM_ASM_UNIFIED
1612 By enabling this option, the kernel will be compiled in
1613 Thumb-2 mode. A compiler/assembler that understand the unified
1614 ARM-Thumb syntax is needed.
1618 config THUMB2_AVOID_R_ARM_THM_JUMP11
1619 bool "Work around buggy Thumb-2 short branch relocations in gas"
1620 depends on THUMB2_KERNEL && MODULES
1623 Various binutils versions can resolve Thumb-2 branches to
1624 locally-defined, preemptible global symbols as short-range "b.n"
1625 branch instructions.
1627 This is a problem, because there's no guarantee the final
1628 destination of the symbol, or any candidate locations for a
1629 trampoline, are within range of the branch. For this reason, the
1630 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1631 relocation in modules at all, and it makes little sense to add
1634 The symptom is that the kernel fails with an "unsupported
1635 relocation" error when loading some modules.
1637 Until fixed tools are available, passing
1638 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1639 code which hits this problem, at the cost of a bit of extra runtime
1640 stack usage in some cases.
1642 The problem is described in more detail at:
1643 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1645 Only Thumb-2 kernels are affected.
1647 Unless you are sure your tools don't have this problem, say Y.
1649 config ARM_ASM_UNIFIED
1653 bool "Use the ARM EABI to compile the kernel"
1655 This option allows for the kernel to be compiled using the latest
1656 ARM ABI (aka EABI). This is only useful if you are using a user
1657 space environment that is also compiled with EABI.
1659 Since there are major incompatibilities between the legacy ABI and
1660 EABI, especially with regard to structure member alignment, this
1661 option also changes the kernel syscall calling convention to
1662 disambiguate both ABIs and allow for backward compatibility support
1663 (selected with CONFIG_OABI_COMPAT).
1665 To use this you need GCC version 4.0.0 or later.
1668 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1669 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1672 This option preserves the old syscall interface along with the
1673 new (ARM EABI) one. It also provides a compatibility layer to
1674 intercept syscalls that have structure arguments which layout
1675 in memory differs between the legacy ABI and the new ARM EABI
1676 (only for non "thumb" binaries). This option adds a tiny
1677 overhead to all syscalls and produces a slightly larger kernel.
1678 If you know you'll be using only pure EABI user space then you
1679 can say N here. If this option is not selected and you attempt
1680 to execute a legacy ABI binary then the result will be
1681 UNPREDICTABLE (in fact it can be predicted that it won't work
1682 at all). If in doubt say Y.
1684 config ARCH_HAS_HOLES_MEMORYMODEL
1687 config ARCH_SPARSEMEM_ENABLE
1690 config ARCH_SPARSEMEM_DEFAULT
1691 def_bool ARCH_SPARSEMEM_ENABLE
1693 config ARCH_SELECT_MEMORY_MODEL
1694 def_bool ARCH_SPARSEMEM_ENABLE
1696 config HAVE_ARCH_PFN_VALID
1697 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1700 bool "High Memory Support"
1703 The address space of ARM processors is only 4 Gigabytes large
1704 and it has to accommodate user address space, kernel address
1705 space as well as some memory mapped IO. That means that, if you
1706 have a large amount of physical memory and/or IO, not all of the
1707 memory can be "permanently mapped" by the kernel. The physical
1708 memory that is not permanently mapped is called "high memory".
1710 Depending on the selected kernel/user memory split, minimum
1711 vmalloc space and actual amount of RAM, you may not need this
1712 option which should result in a slightly faster kernel.
1717 bool "Allocate 2nd-level pagetables from highmem"
1720 config HW_PERF_EVENTS
1721 bool "Enable hardware performance counter support for perf events"
1722 depends on PERF_EVENTS && CPU_HAS_PMU
1725 Enable hardware performance counter support for perf events. If
1726 disabled, perf events will use software events only.
1730 config FORCE_MAX_ZONEORDER
1731 int "Maximum zone order" if ARCH_SHMOBILE
1732 range 11 64 if ARCH_SHMOBILE
1733 default "9" if SA1111
1736 The kernel memory allocator divides physically contiguous memory
1737 blocks into "zones", where each zone is a power of two number of
1738 pages. This option selects the largest power of two that the kernel
1739 keeps in the memory allocator. If you need to allocate very large
1740 blocks of physically contiguous memory, then you may need to
1741 increase this value.
1743 This config option is actually maximum order plus one. For example,
1744 a value of 11 means that the largest free memory block is 2^10 pages.
1747 bool "Timer and CPU usage LEDs"
1748 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1749 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1750 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1751 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1752 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1753 ARCH_AT91 || ARCH_DAVINCI || \
1754 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1756 If you say Y here, the LEDs on your machine will be used
1757 to provide useful information about your current system status.
1759 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1760 be able to select which LEDs are active using the options below. If
1761 you are compiling a kernel for the EBSA-110 or the LART however, the
1762 red LED will simply flash regularly to indicate that the system is
1763 still functional. It is safe to say Y here if you have a CATS
1764 system, but the driver will do nothing.
1767 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1768 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1769 || MACH_OMAP_PERSEUS2
1771 depends on !GENERIC_CLOCKEVENTS
1772 default y if ARCH_EBSA110
1774 If you say Y here, one of the system LEDs (the green one on the
1775 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1776 will flash regularly to indicate that the system is still
1777 operational. This is mainly useful to kernel hackers who are
1778 debugging unstable kernels.
1780 The LART uses the same LED for both Timer LED and CPU usage LED
1781 functions. You may choose to use both, but the Timer LED function
1782 will overrule the CPU usage LED.
1785 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1787 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1788 || MACH_OMAP_PERSEUS2
1791 If you say Y here, the red LED will be used to give a good real
1792 time indication of CPU usage, by lighting whenever the idle task
1793 is not currently executing.
1795 The LART uses the same LED for both Timer LED and CPU usage LED
1796 functions. You may choose to use both, but the Timer LED function
1797 will overrule the CPU usage LED.
1799 config ALIGNMENT_TRAP
1801 depends on CPU_CP15_MMU
1802 default y if !ARCH_EBSA110
1803 select HAVE_PROC_CPU if PROC_FS
1805 ARM processors cannot fetch/store information which is not
1806 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1807 address divisible by 4. On 32-bit ARM processors, these non-aligned
1808 fetch/store instructions will be emulated in software if you say
1809 here, which has a severe performance impact. This is necessary for
1810 correct operation of some network protocols. With an IP-only
1811 configuration it is safe to say N, otherwise say Y.
1813 config UACCESS_WITH_MEMCPY
1814 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1815 depends on MMU && EXPERIMENTAL
1816 default y if CPU_FEROCEON
1818 Implement faster copy_to_user and clear_user methods for CPU
1819 cores where a 8-word STM instruction give significantly higher
1820 memory write throughput than a sequence of individual 32bit stores.
1822 A possible side effect is a slight increase in scheduling latency
1823 between threads sharing the same address space if they invoke
1824 such copy operations with large buffers.
1826 However, if the CPU data cache is using a write-allocate mode,
1827 this option is unlikely to provide any performance gain.
1831 prompt "Enable seccomp to safely compute untrusted bytecode"
1833 This kernel feature is useful for number crunching applications
1834 that may need to compute untrusted bytecode during their
1835 execution. By using pipes or other transports made available to
1836 the process as file descriptors supporting the read/write
1837 syscalls, it's possible to isolate those applications in
1838 their own address space using seccomp. Once seccomp is
1839 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1840 and the task is only allowed to execute a few safe syscalls
1841 defined by each seccomp mode.
1843 config CC_STACKPROTECTOR
1844 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1845 depends on EXPERIMENTAL
1847 This option turns on the -fstack-protector GCC feature. This
1848 feature puts, at the beginning of functions, a canary value on
1849 the stack just before the return address, and validates
1850 the value just before actually returning. Stack based buffer
1851 overflows (that need to overwrite this return address) now also
1852 overwrite the canary, which gets detected and the attack is then
1853 neutralized via a kernel panic.
1854 This feature requires gcc version 4.2 or above.
1856 config DEPRECATED_PARAM_STRUCT
1857 bool "Provide old way to pass kernel parameters"
1859 This was deprecated in 2001 and announced to live on for 5 years.
1860 Some old boot loaders still use this way.
1867 bool "Flattened Device Tree support"
1869 select OF_EARLY_FLATTREE
1872 Include support for flattened device tree machine descriptions.
1874 # Compressed boot loader in ROM. Yes, we really want to ask about
1875 # TEXT and BSS so we preserve their values in the config files.
1876 config ZBOOT_ROM_TEXT
1877 hex "Compressed ROM boot loader base address"
1880 The physical address at which the ROM-able zImage is to be
1881 placed in the target. Platforms which normally make use of
1882 ROM-able zImage formats normally set this to a suitable
1883 value in their defconfig file.
1885 If ZBOOT_ROM is not enabled, this has no effect.
1887 config ZBOOT_ROM_BSS
1888 hex "Compressed ROM boot loader BSS address"
1891 The base address of an area of read/write memory in the target
1892 for the ROM-able zImage which must be available while the
1893 decompressor is running. It must be large enough to hold the
1894 entire decompressed kernel plus an additional 128 KiB.
1895 Platforms which normally make use of ROM-able zImage formats
1896 normally set this to a suitable value in their defconfig file.
1898 If ZBOOT_ROM is not enabled, this has no effect.
1901 bool "Compressed boot loader in ROM/flash"
1902 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1904 Say Y here if you intend to execute your compressed kernel image
1905 (zImage) directly from ROM or flash. If unsure, say N.
1908 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1909 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1910 default ZBOOT_ROM_NONE
1912 Include experimental SD/MMC loading code in the ROM-able zImage.
1913 With this enabled it is possible to write the ROM-able zImage
1914 kernel image to an MMC or SD card and boot the kernel straight
1915 from the reset vector. At reset the processor Mask ROM will load
1916 the first part of the ROM-able zImage which in turn loads the
1917 rest the kernel image to RAM.
1919 config ZBOOT_ROM_NONE
1920 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1922 Do not load image from SD or MMC
1924 config ZBOOT_ROM_MMCIF
1925 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1927 Load image from MMCIF hardware block.
1929 config ZBOOT_ROM_SH_MOBILE_SDHI
1930 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1932 Load image from SDHI hardware block
1936 config ARM_APPENDED_DTB
1937 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1938 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1940 With this option, the boot code will look for a device tree binary
1941 (DTB) appended to zImage
1942 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1944 This is meant as a backward compatibility convenience for those
1945 systems with a bootloader that can't be upgraded to accommodate
1946 the documented boot protocol using a device tree.
1948 Beware that there is very little in terms of protection against
1949 this option being confused by leftover garbage in memory that might
1950 look like a DTB header after a reboot if no actual DTB is appended
1951 to zImage. Do not leave this option active in a production kernel
1952 if you don't intend to always append a DTB. Proper passing of the
1953 location into r2 of a bootloader provided DTB is always preferable
1956 config ARM_ATAG_DTB_COMPAT
1957 bool "Supplement the appended DTB with traditional ATAG information"
1958 depends on ARM_APPENDED_DTB
1960 Some old bootloaders can't be updated to a DTB capable one, yet
1961 they provide ATAGs with memory configuration, the ramdisk address,
1962 the kernel cmdline string, etc. Such information is dynamically
1963 provided by the bootloader and can't always be stored in a static
1964 DTB. To allow a device tree enabled kernel to be used with such
1965 bootloaders, this option allows zImage to extract the information
1966 from the ATAG list and store it at run time into the appended DTB.
1969 string "Default kernel command string"
1972 On some architectures (EBSA110 and CATS), there is currently no way
1973 for the boot loader to pass arguments to the kernel. For these
1974 architectures, you should supply some command-line options at build
1975 time by entering them here. As a minimum, you should specify the
1976 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1979 prompt "Kernel command line type" if CMDLINE != ""
1980 default CMDLINE_FROM_BOOTLOADER
1982 config CMDLINE_FROM_BOOTLOADER
1983 bool "Use bootloader kernel arguments if available"
1985 Uses the command-line options passed by the boot loader. If
1986 the boot loader doesn't provide any, the default kernel command
1987 string provided in CMDLINE will be used.
1989 config CMDLINE_EXTEND
1990 bool "Extend bootloader kernel arguments"
1992 The command-line arguments provided by the boot loader will be
1993 appended to the default kernel command string.
1995 config CMDLINE_FORCE
1996 bool "Always use the default kernel command string"
1998 Always use the default kernel command string, even if the boot
1999 loader passes other arguments to the kernel.
2000 This is useful if you cannot or don't want to change the
2001 command-line options your boot loader passes to the kernel.
2005 bool "Kernel Execute-In-Place from ROM"
2006 depends on !ZBOOT_ROM && !ARM_LPAE
2008 Execute-In-Place allows the kernel to run from non-volatile storage
2009 directly addressable by the CPU, such as NOR flash. This saves RAM
2010 space since the text section of the kernel is not loaded from flash
2011 to RAM. Read-write sections, such as the data section and stack,
2012 are still copied to RAM. The XIP kernel is not compressed since
2013 it has to run directly from flash, so it will take more space to
2014 store it. The flash address used to link the kernel object files,
2015 and for storing it, is configuration dependent. Therefore, if you
2016 say Y here, you must know the proper physical address where to
2017 store the kernel image depending on your own flash memory usage.
2019 Also note that the make target becomes "make xipImage" rather than
2020 "make zImage" or "make Image". The final kernel binary to put in
2021 ROM memory will be arch/arm/boot/xipImage.
2025 config XIP_PHYS_ADDR
2026 hex "XIP Kernel Physical Location"
2027 depends on XIP_KERNEL
2028 default "0x00080000"
2030 This is the physical address in your flash memory the kernel will
2031 be linked for and stored to. This address is dependent on your
2035 bool "Kexec system call (EXPERIMENTAL)"
2036 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2038 kexec is a system call that implements the ability to shutdown your
2039 current kernel, and to start another kernel. It is like a reboot
2040 but it is independent of the system firmware. And like a reboot
2041 you can start any kernel with it, not just Linux.
2043 It is an ongoing process to be certain the hardware in a machine
2044 is properly shutdown, so do not be surprised if this code does not
2045 initially work for you. It may help to enable device hotplugging
2049 bool "Export atags in procfs"
2053 Should the atags used to boot the kernel be exported in an "atags"
2054 file in procfs. Useful with kexec.
2057 bool "Build kdump crash kernel (EXPERIMENTAL)"
2058 depends on EXPERIMENTAL
2060 Generate crash dump after being started by kexec. This should
2061 be normally only set in special crash dump kernels which are
2062 loaded in the main kernel with kexec-tools into a specially
2063 reserved region and then later executed after a crash by
2064 kdump/kexec. The crash dump kernel must be compiled to a
2065 memory address not used by the main kernel
2067 For more details see Documentation/kdump/kdump.txt
2069 config AUTO_ZRELADDR
2070 bool "Auto calculation of the decompressed kernel image address"
2071 depends on !ZBOOT_ROM && !ARCH_U300
2073 ZRELADDR is the physical address where the decompressed kernel
2074 image will be placed. If AUTO_ZRELADDR is selected, the address
2075 will be determined at run-time by masking the current IP with
2076 0xf8000000. This assumes the zImage being placed in the first 128MB
2077 from start of memory.
2081 menu "CPU Power Management"
2085 source "drivers/cpufreq/Kconfig"
2088 tristate "CPUfreq driver for i.MX CPUs"
2089 depends on ARCH_MXC && CPU_FREQ
2091 This enables the CPUfreq driver for i.MX CPUs.
2093 config CPU_FREQ_SA1100
2096 config CPU_FREQ_SA1110
2099 config CPU_FREQ_INTEGRATOR
2100 tristate "CPUfreq driver for ARM Integrator CPUs"
2101 depends on ARCH_INTEGRATOR && CPU_FREQ
2104 This enables the CPUfreq driver for ARM Integrator CPUs.
2106 For details, take a look at <file:Documentation/cpu-freq>.
2112 depends on CPU_FREQ && ARCH_PXA && PXA25x
2114 select CPU_FREQ_TABLE
2115 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2120 Internal configuration node for common cpufreq on Samsung SoC
2122 config CPU_FREQ_S3C24XX
2123 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2124 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2127 This enables the CPUfreq driver for the Samsung S3C24XX family
2130 For details, take a look at <file:Documentation/cpu-freq>.
2134 config CPU_FREQ_S3C24XX_PLL
2135 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2136 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2138 Compile in support for changing the PLL frequency from the
2139 S3C24XX series CPUfreq driver. The PLL takes time to settle
2140 after a frequency change, so by default it is not enabled.
2142 This also means that the PLL tables for the selected CPU(s) will
2143 be built which may increase the size of the kernel image.
2145 config CPU_FREQ_S3C24XX_DEBUG
2146 bool "Debug CPUfreq Samsung driver core"
2147 depends on CPU_FREQ_S3C24XX
2149 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2151 config CPU_FREQ_S3C24XX_IODEBUG
2152 bool "Debug CPUfreq Samsung driver IO timing"
2153 depends on CPU_FREQ_S3C24XX
2155 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2157 config CPU_FREQ_S3C24XX_DEBUGFS
2158 bool "Export debugfs for CPUFreq"
2159 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2161 Export status information via debugfs.
2165 source "drivers/cpuidle/Kconfig"
2169 menu "Floating point emulation"
2171 comment "At least one emulation must be selected"
2174 bool "NWFPE math emulation"
2175 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2177 Say Y to include the NWFPE floating point emulator in the kernel.
2178 This is necessary to run most binaries. Linux does not currently
2179 support floating point hardware so you need to say Y here even if
2180 your machine has an FPA or floating point co-processor podule.
2182 You may say N here if you are going to load the Acorn FPEmulator
2183 early in the bootup.
2186 bool "Support extended precision"
2187 depends on FPE_NWFPE
2189 Say Y to include 80-bit support in the kernel floating-point
2190 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2191 Note that gcc does not generate 80-bit operations by default,
2192 so in most cases this option only enlarges the size of the
2193 floating point emulator without any good reason.
2195 You almost surely want to say N here.
2198 bool "FastFPE math emulation (EXPERIMENTAL)"
2199 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2201 Say Y here to include the FAST floating point emulator in the kernel.
2202 This is an experimental much faster emulator which now also has full
2203 precision for the mantissa. It does not support any exceptions.
2204 It is very simple, and approximately 3-6 times faster than NWFPE.
2206 It should be sufficient for most programs. It may be not suitable
2207 for scientific calculations, but you have to check this for yourself.
2208 If you do not feel you need a faster FP emulation you should better
2212 bool "VFP-format floating point maths"
2213 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2215 Say Y to include VFP support code in the kernel. This is needed
2216 if your hardware includes a VFP unit.
2218 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2219 release notes and additional status information.
2221 Say N if your target does not have VFP hardware.
2229 bool "Advanced SIMD (NEON) Extension support"
2230 depends on VFPv3 && CPU_V7
2232 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2237 menu "Userspace binary formats"
2239 source "fs/Kconfig.binfmt"
2242 tristate "RISC OS personality"
2245 Say Y here to include the kernel code necessary if you want to run
2246 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2247 experimental; if this sounds frightening, say N and sleep in peace.
2248 You can also say M here to compile this support as a module (which
2249 will be called arthur).
2253 menu "Power management options"
2255 source "kernel/power/Kconfig"
2257 config ARCH_SUSPEND_POSSIBLE
2258 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2259 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2260 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2263 config ARM_CPU_SUSPEND
2268 source "net/Kconfig"
2270 source "drivers/Kconfig"
2274 source "arch/arm/Kconfig.debug"
2276 source "security/Kconfig"
2278 source "crypto/Kconfig"
2280 source "lib/Kconfig"